CN105529270A - 具有硅侧壁间隔件的金属栅极 - Google Patents

具有硅侧壁间隔件的金属栅极 Download PDF

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CN105529270A
CN105529270A CN201510674125.7A CN201510674125A CN105529270A CN 105529270 A CN105529270 A CN 105529270A CN 201510674125 A CN201510674125 A CN 201510674125A CN 105529270 A CN105529270 A CN 105529270A
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layer
diffusion barrier
barrier layer
dielectric
gate
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CN105529270B (zh
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方文翰
巫柏奇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

方法包括在电介质中形成开口以呈现突出的半导体鳍，在突出的半导体鳍的侧壁和顶面上形成栅极电介质，以及在栅极电介质上方形成导电扩散阻挡层。导电扩散阻挡层延伸至开口内。该方法还包括形成位于导电扩散阻挡层上方并且延伸至开口内的硅层，以及对硅层实施干蚀刻以去除硅层的水平部分和垂直部分。在干蚀刻之后，形成位于导电扩散阻挡层上方并且延伸至开口内的导电层。本发明的实施例还涉及具有硅侧壁间隔件的金属栅极。

Description

具有硅侧壁间隔件的金属栅极
优先权声明和交叉引用
本申请要求2014年10月17日提交的标题为“MethodofFormingaGateElectrodeforTransistor”的以下临时提交的美国专利申请第62/065，191号的权益，其全部内容结合于此作为参考。
技术领域
本发明的实施例涉及集成电路器件，更具体地，涉及具有硅侧壁间隔件的金属栅极。
背景技术
金属氧化物半导体(MOS)器件是集成电路中的基建元件。现有的MOS器件通常具有包括多晶硅的栅电极，使用诸如离子注入或热扩散的掺杂操作使多晶硅掺杂有p型或n型杂质。栅电极的功函数可以调整为硅的带边。对于n型金属氧化物半导体(NMOS)器件，功函数可以调整为接近硅的导电带。对于p型金属氧化物半导体(PMOS)器件，功函数可以调整为接近硅的价带。可以通过选择适当的杂质实现调整多晶硅栅电极的功函数。
具有多晶硅栅电极的MOS器件展示出载流子耗尽效应，载流子耗尽效应也称为多晶硅耗尽效应。当施加的电场从接近栅极电介质的栅极区清除载流子时，发生多晶硅耗尽效应，从而形成耗尽层。在n掺杂的多晶硅层中，耗尽层包括离子化的非移动供体位点，其中，在p掺杂的多晶硅层中，耗尽层包括离子化的非移动受体位点。耗尽效应导致有效栅极电介质厚度的增加，从而使得在半导体的表面处更加难以产生反型层。
可以通过形成金属栅电极来解决多晶硅耗尽问题，其中，用于NMOS器件和PMOS器件的金属栅极也可以具有带边功函数。因此，产生的金属栅极包括多个层以适合于NMOS器件和PMOS器件的需求。
发明内容
本发明的实施例提供了一种方法，包括：在电介质中形成开口以呈现突出的半导体鳍；在所述突出的半导体鳍的侧壁和顶面上形成栅极电介质；在所述栅极电介质上方形成导电扩散阻挡层，其中，所述导电扩散阻挡层延伸至所述开口内；形成位于所述导电扩散阻挡层上方并且延伸至所述开口内的硅层；对所述硅层实施干蚀刻以去除所述硅层的水平部分和垂直部分；以及在所述干蚀刻之后，形成位于所述导电扩散阻挡层上方并且延伸至所述开口内的导电层。
本发明的另一实施例提供了一种方法，包括：去除伪栅极堆叠件以在层间电介质中形成开口；在所述开口中的突出的半导体鳍的侧壁和顶面上形成栅极电介质；在所述栅极电介质上方形成导电扩散阻挡层，其中，所述导电扩散阻挡层延伸至所述开口内；形成位于所述导电扩散阻挡层上方并且延伸至所述开口内的多晶硅层；对所述多晶硅层和所述栅极电介质实施退火；在所述退火之后，对所述多晶硅层实施各向异性蚀刻以在所述开口的拐角处形成多晶硅拐角间隔件，其中，形成聚合物以覆盖所述多晶硅拐角间隔件；蚀刻所述聚合物，其中，所述多晶硅拐角间隔件在所述蚀刻之后保留；以及在所述各向异性蚀刻之后，在所述导电扩散阻挡层和所述多晶硅拐角间隔件上方形成导电层。
本发明的又一实施例提供了一种器件，包括：隔离区；突出的半导体鳍，位于所述隔离区的顶面上方；以及栅极堆叠件，位于所述突出的半导体鳍的顶面和侧壁上，其中，所述栅极堆叠件包括：栅极电介质；导电扩散阻挡层，位于所述栅极电介质上方；硅拐角间隔件，位于所述导电扩散阻挡层上方，其中，所述硅拐角间隔件位于所述导电扩散阻挡层的底部拐角处；以及导电层，位于所述硅拐角间隔件上方并且与所述硅拐角间隔件接触，其中，所述导电扩散阻挡层、所述硅拐角间隔件和所述导电层形成栅电极的部分。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图15A示出了根据一些实施例的在鳍式场效应晶体管(FinFET)的形成中的中间阶段的截面图；
图15B示出了根据一些实施例的FinFET的另一截面图，其中，从FinFET的沟道长度方向获得截面图；
图16示出了根据一些实施例的FinFET的部分的顶视图；以及
图17示出了根据一些实施例的用于形成FinFET的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…下面”、“在…下方”、“下部”、“在…上面”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
根据各个示例性实施例，提供了鳍式场效应晶体管(FinFET)及其形成方法。示出了形成FinFET的中间阶段。讨论了实施例的变化。贯穿各个视图和说明性实施例，相同的参考标号用于标示相同的元件。
图1至图15A示出了根据一些实施例的在FinFET的形成中的中间阶段的截面图。在如图17所示的工艺流程图中也示意性地示出了图1至图15A中示出的步骤。在随后的讨论中，参照图17中的工艺步骤讨论图1至图15A中示出的工艺步骤。
图1示出了初始结构的立体图。初始结构包括晶圆100，晶圆100进一步包括衬底20。衬底20可以是半导体衬底，半导体衬底可以进一步为硅衬底、硅锗衬底或由其他半导体材料形成的衬底。衬底20可以掺杂有p型杂质或n型杂质。诸如浅沟槽隔离(STI)区的隔离区22可以形成为从衬底20的顶面延伸至衬底20内，其中，衬底20的顶面是晶圆100的主要表面100A。位于相邻的STI区22之间的衬底20的部分称为半导体鳍24。半导体鳍24的顶面和STI区22的顶面可以基本上彼此齐平。
STI区22可以包括可以使用例如高密度等离子体(HDP)化学汽相沉积(CVD)形成的氧化硅。STI区22也可以包括由可流动化学汽相沉积(FCVD)、旋涂等形成的氧化物。
参照图2，使STI区22凹进，从而使得半导体鳍24的顶部高于STI区22的顶面以形成突出鳍24’。相应的步骤示出为如图17所示的工艺流程图200中的步骤202。可以使用干蚀刻工艺实施蚀刻，其中，HF和NH3用作蚀刻气体。在可选实施例中，蚀刻气体包括NF3和NH3。在蚀刻工艺期间，可以生成等离子体。在示例性蚀刻工艺中，蚀刻气体的压力介于约100毫托和约200毫托的范围内。HF的流量可以介于约50sccm和约150sccm的范围内。NH3的流量可以介于约50sccm和约150sccm的范围内。也可以包括氩气，其中氩气的流量介于约20sccm和约100sccm的范围内。在可选实施例中，使用湿蚀刻工艺实施STI区22的凹进。例如，蚀刻化学物质可以包括稀释的HF。
参照图3，在突出鳍24’的顶面和侧壁上形成栅极堆叠件29。相应的步骤示出为如图17所示的工艺流程图200中的步骤204。栅极堆叠件29包括栅极电介质27和位于栅极电介质27上方的栅电极26。例如，可以使用多晶硅形成栅电极26，但是也可以使用其他材料。栅极堆叠件29也可以包括位于栅电极26上方的硬掩模层(未示出)，其中，例如，硬掩模层可以由氧化硅形成。栅极堆叠件29可以横跨在单个或多个突出鳍24’和/或STI区22上方。栅极堆叠件29的纵向也可以基本上垂直于突出鳍24’的纵向。根据本发明的一些实施例，栅极堆叠件29是伪栅极堆叠件并且将在随后的步骤中被替换栅极代替。
接下来，在栅极堆叠件29的侧壁上形成栅极间隔件28。根据本发明的一些实施例，栅极间隔件28由诸如碳氮化硅(SiCN)、氮化硅等的介电材料形成并且可以具有单层结构或多层结构。栅极间隔件28也可以具有包括多个介电层的复合结构。
然后实施蚀刻步骤(在下文中称为源极/漏极凹进)以蚀刻未由栅极堆叠件29和栅极间隔件28覆盖的突出鳍24’的部分，从而产生图4中示出的结构。该凹进可以是各向异性的，并且因此直接位于栅极堆叠件29和栅极间隔件28下面的半导体鳍24的部分受到保护并且不被蚀刻。凹进的半导体鳍24的顶面24A低于STI区22的顶面22A。因此，在STI区22之间形成凹槽31。凹槽31位于栅极堆叠件29的相对侧上。
接下来，通过在凹槽31中选择性地生长半导体材料而形成外延区30，从而产生图5中的结构。图4和图5中示出的步骤示出为如图17所示的工艺流程图200中的步骤206。在一些示例性实施例中，外延区30包括硅锗或硅。取决于产生的FinFET是p型FinFET还是n型FinFET，随着外延的进行可以原位掺杂p型或n型杂质。例如，当产生的FinFET是p型FinFET时，可以生长SiGeB。相反地，当产生的FinFET是n型FinFET时，可以生长SiP。在可选实施例中，外延区30包括III-V族化合物半导体，诸如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、它们的组合或它们的多层。在用外延区30填充凹槽31之后，外延区30的进一步外延生长使得外延区30水平扩展，并且可以开始形成小平面。此外，由于外延区30的横向生长，STI区22的一些顶面22A位于外延区30的一些部分下面并且与外延区30的一些部分对准。
在外延步骤之后，外延区30可以进一步注入有p型或n型杂质以形成源极和漏极区，使用参考标号30标示源极和漏极区。在可选实施例中，由于p型或n型杂质的原位掺杂，在外延期间形成源极和漏极区，所以跳过注入步骤。源极和漏极区30位于栅极堆叠件29的相对侧上，并且可以位于STI区22的表面22A的部分上面并且与STI区22的表面22A的部分重叠。外延区30包括形成在STI区22中的下部30A和形成在STI区22的顶面22A上方的上部30B。下部30A的侧壁成形为凹槽31(图4)的形状，下部30A可以具有(基本上)笔直的边缘，该笔直的边缘也可以是与衬底20的主要表面(诸如底面)垂直的垂直边缘。例如，下部30A的侧壁的倾斜角θ可以介于约80度和约90度的范围内。
图6示出了在形成层间电介质(ILD)36之后的结构的立体图。相应的步骤示出为如图17所示的工艺流程图200中的步骤208。根据本发明的一些实施例，在形成ILD36之前，在源极和漏极区30上形成缓冲氧化物层(未示出)和接触蚀刻停止层(CESL，未示出)。根据本发明的一些实施例，缓冲氧化物层包括氧化硅，并且CESL可以包括氮化硅、碳氮化硅等。例如，可以使用原子层沉积(ALD)形成缓冲氧化物层和CESL。例如，ILD36可以包括使用可流动化学汽相沉积(FCVD)形成的可流动氧化物。ILD36也可以包括磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、正硅酸乙酯(TEOS)氧化物等。可以实施化学机械抛光(CMP)以使ILD36、栅极堆叠件29和栅极间隔件28的顶面彼此齐平。
在随后的步骤中，去除ILD36的部分36A以形成接触开口。然后在外延区30的表面上形成源极/漏极硅化物区44(图7)。形成工艺包括将金属层沉积至接触开口内，实施退火以使金属层与外延区30的暴露表面部分反应以形成硅化物区44，以及然后去除金属层中的未反应金属。然后在接触开口内填充诸如钨的导电材料以形成接触插塞42。
接下来，如图8至图15A所示，用金属栅极和替换栅极电介质代替包括伪栅电极26和伪栅极电介质27的伪栅极堆叠件。从图7中的包含线A-A的相同的垂直面获得图8至图15A中示出的截面图。
首先，如图8所示，去除伪栅电极26和伪栅极电介质27，从而形成开口46。相应的步骤示出为如图17所示的工艺流程图200中的步骤210。突出鳍24’的顶面和侧壁暴露于开口46。
接下来，参照图9，形成栅极电介质47。根据本发明的一些实施例，栅极电介质47包括作为下部的界面层(IL)48。IL48形成在突出鳍24’的暴露表面上。IL48可以包括诸如氧化硅层的氧化物层，通过突出鳍24’的热氧化、化学氧化工艺或沉积工艺形成该氧化物层。栅极电介质47也可以包括形成在IL48上方的高k介电层50。高k介电层50包括诸如氧化铪、氧化镧、氧化铝、氧化锆等的高k介电材料。高k介电材料的介电常数(k值)高于3.9，并且可以高于约7.0，并且有时高达21.0或更高。高k介电层位于IL48上面并且可以与IL48接触。高k介电层50形成为共形层，并且在突出鳍24’的侧壁上以及ILD36的顶面和侧壁上延伸。
再次参照图9，在栅极介电层47上方形成导电扩散阻挡层52。根据本发明的一些实施例，扩散阻挡层52包括TiN。TiN层的厚度可以小于约并且可以介于约和约的范围内。可选择地，可以在TiN层上方形成TaN层(扩散阻挡层52的上部)。根据一些实施例，TaN层的厚度可以低于约扩散阻挡层52包括位于开口46的底部处的底部(其是水平部分)和与高k介电层50接触的侧壁部(其是垂直部分)。图9中示出的步骤示出为如图17所示的工艺流程图200中的步骤212。
接下来，实施处理以改进导电扩散阻挡层52在随后的处理步骤期间阻止氧渗透的能力。在一些实施例中，处理包括去耦等离子体氮化(DPN)工艺和随后的退火工艺。可以使用诸如N2、NH3等的含氮工艺气体实施DPN。例如，可以在约800℃至约1000℃的温度下实施退火并且持续约1毫秒至约50秒。通过处理，沿着导电扩散阻挡层52和栅极介电层47之间的界面的导电扩散阻挡层52中的氮浓度增大。
接下来，如图10所示，在扩散阻挡层52上方沉积多晶硅覆盖层54。相应的步骤示出为如图17所示的工艺流程图200中的步骤214。贯穿说明书，根据其他实施例，虽然覆盖层54称为多晶硅覆盖层，但是覆盖层54也可以包括非晶硅。多晶硅覆盖层54可以使用化学汽相沉积(CVD)沉积并且形成为共形层，多晶硅覆盖层54的水平部分的厚度T1接近垂直部分的厚度T2。例如，厚度差|T1-T2|可以小于厚度T1或T2的约20％。厚度T1和T2可以介于约和约的范围内。根据本发明的一些实施例，多晶硅覆盖层54未掺杂有诸如硼、铟、磷、砷和锑的p型和n型杂质。
多晶硅覆盖层54形成为牺牲层，并且用于在随后的覆盖后退火期间保护扩散阻挡层52和高k介电层50。因此，在随后的整个覆盖后退火期间，多晶硅覆盖层54位于扩散阻挡层52上方。根据一些实施例，在介于约350℃和约750℃的范围内的温度下实施覆盖后退火。实施退火的时间周期可以介于约20秒和约60秒的范围内。可以使用熔炉退火、激光退火、RTA等实施覆盖后退火。
在覆盖后退火之后，实施各向异性蚀刻以去除多晶硅覆盖层54，并且图11中示出了产生的结构。根据一些实施例，使用干蚀刻工艺实施各向异性蚀刻。相应的步骤示出为如图17所示的工艺流程图200中的步骤216。在各向异性蚀刻中，打开等离子体。根据本发明的一些实施例，工艺气体包括作为蚀刻气体以用于去除多晶硅的HBr和NF3。此外，工艺气体包括用于在开口46的底部拐角处沉积聚合物56的沉积气体。根据一些示例性实施例，沉积气体包括诸如CH4的含碳和氢的气体，其中，含碳和氢的气体用于生成含碳聚合物56。也可以在工艺气体中添加氩气。聚合物56沉积至开口46的底部拐角，而在诸如扩散阻挡层52的大部分侧壁和底面的其他部分中，沉积较少聚合物56或基本上未沉积聚合物56。在各向异性蚀刻中，聚合物56保护多晶硅层54的拐角部分免受蚀刻。因此，在各向异性蚀刻之后，多晶硅层54的一些拐角部分54A和54B保留未被去除，并且在下文中称为多晶硅拐角间隔件54(包括54A和54B)。多晶硅拐角间隔件54A位于ILD36的侧壁上，并且多晶硅间隔件54B位于突出鳍24’的侧壁上。根据一些实施例，拐角间隔件54A和54B也可以包括非晶硅。
在以上讨论的用于去除多晶硅层54的工艺中，采用干蚀刻工艺。虽然湿蚀刻也能够去除多晶硅覆盖层54，但是湿蚀刻是各项同性的。此外，湿蚀刻在多晶硅的一些晶格方向上具有高蚀刻速率。因此，如果湿蚀刻用于去除多晶硅覆盖层54，则将完全去除多晶硅的拐角部分，从而暴露出扩散阻挡层52和高k介电层50的拐角部分。结果，可以蚀刻扩散阻挡层52和高k介电层50的拐角部分，并且因此暴露出邻近的突出鳍24’。这可以导致随后填充的栅极金属(诸如钨或钴)形成朝着突出鳍24’的突出件，并且产生的栅极可能潜在地与突出鳍24’短路。在本发明的实施例中，通过使用各向异性蚀刻和进一步添加沉积气体，避免不期望地形成突出件。
图12示出了聚合物56的去除，使用湿蚀刻实施聚合物56的去除。相应的步骤示出为如图17所示的工艺流程图200中的步骤218。选择蚀刻剂，使得在湿蚀刻中，去除聚合物56，并且多晶硅拐角间隔件54A和54B以及扩散阻挡层52未被蚀刻。根据本发明的一些实施例，使用包括HF和NH3的化学物质实施湿蚀刻。
图13至图15A示出了用于形成金属栅极的剩余的形成步骤。相应的步骤示出为如图17所示的工艺流程图200中的步骤220。图13示出了在硅拐角间隔件54A和54B以及扩散阻挡层52上方形成额外的导电层58。导电层58包括与多晶硅拐角间隔件54A和54B接触的一些部分以及与扩散阻挡层52接触的其他部分。而且，多晶硅拐角间隔件54A和54B将扩散阻挡层52的拐角部分与导电层58分隔开。此外，扩散阻挡层52和导电层58组合形成包封件，该包封件将多晶硅拐角间隔件54A和54B完全封闭(和密封)在其中。根据本发明的一些实施例，导电层58包括TaN，TaN也可以用作扩散阻挡层。在可选实施例中，诸如TiAl、TiN、Co、Al等的其他材料可以用于形成导电层58。
图13也示出了导电层60的形成，由于导电层60设置产生的FinFET的功函数，所以导电层60有时称为功函金属。在产生的FinFET是n型FinFET的实施例中，导电层60可以是TiAl层。在产生的FinFET是p型FinFET的可选实施例中，导电层60可以是TiN层，其中，TiAl层可以形成在TiN层上方。例如，形成方法可以包括物理汽相沉积(PVD)。
接下来，形成层62以填充凹槽46，并且图14中示出了产生的结构。根据一些示例性实施例，随后形成的金属层62包括阻挡层、润湿层和填充金属。在一些实施例中，阻挡层可以包括TiN，可以使用PVD形成阻挡层。润湿层可以是钴层，可以使用CVD形成润湿层。填充金属可以包括铝或铝合金，也可以使用PVD、CVD等形成填充金属。可以回流填充金属以完全填充如图13中的剩余的凹槽46。
图15A示出了用于去除位于ILD层36上方的层50、52、56、58、60和62的过量部分的平坦化步骤(例如，CMP)。层48、50、52、56、58、60和62的剩余部分以及多晶硅拐角间隔件54A和54B组合形成替换栅极堆叠件64。层50、52、56、58、60的每个剩余部分包括底部以及位于底部上方并且连接至底部的侧壁部分。因此形成FinFET66。
在示出的实施例中，在形成替换栅极64之前形成源极/漏极接触插塞42。根据本发明的可选实施例，也可以在形成替换栅极64之后形成源极/漏极接触插塞42。
图15A示出了从与突出鳍24’的纵向垂直的平面获得的截面图。例如，图15A示出了从图7中的包含线A-A的垂直平面获得的截面图(除了图7中示出的伪栅极已被替换栅极代替之外)。图15B示出了从与突出鳍24’的纵向平行的平面获得的截面图，其中，该平面是图7中的包含线B-B的相同的平面。图15B示出，也可以在接近源极/漏极区68的相对端上形成多晶硅拐角间隔件54A和54B。
图16示出了FinFET66的顶视图，其中，示出了替换栅极64和突出鳍24’，而未示出FinFET66的其他组件。示出了可能形成多晶硅拐角间隔件54的位置并且标记为54。多晶硅拐角间隔件54A和54B可以形成全环、部分环或与示出的环对准的隔离部分。
图16也示出了形成在突出鳍24’的顶部上的多晶硅拐角间隔件54C。多晶硅拐角间隔件54C也位于形成在扩散阻挡层52(图15A)的水平部分和垂直部分之间的拐角处，除了扩散阻挡层52的相应的水平部分位于突出鳍24’的顶部上。而且，多晶硅拐角间隔件54C可以与多晶硅拐角间隔件54A和54B物理分离。
应该理解，多晶硅拐角间隔件54的形成受到各个工艺条件的影响，并且多晶硅拐角间隔件54的实际位置和尺寸受到工艺变化的影响。因此，多晶硅拐角间隔件54非常可能但不是必须出现在标记的拐角区的所有或一些部分中。因此，在实际的晶圆上，多晶硅拐角间隔件54可以形成(或不形成)在如图16所示的位置的所有或任何部分中，并且可以形成为分离的间隔件。
本发明的实施例具有一些有利特征。通过使用干蚀刻来去除用于使扩散阻挡层和高k介电层退火的牺牲多晶硅，避免了扩散阻挡层和高k介电层的拐角部分的不期望的去除。结果，避免了由于扩散阻挡层和高k介电层的拐角部分的不期望的去除而形成的金属栅极突出件。
根据本发明的一些实施例，方法包括在电介质中形成开口以呈现突出的半导体鳍，在突出的半导体鳍的侧壁和顶面上形成栅极电介质，以及在栅极电介质上方形成导电扩散阻挡层。导电扩散阻挡层延伸至开口内。该方法还包括形成位于导电扩散阻挡层上方并且延伸至开口内的硅层，以及对硅层实施干蚀刻以去除硅层的水平部分和垂直部分。在干蚀刻之后，形成位于导电扩散阻挡层上方并且延伸至开口内的导电层。
在上述方法中，其中，所述干蚀刻是各向异性的。
在上述方法中，其中，用包括蚀刻气体和沉积气体的工艺气体实施所述干蚀刻。
在上述方法中，其中，用包括蚀刻气体和沉积气体的工艺气体实施所述干蚀刻，所述沉积气体包括含碳和氢的气体。
在上述方法中，还包括：在所述干蚀刻之后和在形成所述导电层之前，实施湿蚀刻以去除在所述干蚀刻中形成的聚合物，其中，所述聚合物沉积在所述开口的底部拐角处。
在上述方法中，其中，在所述干蚀刻之后，所述硅层包括保留在所述开口的底部拐角处的硅拐角间隔件。
在上述方法中，其中，在所述干蚀刻之后，所述硅层包括保留在所述开口的底部拐角处的硅拐角间隔件，所述导电扩散阻挡层和所述导电层均与所述硅拐角间隔件物理接触。
根据本发明的可选实施例，一种方法包括去除伪栅极堆叠件以在层间电介质中形成开口，在开口中的突出的半导体鳍的侧壁和顶面上形成栅极电介质，以及在栅极电介质上方形成导电扩散阻挡层。导电扩散阻挡层延伸至开口内。该方法还包括形成位于导电扩散阻挡层上方并且延伸至开口内的多晶硅层，以及对多晶硅层和栅极电介质实施退火。在退火之后，对多晶硅层实施各向异性蚀刻以在开口的拐角处形成多晶硅拐角间隔件，其中，形成聚合物以覆盖多晶硅拐角间隔件。然后蚀刻聚合物，其中在蚀刻之后保留多晶硅拐角间隔件。在各向异性蚀刻之后，在导电扩散阻挡层和多晶硅拐角间隔件上方形成导电层。
在上述方法中，其中，在所述各向异性蚀刻以及蚀刻所述聚合物之后，去除所述多晶硅层的水平部分和垂直部分，并且暴露出所述导电扩散阻挡层的顶面和侧壁表面，其中，所述导电扩散阻挡层的顶面和侧壁表面位于所述开口中。
在上述方法中，其中，所述导电扩散阻挡层和所述导电层均与所述多晶硅拐角间隔件物理接触。
在上述方法中，其中，所述导电扩散阻挡层和所述导电层彼此物理接触。
在上述方法中，其中，所述各向异性蚀刻是干蚀刻，并且使用湿蚀刻实施蚀刻所述聚合物。
在上述方法中，其中，所述多晶硅拐角间隔件未掺杂有p型和n型杂质。
根据本发明的又可选实施例，一种器件包括隔离区、位于隔离区的顶面上方的突出的半导体鳍、位于突出的半导体鳍的顶面和侧壁上的栅极堆叠件。栅极堆叠件包括栅极电介质、位于栅极电介质上方的导电扩散阻挡层、位于导电扩散阻挡层上方的硅拐角间隔件，其中，硅拐角间隔件位于导电扩散阻挡层的底部拐角处，并且导电层位于硅拐角间隔件上方并且与硅拐角间隔件接触，其中，导电扩散阻挡层、硅拐角间隔件和导电层形成栅电极的部分。
在上述器件中，其中，所述导电扩散阻挡层和所述导电层组合完全封闭所述硅拐角间隔件。
在上述器件中，其中，所述导电扩散阻挡层包括TiN，并且所述导电层包括TaN，其中，所述TiN和所述TaN与所述硅拐角间隔件接触并且彼此接触。
在上述器件中，还包括：层间电介质，位于所述栅电极的相对侧上。
在上述器件中，其中，所述硅拐角间隔件未掺杂有p型和n型杂质。
在上述器件中，其中，所述导电扩散阻挡层包括与所述导电层的第一部分物理接触的第一部分。
在上述器件中，其中，所述导电扩散阻挡层的第一部分与所述导电层的第一部分是水平部分，并且其中，所述导电扩散阻挡层还包括与所述导电层的第二部分物理接触的第二部分，其中，所述导电扩散阻挡层的第二部分与所述导电层的第二部分是垂直部分。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种方法，包括：
在电介质中形成开口以呈现突出的半导体鳍；
在所述突出的半导体鳍的侧壁和顶面上形成栅极电介质；
在所述栅极电介质上方形成导电扩散阻挡层，其中，所述导电扩散阻挡层延伸至所述开口内；
形成位于所述导电扩散阻挡层上方并且延伸至所述开口内的硅层；
对所述硅层实施干蚀刻以去除所述硅层的水平部分和垂直部分；以及
在所述干蚀刻之后，形成位于所述导电扩散阻挡层上方并且延伸至所述开口内的导电层。
2.根据权利要求1所述的方法，其中，所述干蚀刻是各向异性的。
3.根据权利要求1所述的方法，其中，用包括蚀刻气体和沉积气体的工艺气体实施所述干蚀刻。
4.根据权利要求3所述的方法，其中，所述沉积气体包括含碳和氢的气体。
5.根据权利要求1所述的方法，还包括：
在所述干蚀刻之后和在形成所述导电层之前，实施湿蚀刻以去除在所述干蚀刻中形成的聚合物，其中，所述聚合物沉积在所述开口的底部拐角处。
6.根据权利要求1所述的方法，其中，在所述干蚀刻之后，所述硅层包括保留在所述开口的底部拐角处的硅拐角间隔件。
7.根据权利要求6所述的方法，其中，所述导电扩散阻挡层和所述导电层均与所述硅拐角间隔件物理接触。
8.一种方法，包括：
去除伪栅极堆叠件以在层间电介质中形成开口；
在所述开口中的突出的半导体鳍的侧壁和顶面上形成栅极电介质；
在所述栅极电介质上方形成导电扩散阻挡层，其中，所述导电扩散阻挡层延伸至所述开口内；
形成位于所述导电扩散阻挡层上方并且延伸至所述开口内的多晶硅层；
对所述多晶硅层和所述栅极电介质实施退火；
在所述退火之后，对所述多晶硅层实施各向异性蚀刻以在所述开口的拐角处形成多晶硅拐角间隔件，其中，形成聚合物以覆盖所述多晶硅拐角间隔件；
蚀刻所述聚合物，其中，所述多晶硅拐角间隔件在所述蚀刻之后保留；以及
在所述各向异性蚀刻之后，在所述导电扩散阻挡层和所述多晶硅拐角间隔件上方形成导电层。
9.根据权利要求8所述的方法，其中，在所述各向异性蚀刻以及蚀刻所述聚合物之后，去除所述多晶硅层的水平部分和垂直部分，并且暴露出所述导电扩散阻挡层的顶面和侧壁表面，其中，所述导电扩散阻挡层的顶面和侧壁表面位于所述开口中。
10.一种器件，包括：
隔离区；
突出的半导体鳍，位于所述隔离区的顶面上方；以及
栅极堆叠件，位于所述突出的半导体鳍的顶面和侧壁上，其中，所述栅极堆叠件包括：
栅极电介质；
导电扩散阻挡层，位于所述栅极电介质上方；
硅拐角间隔件，位于所述导电扩散阻挡层上方，其中，所述硅拐角间隔件位于所述导电扩散阻挡层的底部拐角处；以及
导电层，位于所述硅拐角间隔件上方并且与所述硅拐角间隔件接触，其中，所述导电扩散阻挡层、所述硅拐角间隔件和所述导电层形成栅电极的部分。
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