CN105529258B - Stablize the process of gate topography in RFLDMOS technique - Google Patents
Stablize the process of gate topography in RFLDMOS technique Download PDFInfo
- Publication number
- CN105529258B CN105529258B CN201610064060.9A CN201610064060A CN105529258B CN 105529258 B CN105529258 B CN 105529258B CN 201610064060 A CN201610064060 A CN 201610064060A CN 105529258 B CN105529258 B CN 105529258B
- Authority
- CN
- China
- Prior art keywords
- grid
- rfldmos
- etching
- technique
- length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000012876 topography Methods 0.000 title claims abstract description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 34
- 239000001301 oxygen Substances 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 238000001259 photo etching Methods 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 11
- 229910003978 SiClx Inorganic materials 0.000 claims abstract description 5
- 239000011800 void material Substances 0.000 claims 3
- 239000000126 substance Substances 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 10
- 238000001459 lithography Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000006641 stabilisation Effects 0.000 description 3
- 238000011105 stabilization Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides the process for stablizing gate topography in a kind of RFLDMOS technique, include the following steps: that one layer of grid oxygen SiClx 1) is grown in p-type lightly doped epitaxial layer forms grid oxide layer；2) one layer of polysilicon is deposited on grid oxide layer form polysilicon gate；3) photoetching is first passed through, the source of device grids and wherein one end of drain terminal are defined, carries out first time etching, photoresist is removed, forms the half of grid；4) second of photoetching is carried out again, defines the other end of device grids, then carry out second of etching, removes photoresist.The present invention forms grid using the method for two steps etching, the method to form grid etched by a step compare in the prior art, reduce the clearance rate (clear ratio) of single etch, the pattern of control grid that can be more stable for etching, to achieve the purpose that stable threshold voltage.
Description
Technical field
The present invention relates to semiconductor integrated circuit technique manufacturing field, in particular to the system of the grid in a kind of RFLDMOS
Make method.
Background technique
High-power RF device R FLDMOS (lateral diffusion metal oxide semiconductor) for base station etc. includes following knot
Structure: source electrode 13, drain electrode 14, grid 15, channel 16 and base stage and Faraday shield ring 17, detailed construction is shown in Fig. 1.Device is located at
In the epitaxial layer 12 of the growth of heavy doping substrate 11, drain terminal 14 has a longer drift region to obtain required breakdown potential
Pressure, Faraday shield ring 17 in drain terminal 14 plus one layer of thin-medium and metal plate by forming.Channel 16 is by 15 source of self-aligning grid
The P-type ion at edge is injected, and promotes to be formed by long-time high temperature, and exit is in the same side in source, the Yuan Hegou of device
Road will be connected on the substrate of heavy doping.The height of the deep or light threshold voltage for just determining device of the length of channel 16.
For RFLDMOS device, since channel 16 is to inject to be formed by 15 source edge of self-aligning grid, grid
The pattern of 15 sources just leverage injection ion number, also just affect the threshold voltage of device, 15 pattern of grid
Stability has vital effect to the stability of device threshold voltage.
And the clearance rate (clear ratio) of the grid of RFLDMOS device is very big, and polysilicon gate is one-step method
It etches and, for etching, the pattern of grid just very difficult stabilization, there are wafer to wafer and center to
The otherness of edge, so as to cause threshold voltage, there is also the differences of wafer to wafer and center to edge.
Therefore, how in RFLDMOS preparation, stablize the pattern of grid, become and asked for this field one is urgently to be resolved
Topic.
Summary of the invention
The technical problem to be solved by the invention is to provide the technique sides for stablizing gate topography in a kind of RFLDMOS technique
Method, to solve in the preparation process of RFLDMOS, gate topography is unstable and causes the threshold voltage of RFLDMOS unstable
Problem.
To solve the above problems, the present invention provides the process for stablizing gate topography in a kind of RFLDMOS technique, packet
Include step:
1) it is lightly doped in extension in p-type and grows one layer of grid oxygen SiClx formation grid oxide layer.
2) one layer of polysilicon is deposited on grid oxide layer form polysilicon gate.
3) photoetching is first passed through, the source of device grids and wherein one end of drain terminal are defined, carries out first time etching,
Photoresist is removed, the half of grid is formed.
4) second of photoetching is carried out again, defines the other end of device grids, then carry out second of etching, removes photoetching
Glue.
It is thus etched by two steps and forms complete grid, and the clearance rate (clear ratio) when single etch
Also it is reduced, is conducive to the stabilization of gate topography, and then improve the stabilization of the threshold voltage of device.
Preferably, the thickness of the grid oxide layer can need to be adjusted according to device, and shape can also be carved by photoetching
Erosion is changed.
Preferably, the polysilicon gate with a thickness of 0.25~0.35 μm, can be adjusted according to the needs of device.Into
One step preferably, the polysilicon gate with a thickness of 0.3 μm.
There is thick grid oxygen preferably for drain terminal and source has the device of thin grid oxygen:
It after forming grid oxide layer, performs etching the grid oxide layer, makes the thickness of the grid oxide layer of source part in step 1)
Reduction forms thin grid oxygen；In etching, retain a thick grid oxygen area in source, the grid oxygen in the thickness grid oxygen area not etches, thickness
It remains unchanged.
In step 3), the progress first time lithography and etching on polysilicon gate, the source side of etched features grid, and
Retain a polysilicon dummy line (dummy line)；The dummy line (dummy line) is located at thick grid oxygen area, and length is than the thick grid oxygen
Area is small；Remove photoresist；It is further preferred that the length in length grid oxygen area thicker than this of the dummy line (dummy line) it is small by 0.2~
0.4μm；It is further preferred that the length in length grid oxygen area thicker than this of the dummy line (dummy line) is 0.3 μm small.
In step 4), second of lithography and etching is carried out on polysilicon gate, in photoetching, not only opens drain terminal, and
And the dummy line (dummy line) of source side is opened, and opening length ratio when dummy line (the dummy line) of opening source side
Dummy line (dummy line) greatly, in this way, etching when, formed grid drain terminal while, etching remove dummy line (dummy
Line), form a complete grid.It is further preferred that the every side of opening length have more 0.05 than dummy line (dummy line)~
0.3μm.It is further preferred that the every side of opening length has more 0.15 μm than dummy line (dummy line).
The present invention provides the process for stablizing gate topography in a kind of RFLDMOS technique, the method etched using two steps
Grid is formed, etching the method to form grid by a step and compare in the prior art reduces the clearance rate of single etch
(clear ratio), the pattern of control grid that can be more stable for etching, to reach the mesh of stable threshold voltage
's.Meanwhile for having a thick grid oxygen for drain terminal and source has the device of thin grid oxygen, by introducing dummy line (dummy in source
Line) middle process, further reduced clearance rate (clear ratio) of the source in single etch, make etching can be more
The pattern of stable control grid, to make the stability of the threshold voltage of device more preferably.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of RFLDMOS.
Fig. 2 is one step 1) schematic diagram of embodiment.
Fig. 3 is one step 2) schematic diagram of embodiment.
Fig. 4 is one step 3) schematic diagram of embodiment.
Fig. 5 is one step 4) schematic diagram of embodiment.
Fig. 6 is two step 1) schematic diagram of embodiment.
Fig. 7 is two step 2) schematic diagram of embodiment.
Fig. 8 is two step 3) schematic diagram of embodiment.
Fig. 9 is photoetching schematic diagram in two step 4) of embodiment.
Figure 10 is two step 4) of embodiment etching, removes photoresist schematic diagram.
Figure 11 is step flow chart of the invention.
The meaning for the symbol used in Figure of description explains that volume is as follows:
11 heavy doping substrate, 12 epitaxial layer
The drain electrode of 13 source electrodes 14
15 grid, 16 channel
17 Faraday shield ring, 1 heavy doping substrate
2 type lightly doped epitaxial layer, 3 grid oxide layer
31 thick grid oxygen area, 4 polysilicon gate
41 dummy lines (dummy line) 5 photoresists
6 grid L open length
Specific embodiment
To make auditor have a better understanding the principle of the present invention, method and effect, in conjunction with Figure of description, now adopt
The present invention is explained as follows with the form of specific embodiment:
Embodiment one:
The process for stablizing gate topography in a kind of RFLDMOS technique, includes the following steps:
1) a layer thickness is grown in p-type lightly doped epitaxial layer 2 isGrid oxygen SiClx formed grid oxide layer 3, to the grid
The source side of oxygen layer performs etching, make its with a thickness ofForm thin grid oxide layer.
In other embodiments of the invention, the thickness and shape of the grid oxide layer 3 can need to carry out according to device
Adjustment.
2) one layer of polysilicon is deposited on grid oxide layer and form polysilicon gate 4, with a thickness of 0.3 μm.
In other embodiments of the invention, the polysilicon gate 4 with a thickness of 0.25~0.35 μm, thickness can root
It is adjusted according to the needs of device.
3) first time photoetching is carried out on polysilicon gate 4, defines the source of device, is carried out first time etching, is then gone
Except photoresist 5, in this way, foring the half of grid.
4) second of photoetching is carried out on polysilicon gate 4, defines the drain terminal of device grids, is carried out second and is etched, goes
Except photoresist 5.
Clearance rate (the clear in this way, method etched by two steps, etches complete grid 6, when single etch
Ratio it) is reduced, the stability of 6 pattern of grid improves, and the stability of the threshold voltage of RFLDMOS is improved in turn.
Embodiment two
Stablize the process of gate topography in a kind of RFLDMOS technique, wherein the drain terminal of the RFLDMOS have a thick grid oxygen and
The step of source has thin grid oxygen, the process is as follows:
1) a layer thickness is grown in p-type lightly doped epitaxial layer 2 isGrid oxygen SiClx formed grid oxide layer 3, to the grid
Oxygen layer performs etching, make the grid oxide layer of source part with a thickness ofIn etching, retain a thick grid oxygen area 31 in source,
The grid oxygen in the thickness grid oxygen area 31 not etches, and thickness is still
2) one layer of polysilicon is deposited on grid oxide layer 3 and form polysilicon gate 4, with a thickness of 0.3 μm.
In other embodiments of the invention, the polysilicon gate 4 with a thickness of 0.25~0.35 μm, can be according to device
It needs to be adjusted.
3) first time lithography and etching, the source side of etched features grid are carried out on polysilicon gate 4, and retain one
Polysilicon dummy line (dummy line) 41；The dummy line (dummy line) 41 is located at thick grid oxygen area 31, and length is than the thick grid oxygen area
31 is 0.3 μm small；Remove photoresist.
In other embodiments of the invention, length grid oxygen area 31 thicker than this of the dummy line (dummy line) 41 it is long
It spends 0.2~0.4 μm small.
In other embodiments of the invention, the length of the dummy line (dummy line) 41 is not less than 0.5 μm.
4) second of lithography and etching is carried out on polysilicon gate 4, in photoetching, not only opens drain terminal, but also open source
The dummy line (dummy line) 41 of side is held, and the opening length L when dummy line (dummy line) 41 of opening source side is than empty
Quasi- line (dummy line) greatly, every side grows 0.15 μm than dummy line (dummy line) 41.In this way, forming grid in etching
While drain terminal, etching removes dummy line (dummy line) 41, forms a complete grid 6.
In other embodiments of the invention, which is greater than dummy line (dummy line) 41, and every side is big
Length is 0.05~0.3 μm, and specific width can be adjusted according to the requirement of technique.
Due to the introducing of dummy line (dummy line), the clearance rate (clear in first time photoetching further reduced
Ratio), and due to the influence of dummy line (dummy line), the stability of the pattern of grid is further improved, the RFLDMOS
The stability of threshold voltage further improve.
Embodiment as above is only several preferred embodiments of the invention, and content is explanation of the invention, is not
Limitation to the content of present invention.Those skilled in the art can be done with principle according to the present invention, method, embodiment and schema
The embodiment of other modes out, all these pairs of substitutions of the invention, equivalence replacement and deformation, is regarded as of the invention
In protection scope.
Claims (8)
1. stablizing the process of gate topography in a kind of RFLDMOS technique, which comprises the steps of:
1) one layer of grid oxygen SiClx is grown in p-type lightly doped epitaxial layer form grid oxide layer；Make the RFLDMOS's by chemical wet etching
Drain terminal has thick grid oxygen and source has thin grid oxygen；
2) one layer of polysilicon is deposited on grid oxide layer form polysilicon gate；
3) first time photoetching is first passed through, the source of device grids is defined, carries out first time etching, the first time photoetching, etching
It is carried out in device grids source side；
When first time photoetching, etching for the first time, device grids source side retains a polysilicon dummy line；
The dummy line is located at the thickness grid oxygen area, and length is smaller than the thick grid oxygen area；
Photoresist is removed, the half of grid is formed；
4) second of photoetching is carried out again, defines the other end of device grids, then carry out second of etching, in photoetching, not only
Drain terminal is opened, and opens dummy line；Remove photoresist.
2. stablizing the process of gate topography in RFLDMOS technique as described in claim 1, which is characterized in that in step
2) in, the polysilicon gate with a thickness of 0.25~0.35 μm.
3. stablizing the process of gate topography in RFLDMOS technique as described in claim 1, which is characterized in that the void
The length in length grid oxygen area thicker than this of quasi- line is 0.2~0.4 μm small.
4. stablizing the process of gate topography in RFLDMOS technique as described in claim 1, which is characterized in that the void
The length in length grid oxygen area thicker than this of quasi- line is 0.3 μm small.
5. stablizing the process of gate topography in RFLDMOS technique as described in claim 1, which is characterized in that the void
The length of quasi- line is not less than 0.5 μm.
6. stablizing the process of gate topography in RFLDMOS technique as described in claim 1, which is characterized in that open empty
When quasi- line, the length opened is greater than the length of dummy line.
7. stablizing the process of gate topography in RFLDMOS technique as claimed in claim 6, which is characterized in that open empty
When quasi- line, the every side of the opening length has more 0.05~0.3 μm than dummy line.
8. stablizing the process of gate topography in RFLDMOS technique as claimed in claim 7, which is characterized in that open empty
When quasi- line, the every side of the opening length has more 0.15 μm than dummy line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610064060.9A CN105529258B (en) | 2016-01-29 | 2016-01-29 | Stablize the process of gate topography in RFLDMOS technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610064060.9A CN105529258B (en) | 2016-01-29 | 2016-01-29 | Stablize the process of gate topography in RFLDMOS technique |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105529258A CN105529258A (en) | 2016-04-27 |
| CN105529258B true CN105529258B (en) | 2019-04-09 |
Family
ID=55771405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610064060.9A Active CN105529258B (en) | 2016-01-29 | 2016-01-29 | Stablize the process of gate topography in RFLDMOS technique |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105529258B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103065959A (en) * | 2011-10-21 | 2013-04-24 | 上海华虹Nec电子有限公司 | Method for reducing silicon etching loading effect |
| CN104216233A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Exposure method |
| CN104851803A (en) * | 2014-02-17 | 2015-08-19 | 无锡华润上华半导体有限公司 | Transverse diffused metal oxide semiconductor device manufacture method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100517578C (en) * | 2006-11-28 | 2009-07-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device grids preparation method |
| CN101752251B (en) * | 2008-12-04 | 2012-06-20 | 上海华虹Nec电子有限公司 | Fully-automatic aligning high-pressure N-shaped DMOS device and manufacturing method thereof |
| JP2010245101A (en) * | 2009-04-01 | 2010-10-28 | Hitachi High-Technologies Corp | Dry etching method |
-
2016
- 2016-01-29 CN CN201610064060.9A patent/CN105529258B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103065959A (en) * | 2011-10-21 | 2013-04-24 | 上海华虹Nec电子有限公司 | Method for reducing silicon etching loading effect |
| CN104216233A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Exposure method |
| CN104851803A (en) * | 2014-02-17 | 2015-08-19 | 无锡华润上华半导体有限公司 | Transverse diffused metal oxide semiconductor device manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105529258A (en) | 2016-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10475896B2 (en) | Silicon carbide MOSFET device and method for manufacturing the same | |
| CN106206322B (en) | The manufacturing method of autoregistration low pressure super node MOSFET | |
| CN108649072A (en) | A kind of groove MOSFET device and its manufacturing method of low on-resistance | |
| CN105762176A (en) | Silicon carbide mosfet device and manufacturing method thereof | |
| CN103337460B (en) | A kind of GaN HEMT device preparation method integrated for E/D | |
| CN105810680B (en) | JFET and its manufacturing method | |
| CN209592046U (en) | A kind of enhanced semiconductor transistor | |
| CN105655402A (en) | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same | |
| CN110400846A (en) | With ladder deep trouth shield grid MOS structure and production method | |
| CN104617045A (en) | Manufacturing method of trench gate power device | |
| CN104347375B (en) | The method that barrier layer performs etching to grid polycrystalline silicon is done using oxide-film | |
| CN105529258B (en) | Stablize the process of gate topography in RFLDMOS technique | |
| CN111509034A (en) | Field effect transistor with same gate source doping, cell structure and preparation method | |
| CN105047647B (en) | The production method of photoetching alignment mark in thick epitaxy technique | |
| CN111106169A (en) | Transistor device and preparation method thereof | |
| CN115376919A (en) | Enhanced GaN power device and preparation method thereof | |
| CN106328523B (en) | The production method of radio frequency lateral direction bilateral diffusion MOS device | |
| CN104299903B (en) | The manufacture method of trench gate mosfet | |
| CN106356304A (en) | Semiconductor production process | |
| CN102956489B (en) | Manufacture method of trench transistor | |
| CN105336612A (en) | Planar VDMOS device and manufacturing method thereof | |
| CN205488142U (en) | Low pressure surpasses knot MOSFET terminal structure | |
| CN104637799A (en) | Manufacturing method of fully-automatically-aligned high-density groove gate field effect semiconductor device | |
| CN106158961B (en) | Plane VDMOS device production method | |
| CN105336785B (en) | A kind of depletion type VDMOS device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |