CN105514170A - Power metal oxide semiconductor field effect transistor and manufacturing method of power metal oxide semiconductor field effect transistor - Google Patents
Power metal oxide semiconductor field effect transistor and manufacturing method of power metal oxide semiconductor field effect transistor Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 25
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 25
- 230000005669 field effect Effects 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 35
- 239000012535 impurity Substances 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 11
- 238000004891 communication Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 230000007935 neutral effect Effects 0.000 claims description 4
- 230000026267 regulation of growth Effects 0.000 claims description 3
- 239000002800 charge carrier Substances 0.000 abstract description 3
- 230000006698 induction Effects 0.000 abstract description 3
- 210000000746 body region Anatomy 0.000 abstract 5
- 239000000203 mixture Substances 0.000 description 15
- 230000003071 parasitic effect Effects 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 208000002925 dental caries Diseases 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention provides a power metal oxide semiconductor field effect transistor. The transistor comprises an epitaxial layer, a body region, grid electrodes and oxidization layers, wherein the epitaxial layer grows in advance and trenches are formed in the top surface of the epitaxial layer. The body region is located between the trenches and extends to a pre-set position towards the direction of a bottom surface of the epitaxial layer. The grid electrodes are located in the trenches and are parallel to the extending direction of the body region; the grid electrodes comprise two first grid electrodes and a central grid electrode located between the first grid electrodes; the length of each first grid electrode is greater than the depth of the body region and is smaller than the length of the central grid electrode. When the central grid electrode is used for connecting a low potential, the epitaxial layer is used up; or when the central grid electrode is used for connecting a high potential, most charge carriers of a conduction channel and/or an induction epitaxial layer in the body region are enhanced. The oxidization layers are located at the bottoms and lateral walls of the trenches and lateral surfaces of the first grid electrodes. With the adoption of the power metal oxide semiconductor field effect transistor provided by the invention, a voltage-resisting capability and a switching-on/off speed can be improved and conduction resistance is reduced.
Description
Technical field
The invention belongs to technical field of semiconductor device, particularly relate to a kind of power metal oxide semiconductor field-effect transistor.
Background technology
Slot type MOSFET (TrenchMOSFET) is the New Type Power Devices developed rapidly in recent years.Slot type MOSFET (TrenchMOSFET) has more premium properties than bipolar power component, such as: high input impedance, low drive current, not few sub-storage effect, switching speed is fast, operating frequency is high, there is negative current temperature coefficient, and have good electric current self-adjusting ability, effectively can prevent the generation of electric current concentration of local and focus, homogeneous current distribution, easily increase current capacity by parallel way, there is stronger power handling capability, Heat stability is good, safety operation area is large, there is no second breakdown etc., be widely used in various electronic equipment, as high-speed switching circuit, Switching Power Supply, uninterrupted power supply, high power amplifying circuit, high-fidelity music center circuit, radio-frequency (RF) power amplification circuit, power conversion circuit, motor frequency conversion circuit, motor-drive circuit, solid state relay, interface circuit etc. between control circuit and power termination.
The concrete structure of conventional groove formula mos field effect transistor (TrenchMOSFET), composition graphs 4, for NMOS, silicon chip 100 back side is as drain electrode 110, silicon chip 100 manufactures epitaxial loayer 101, digging groove 102 in epitaxial loayer 101, grows one deck gate oxide 103 in groove 102, and then deposit gate electrode 104, between gate electrode 104 and source electrode 109, there is separator 107 (BPSG).Inject the p type impurity in tagma 105 and the N-type impurity in source region 106 at epitaxial loayer 103 intermediate ion, the impurity concentration in the relative concentration tagma 105 of the p type impurity of ohmic contact regions 108 is higher.
But the slot type MOSFET (TrenchMOSFET) of this traditional structure understands the withstand voltage of limiting device.If improve the puncture voltage of device, then need the doping content reducing epitaxial loayer 101, the conducting resistance of device will raise, and power consumption strengthens.Meanwhile, gate electrode 104, grid oxic horizon 103 and drain electrode composition parasitic capacitance, limit the switching speed of transistor, increase the switching loss of transistor.
Summary of the invention
The present invention aims to provide a kind of power metal oxide semiconductor field-effect transistor, improves the voltage endurance capability of device and the switching speed of device, and reduces the conducting resistance of device.
The invention provides a kind of power metal oxide semiconductor field-effect transistor, this transistor comprises epitaxial loayer, tagma, gate electrode and oxide layer, and epitaxial loayer grows in advance, and is provided with groove at the end face of epitaxial loayer.Tagma is between groove, and the direction, bottom surface of epitaxial layers extends to precalculated position.Gate electrode is positioned at groove, and be parallel to the bearing of trend in tagma, gate electrode comprises two first grid electrodes and the central gate electrode between first grid electrode, the length of first grid electrode is greater than the tagma degree of depth, and is less than the length of central gate electrode, central gate electrode, during for connecing electronegative potential, exhaust epitaxial loayer and/or, when connecing high potential, strengthen the majority carrier of communication channel in tagma and/or induction epitaxial loayer.Oxide layer invests the side surface of the bottom of groove, sidewall and first grid electrode.
Further, oxide layer comprises first grid oxide layer and central grid oxic horizon, and first grid oxide layer is positioned at the upper portion side wall of groove and the side surface of first grid electrode, for being separated in first grid electrode and tagma and central gate electrode.Central authorities' grid oxic horizon is positioned at the bottom of groove, and extends trenched side-wall, terminates in the bottom surface of first grid electrode, for electric isolution central authorities' gate electrode and epitaxial loayer.
Further, the thickness of central grid oxic horizon is greater than the thickness of first grid oxide layer.
Further, the one-tenth-value thickness 1/10 of central grid oxic horizon is also greater than set point.
Further, when central gate electrode connects electronegative potential, first grid electrode connecting to neutral current potential, closes transistor for electricity.When central authorities' gate electrode connects high potential, first grid electrode is in forward bias, for electric-opening transistor.
Further, the end face of two first grid electrodes flushes.
Further, the material of gate electrode is polysilicon.
The present invention also provides a kind of power metal oxide semiconductor field-effect transistor manufacture method, and the method concrete steps comprise:
Step S1: at the epitaxial loayer of Grown impurity;
Step S2: dig groove to bottom surface from the end face of epitaxial loayer;
Step S3: thermal growth oxide layer in the end face and groove of epitaxial loayer;
Step S4: depositing polysilicon in oxide layer, forms central gate electrode;
Step S5: etching oxidation layer, to desired location, forms central grid oxic horizon;
Step S6: hot growth regulation dioxide layer, forms the first grid electrode hole between epitaxial loayer and central gate electrode;
Step S7: depositing polysilicon in the second oxide layer, forms first grid electrode;
Step S8: ion implantation, forms the tagma between groove, deposit isolating oxide layer and metal, forms source electrode and drain electrode, forms transistor.
Further, in the step S4 of this manufacture method, form central gate electrode concrete steps and comprise: depositing polysilicon is in the surface of oxide layer, and filling groove, then etch, the polysilicon outside removing groove, forms central gate electrode;
Further, in the step S7 of this manufacture method, form first grid electrode concrete steps and comprise: depositing polysilicon is in the surface of oxide layer, and fill first grid electrode hole, etch, the polysilicon outside removing first grid electrode hole, forms first grid electrode again.
Further, in the step S8 of this manufacture method, deposit isolating oxide layer and metal, form source electrode concrete steps to comprise: deposit isolating oxide layer, and etch between groove, form contact hole, ion implantation is in ohmic contact regions again, with the Metal Contact of deposit, forms source electrode.
Power metal oxide semiconductor field-effect transistor provided by the invention, when transistor reverse bias, central gate electrode and source shorted, or independent grounding end, first grid electrode connecting to neutral current potential, now can close transistor by electricity.Central authorities' gate electrode makes the vertical direction of electric field aligned current exhaust epitaxial loayer.Usually there is the structure of identical central gate electrode at the opposite side of epitaxial loayer, exhaust epitaxial loayer from both sides, the concentration impurity ion in epitaxial loayer is reduced.Meanwhile, tagma is dopant implant p type impurity ion range, and epitaxial loayer is doped N-type extrinsic region, and tagma and epitaxial loayer exhaust charge carrier mutually, and the concentration impurity ion of epitaxial loayer is reduced again.The concentration impurity ion of epitaxial loayer reduces, and the puncture voltage of transistor raises, and the voltage endurance capability of device strengthens.Namely, when the impurity concentration that the epitaxial loayer of transistor adulterates identical, transistor of the present invention possesses higher puncture voltage.
When transistor forward conduction, central authorities' gate electrode connects high potential, first grid electrode is in forward bias, now can electric-opening transistor, central authorities' gate electrode and first grid electrode act in communication channel simultaneously, attract more electronics, strengthen the opening degree of communication channel, reduce the conducting resistance of communication channel part.Central authorities' gate electrode connects high potential, and in the non-overlapped part of central gate electrode and first grid electrode, i.e. epitaxial loayer, will induce more electronics, reduces epitaxial layer portion conducting resistance further, and pressure drop reduces.Simultaneously, when transistor reaches identical puncture voltage, the epitaxial loayer of transistor of the present invention, the concentration impurity ion that can adulterate can be higher, now, the resistivity of epitaxial loayer during forward conduction reduces, and again reduces the conducting resistance of epitaxial layer portion, namely, when the puncture voltage of transistor is identical, transistor of the present invention possesses lower conducting resistance.
First grid electrode and drain electrode separate by the central gate electrode of transistor of the present invention, the length of first grid electrode is greater than the degree of depth in tagma, and be less than the length of central gate electrode, when the thickness of epitaxial loayer 201 is constant, due to the existence of central gate electrode and central grid oxic horizon, spacing distance between first grid electrode and drain electrode strengthens, be equivalent to add the field plate spacing between the parasitic capacitance that is made up of grid and draining, spacing increases, parasitic capacitance reduces, namely first grid electrode reduces to the parasitic capacitance of drain electrode, make transistor can be operated in higher frequency range, switching speed can be improved and reduce switching loss.
Therefore, power metal oxide semiconductor field-effect transistor provided by the invention, can improve the voltage endurance capability of device and the switching speed of device, and reduce the conducting resistance of device.
The preparation method of transistor that the present embodiment provides, by deposit and etch polysilicon, makes central gate electrode and two first grid electrodes be formed in same groove, realizes the making of gate electrode, forms power metal oxide semiconductor field-effect transistor.The independence that this manufacture method can realize central gate electrode exists, and with the electric isolution of first grid electrode, reach central gate electrode and connect different potentials, realize corresponding electric property.
Accompanying drawing explanation
Fig. 1 is a power metal oxide semiconductor field-effect transistor section of structure provided by the invention;
Fig. 2 is a power metal oxide semiconductor field-effect transistor process chart provided by the invention;
Fig. 3 is another power metal oxide semiconductor field-effect transistor process chart provided by the invention;
Fig. 3 A is the section of structure of Grown epitaxial loayer in another technological process provided by the invention;
Fig. 3 B is the section of structure etching deep trench in another technological process provided by the invention;
Fig. 3 C is the section of structure growing oxide layer in another technological process provided by the invention;
Fig. 3 D is the section of structure of the central gate electrode formed in another technological process provided by the invention;
Fig. 3 E is the section of structure of etching oxidation layer in another technological process provided by the invention;
Fig. 3 F is the section of structure of first grid electrode in another technological process provided by the invention;
Fig. 3 G is the section of structure injecting tagma in another technological process provided by the invention;
Fig. 3 H is the section of structure injecting source region in another technological process provided by the invention;
Fig. 3 I is the section of structure forming isolating oxide layer and metal contact hole in another technological process provided by the invention;
Fig. 3 J is the section of structure injecting ohmic contact regions in another technological process provided by the invention;
Fig. 3 K is the section of structure of deposit source metal and drain contact metallization in another technological process provided by the invention;
Fig. 4 is the section of structure of INVENTIONConventional metal-oxide semiconductor field effect transistor (TrenchMOSFET).
Embodiment
Further illustrate the present invention below by specific embodiment, but should be understood to, these embodiments are only used for the use specifically described more in detail, and should not be construed as limiting the present invention in any form.
First aspect, the invention provides a kind of power metal oxide semiconductor field-effect transistor, is described as follows:
The invention provides a kind of power metal oxide semiconductor field-effect transistor, for NMOS, composition graphs 1, this transistor comprises epitaxial loayer 201, tagma 207, gate electrode and oxide layer.Epitaxial loayer 201 grows in advance, and is provided with groove 202 at the end face of epitaxial loayer 201.Tagma 207 is between groove 202, and the direction, bottom surface of epitaxial layers 201 extends to precalculated position.Gate electrode is positioned at groove 202, and be parallel to the bearing of trend in tagma 207, gate electrode comprises two first grid electrodes 206 and the central gate electrode 204 between first grid electrode 206, the length of first grid electrode 206 is greater than tagma 207 degree of depth, and be less than the length of central gate electrode 204, when central gate electrode 204 is for connecing electronegative potential, exhaust epitaxial loayer 201 and/or, when connecing high potential, the majority carrier of the communication channel in enhancing tagma 207 and/or induction epitaxial loayer 201.Oxide layer invests the side surface of the bottom of groove 202, sidewall and first grid electrode 206.
The transistor of the present embodiment, draws central gate electrode 204 between two first grid electrodes 206, and during transistor, as required, central gate electrode 204 connects different potentials, can reach different electric property.
When transistor reverse bias, central gate electrode 204 and source electrode 212 short circuit, or central gate electrode 204 independent grounding end, first grid electrode 206 connecting to neutral current potential, now can close transistor by electricity.Central authorities' gate electrode 204 makes the vertical direction of electric field aligned current exhaust epitaxial loayer 201.Usually there is the structure of identical central gate electrode 204 at the opposite side of epitaxial loayer 201, exhaust epitaxial loayer 201 from both sides, the concentration impurity ion in epitaxial loayer 201 is reduced.Meanwhile, tagma 207 is dopant implant p type impurity ion range, and epitaxial loayer 201 is doped N-type extrinsic regions, and tagma 207 and epitaxial loayer 201 exhaust charge carrier mutually, and the concentration impurity ion of epitaxial loayer 201 is reduced again.The concentration impurity ion of epitaxial loayer 201 reduces, and the puncture voltage of transistor raises, and the voltage endurance capability of device strengthens.Namely, when the impurity concentration that the epitaxial loayer of transistor adulterates identical, transistor of the present invention possesses higher puncture voltage.
When transistor forward conduction, central authorities' gate electrode 204 connects high potential, first grid electrode 206 is in forward bias, now can electric-opening transistor, central authorities' gate electrode 204 acts in communication channel with first grid electrode 206 simultaneously, attract more electronics, strengthen the opening degree of communication channel, reduce the conducting resistance of communication channel part.Central authorities' gate electrode 204 connects high potential, and in the non-overlapped part of central gate electrode 204 and first grid electrode 206, i.e. epitaxial loayer 201, will induce more electronics, and reduce epitaxial loayer 201 part conducting resistance further, pressure drop reduces.Simultaneously, when transistor reaches identical puncture voltage, the epitaxial loayer 201 of the present embodiment transistor, the concentration impurity ion that can adulterate can be higher, now, the resistivity of the epitaxial loayer 201 during forward conduction reduces, and again reduce the conducting resistance of epitaxial loayer 201 part, transistor of the present invention possesses lower conducting resistance.
First grid electrode 206 and drain electrode 213 separate by the central gate electrode 204 of the present embodiment transistor, the length of first grid electrode 206 is greater than the degree of depth in tagma 207, and be less than the length of central gate electrode 204, when the thickness of epitaxial loayer 201 is constant, due to the existence of central gate electrode 204 and central grid oxic horizon 203, spacing distance between first grid electrode 206 and drain electrode 213 strengthens, be equivalent to add the field plate spacing between the parasitic capacitances that are made up of grid and drain electrode 213, spacing increases, parasitic capacitance reduces, namely first grid electrode 206 reduces to the parasitic capacitance of drain electrode 213, make transistor can be operated in higher frequency range, there is switching speed and less switching loss faster.Further, the present embodiment transistor can reduce conducting resistance and the switching time of device, therefore, it is possible to obtain lower FOM value.
Therefore, the power metal oxide semiconductor field-effect transistor that the present embodiment provides, can improve the voltage endurance capability of device and the switching speed of device, and reduce the conducting resistance of device.In addition, the present embodiment transistor also has the advantages such as making manufacture of materials amount is large.
The oxide layer of the present embodiment transistor comprises first grid oxide layer 205 and central grid oxic horizon 203, and first grid oxide layer 205 is positioned at the upper portion side wall of groove 202, can electric isolution first grid electrode 206 and tagma 207.When first grid electrode 206 connects zero potential, repel the electronics in tagma 207, transistor is in closed condition.When first grid electrode 206 connects high potential, attract the electronics in tagma 207, first grid oxide layer 205 block electrons is neutralized, and forms communication channel.First grid oxide layer 205 also comprises the oxide layer of the side surface of first grid electrode 206, for electric isolution first grid electrode 206 and central gate electrode 204.The first grid oxide layer 205 at two places completes in same processing procedure.Central authorities' grid oxic horizon 203 is positioned at the bottom of groove 202, and extends groove 202 sidewall, terminates in the bottom surface of first grid electrode 206, and central grid oxic horizon 203 can electric isolution central authorities' gate electrode 204 and epitaxial loayer 201.When central gate electrode 204 connects high potential, attract the electronics in epitaxial loayer 201, and block electrons is not neutralized by central gate electrode 204, reduce epitaxial electric resistance during conducting, reduce pressure drop.The thickness of central authorities' grid oxic horizon 203 is greater than set point, and its set point is the one-tenth-value thickness 1/10 of the oxide layer of breakdown voltage transistor.Puncture voltage is higher, and required central grid oxic horizon 203 is thicker.The thickness of central authorities' grid oxic horizon 203 is greater than first grid oxide layer 205, when guaranteeing transistor forward conduction, can normally work, and during reverse bias, transistor is not easily breakdown.First grid oxide layer 205 and central grid oxic horizon 203 adopt silicon dioxide, the mode grown by heat, generate fine and close oxide layer.In groove 202, the end face of two first grid electrodes 206 flushes, and completes in etching grid polysilicon step simultaneously.The material of first grid electrode 206 and central gate electrode 204 is polysilicons, and the mode of employing deposit generates the polysilicon containing foreign ion, and output is large, is convenient to draw materials.
Second aspect, the invention provides a kind of power metal oxide semiconductor field-effect transistor manufacture method, concrete steps are as follows.
The invention provides a kind of power metal oxide semiconductor field-effect transistor manufacture method, for NMOS, composition graphs 2, concrete steps comprise:
Step S1: at the epitaxial loayer of Grown impurity;
Step S2: dig groove to bottom surface from the end face of epitaxial loayer;
Step S3: thermal growth oxide layer in the end face and groove of epitaxial loayer;
Step S4: depositing polysilicon in oxide layer, forms central gate electrode;
Step S5: etching oxidation layer, to desired location, forms central grid oxic horizon;
Step S6: hot growth regulation dioxide layer, forms the first grid electrode hole between epitaxial loayer and central gate electrode;
Step S7: depositing polysilicon in the second oxide layer, forms first grid electrode;
Step S8: ion implantation, forms the tagma between groove, deposit isolating oxide layer and metal, forms source electrode and leakage
Pole, forms transistor.
The preparation method of transistor that the present embodiment provides, by deposit and etch polysilicon, makes central gate electrode and two first grid electrodes be formed in same groove, realizes the making of gate electrode, forms power metal oxide semiconductor field-effect transistor.The independence that this manufacture method can realize central gate electrode exists, and with the electric isolution of first grid electrode, reach central gate electrode and connect different potentials, realize corresponding electric property.
Further, in the step S4 of preparation method of transistor provided by the invention, form central gate electrode concrete grammar and comprise: depositing polysilicon is in the surface of oxide layer, and filling groove 202, etch, the polysilicon outside removing groove 202, forms central gate electrode 204 again.In the step s 7, the method forming first grid electrode specifically comprises: depositing polysilicon in the surface of oxide layer, and fills described first grid electrode hole, then etches, and the polysilicon outside removing first grid electrode hole, forms first grid electrode 206.When etching, the polysilicon outside removing groove 202 or first grid electrode hole, can guarantee that surface between groove is without remaining polysilicon, short circuit when preventing subsequent transistor from working.In step s 8, deposit isolating oxide layer 209 and metal, the method forming source electrode 212 specifically comprises: deposit isolating oxide layer 209, and etch between groove 202, form metal contact hole 210, then ion implantation is in ohmic contact regions 211, with the Metal Contact of deposit, form source electrode 212.
The invention provides another kind of power metal oxide semiconductor field-effect transistor manufacture method, for NMOS, combined process flow chart 3, concrete technology step comprises:
Step S21: Grown epitaxial loayer, composition graphs 3A, grow N epitaxial loayer 201, i.e. N drift region 201 on an n+substrate 200.The resistivity that substrate 200 is heavily doped to N-type impurity is the scope of 1 ‰ ohm-cm---3 ‰ ohm-cm, and the N-type impurity doping content of N drift region 201 thus the withstand voltage of transistor decides.
Step S22: etching deep trench, composition graphs 3B, in N drift region 201, etches from the end face of drift region 201 to bottom surface, gos deep into most of N drift region 201 and digs groove 202.
Step S23: growth oxide layer, composition graphs 3C, the inner and N drift region 201 superficial growth oxide layer at groove 202.The thickness of this oxide layer has certain requirement, must can bear source electrode and the inverse peak voltage added by drain electrode.Inverse peak voltage is larger, and oxide layer is also thicker.The control thickness that the growth needs of this oxide layer is strict and quality.
Step S24: deposit trench polisilicon is also etched back in groove, composition graphs 3D, and depositing polysilicon is as central gate electrode 204.Depositing polysilicon is on the surface of the whole oxide layer of this structure, and filling groove 202.Doped with the foreign ion of N-type impurity in polysilicon.Then, polysilicon layer is etched back to again in groove 202, and the polysilicon outside removing groove 202, polysilicon layer is basic equal with oxide layer surface.Central gate electrode 204 is formed in groove 202.
Step S25: etching oxidation layer, composition graphs 3E, adopt buffer oxide to etch, oxide layer etched into the precalculated position in groove 202, form central grid oxic horizon 203.Meanwhile, also between central gate electrode 204 and drift region 201, two cavitys in left and right are formed.Central authorities' grid oxic horizon 203 is by central gate electrode 204 and drift region 201 electric isolution mutually.Buffered oxide etch has precedence over polysilicon or epitaxial silicon etching silicon dioxide.
Step S26: deposit first grid electrode is also etched back to the surface of first grid electrode hole, composition graphs 3F, on the end face of this structure, heat growth the first grid oxic horizon 205, forms first grid electrode hole in each cavity.In each cavity, the sidewall of the Part I contiguous center gate electrode 204 of first grid oxide layer 205, and the Part II of first grid oxide layer 205 adjoins the sidewall in tagma 207.Then at the first grid oxide layer surface deposition polysilicon of this structure, and fill first grid electrode hole, then carry out go back to the surface etching into first grid oxide layer, the polysilicon outside removing first grid electrode hole, forms first grid electrode 206.
Step S27: inject tagma, composition graphs 3G, injects the tagma 207 of this transistor.What tagma 207 was injected is p type impurity, and the threshold voltage that concrete dosage and energy will require according to this transistor decides.
Step S28: inject source region, composition graphs 3H, injects the source region 208 of this transistor.What source region 208 was injected is N-type impurity, finally, and high two orders of magnitude of N-type impurity concentration of the N-type impurity concentration ratio drift region 201 in source region 208.
Step S29: deposit isolating oxide layer BPSG also etches metal contact hole, composition graphs 3I, and deposit isolating oxide layer BPSG (boron-phosphorosilicate glass) 209 also etches contact hole 210.At the surface deposition isolating oxide layer BPSG209 of this structure, this isolating oxide layer 209 is used as the isolation of central gate electrode 204 and first grid electrode 206 and source metal 212.Then on isolating oxide layer BPSG209, metal contact hole 210 is etched.Central authorities' gate electrode 204 is drawn in device periphery and reserves bonding wire region.
Step S30: inject ohmic contact regions, composition graphs 3J, injects ohmic contact regions 211.What ohmic contact regions 211 was injected be p type impurity, for reducing herein with the resistance of Metal Contact, reduction conducting resistance, prevents opening by mistake of parasitic NPN transistor from opening.This parasitic transistor is once open, and power MOSFET will not control by gate electrode, cause transistor nonfunctional.
Step S31: deposit source metal and drain contact metallization, composition graphs 3K, deposit source metal 212.At the upper surface depositing metal of this structure, as the source contact metal of whole transistor.Meanwhile, carry out thinning at the lower surface of this structure, substrate 200 is thinned to 200um.Then, then depositing metal forms the drain contact metallization 213 of transistor, forms transistor, completes the whole manufacture craft process of transistor.
Although present invention has been description to a certain degree, significantly, under the condition not departing from the spirit and scope of the present invention, can carry out the suitable change of each condition.Be appreciated that and the invention is not restricted to described embodiment, and be attributed to the scope of claim, it comprises the equivalent replacement of described each factor.
Claims (10)
1. a power metal oxide semiconductor field-effect transistor, is characterized in that, comprising:
Epitaxial loayer, tagma, gate electrode and oxide layer,
Described epitaxial loayer grows in advance, and is provided with groove at the end face of epitaxial loayer;
Described tagma between described groove, and extends to precalculated position to the direction, bottom surface of described epitaxial loayer;
Described gate electrode is positioned at described groove, and is parallel to the bearing of trend in described tagma,
Described gate electrode comprises two first grid electrodes and the central gate electrode between described first grid electrode,
The length of described first grid electrode is greater than the described tagma degree of depth, and is less than the length of described central gate electrode,
Described central gate electrode, during for connecing electronegative potential, exhaust described epitaxial loayer and/or, when connecing high potential, strengthen the communication channel in described tagma and/or respond to the majority carrier of described epitaxial loayer;
Described oxide layer invests the side surface of the bottom of described groove, sidewall and described first grid electrode.
2. transistor according to claim 1, is characterized in that,
Described oxide layer comprises first grid oxide layer and central grid oxic horizon,
Described first grid oxide layer is positioned at the upper portion side wall of described groove and the side surface of described first grid electrode, for being separated in described first grid electrode and described tagma and described central gate electrode;
Described central grid oxic horizon is positioned at the bottom of described groove, and extends described trenched side-wall, terminates in the bottom surface of described first grid electrode, for gate electrode central described in electric isolution and described epitaxial loayer.
3. transistor according to claim 2, is characterized in that,
The thickness of described central grid oxic horizon is greater than the thickness of described first grid oxide layer.
4. transistor according to claim 2, is characterized in that,
The one-tenth-value thickness 1/10 of described central grid oxic horizon is also greater than set point.
5. transistor according to claim 1, is characterized in that,
When described central gate electrode connects electronegative potential, first grid electrode connecting to neutral current potential, closes described transistor for electricity;
When described central gate electrode connects high potential, first grid electrode is in forward bias, for transistor described in electric-opening.
6. transistor according to claim 5, is characterized in that,
The end face of described two first grid electrodes flushes.
7. transistor according to claim 5, is characterized in that,
The material of described gate electrode is polysilicon.
8. a manufacture method for power metal oxide semiconductor field-effect transistor, is characterized in that, described method comprises:
Step S1: at the epitaxial loayer of Grown impurity;
Step S2: dig groove to bottom surface from the end face of epitaxial loayer;
Step S3: thermal growth oxide layer in the end face and groove of epitaxial loayer;
Step S4: depositing polysilicon in oxide layer, forms central gate electrode;
Step S5: etching oxidation layer, to desired location, forms central grid oxic horizon;
Step S6: hot growth regulation dioxide layer, forms the first grid electrode hole between epitaxial loayer and central gate electrode;
Step S7: depositing polysilicon in the second oxide layer, forms first grid electrode;
Step S8: ion implantation, forms the tagma between groove, deposit isolating oxide layer and metal, forms source electrode and drain electrode, forms transistor.
9. manufacture method according to claim 8, is characterized in that,
In step s 4 which, form central gate electrode, the method specifically comprises: depositing polysilicon in the surface of described oxide layer, and fills described groove, then etches, and removes the polysilicon outside described groove, forms central gate electrode;
In the step s 7, form first grid electrode, the method specifically comprises: depositing polysilicon in the surface of described oxide layer, and fills described first grid electrode hole, then etches, and removes the polysilicon outside described first grid electrode hole, forms first grid electrode.
10. manufacture method according to claim 8, is characterized in that,
In step s 8, deposit isolating oxide layer and metal, form source electrode, the method specifically comprises: deposit isolating oxide layer, and etches between described groove, form contact hole, then ion implantation is in ohmic contact regions, with the Metal Contact of deposit, forms source electrode.
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