CN105514149A - Groove type FRD chip and preparation method - Google Patents
Groove type FRD chip and preparation method Download PDFInfo
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- CN105514149A CN105514149A CN201510990458.0A CN201510990458A CN105514149A CN 105514149 A CN105514149 A CN 105514149A CN 201510990458 A CN201510990458 A CN 201510990458A CN 105514149 A CN105514149 A CN 105514149A
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- 238000002360 preparation method Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 25
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims abstract description 13
- 239000004411 aluminium Substances 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 238000004026 adhesive bonding Methods 0.000 claims description 16
- 238000003475 lamination Methods 0.000 claims description 11
- 238000004140 cleaning Methods 0.000 claims description 10
- 238000004544 sputter deposition Methods 0.000 claims description 10
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 8
- 238000011161 development Methods 0.000 claims description 8
- 239000002904 solvent Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 239000002131 composite material Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 239000013067 intermediate product Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 238000011084 recovery Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention discloses a groove type FRD chip. The groove type FRD chip includes an N+ substrate layer, an N-epitaxial layer, a P type doped region, an oxide layer, an aluminum layer and a metal layer; the N- epitaxial layer is arranged on the N+ substrate layer; the P type doped region is arranged on the N-epitaxial layer; the oxide layer is arranged on the P type doped region of a terminal region; the aluminum layer is arranged on the P type doped region of an active region; the metal layer is arranged at one side of the N+ substrate layer far away from the N- epitaxial layer; terminal region grooves are formed in the P type doped region of the terminal region through etching; active region grooves are formed in the P type doped region of the active region through etching; and the terminal region grooves and the active region grooves are filled with oxides. According to the groove type FRD chip of the invention, the groove structure is adopted, and therefore, forward voltage drop can be effectively reduced, the risk of electric leakage can be reduced, high efficiency and safety in the use process of the groove type FRD chip can be ensured, and production cost can be effectively reduced. The structure of the groove type FRD chip is simple.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly, relate to a kind of groove-shaped FRD chip and preparation method.
Background technology
FRD and fast recovery diode, be a kind ofly have that switching characteristic is good, reverse recovery time short feature semiconductor diode.The internal structure of fast recovery diode is PN diode and Schottky diode parallel-connection structure, and it comprises pressure ring (guard ring) region and the termination environment of the middle service area of chip and active area and service area surrounding by functional regional division.Traditional F RD chip structure is complicated, and manufacturing process generally needs 4-6 road photo-mask process, along with increasing of photoetching number of times, the cost of manufacture of chip also increases thereupon, and due to the limitation of product structure, its forward voltage drop is higher, and there is certain electric leakage risk, fail safe is poor.
Summary of the invention
In order to overcome the deficiencies in the prior art, the object of the present invention is to provide a kind of groove-shaped FRD chip, its slot type structure effectively decreases forward voltage drop, reduce the risk of electric leakage, ensure that the efficient and safety in its use procedure, and structure is simple, effectively reduces production cost.
For solving the problem, the technical solution adopted in the present invention is as follows:
A kind of groove-shaped FRD chip, comprise N+ substrate layer, N-epitaxial loayer, P type doped region, oxide layer, aluminium lamination and metal level, described N-epitaxial loayer is arranged on N+ substrate layer, described P type doped region is arranged on N-epitaxial loayer, described oxide layer is arranged on the P type doped region of termination environment, described aluminium lamination is arranged on the P type doped region of active area, described metal level is arranged on the side of N+ substrate layer away from N-epitaxial loayer, termination environment groove is etched with in the P type doped region of described termination environment, active area groove is etched with in the P type doped region of described active area, oxide is filled with in described termination environment groove and active area groove.
Preferably, described oxide layer and oxide are silicon dioxide, and described oxidated layer thickness is 1.5-2.0 μm.
Preferably, described P type doped region junction depth 2.8-3.2 μm.
Preferably, described termination environment groove and active area gash depth are 3.8-4.2 μm, and described termination environment groove is the closed annular trench being surrounded with source region groove.
Preferably, described metal level is Ti/Ni/Ag composite bed, wherein, Ti layer thickness is 0.1-0.3 μm, Ni layer thickness be 0.1-0.3 μm, Ag layer thickness is 0.7-1.0 μm, described Ti layer contacts with N+ substrate layer 1, and Ni layer is arranged on Ti layer, and Ag layer is arranged on Ni layer.
The present invention also provides a kind of preparation method of groove-shaped FRD chip, comprises the following steps:
1), after N+ substrate layer and N-epitaxial loayer being cleaned, at the diffusion of N-epi-layer surface or injection boron ion, P type doped region is formed;
2) by gluing, exposure, development and etching technics, in the P type doped region of termination environment, etching forms termination environment groove respectively, after in the P type doped region of active area, etching is formed with source region groove, removal gluing process is coated in the photoresist on P type doped region;
3) deposition oxide on P type doped region, by gluing, exposure, development and etching technics, etching removing is deposited on the oxide on the surface, P type doped region of active area, retains the oxide being deposited on the surface, P type doped region of termination environment, forms oxide layer; Reservation gluing process is coated in the photoresist in oxide layer;
4) clean after splash-proofing sputtering metal aluminium on P type doped region, removal step 3) in be coated in the photoresist in oxide layer and the metallic aluminium above photoresist, retain and sputter at the metallic aluminium on the surface, P type doped region of active area, form aluminium lamination;
5), after reduction processing being carried out away from the side of N-epitaxial loayer to N+ substrate layer, form metal level at its surface sputtering or evaporation, obtain described groove-shaped FRD chip.
Further, described step 4) cleaning of middle cleaning employing chemical solvent, described chemical solvent is liquid or the acetone of removing photoresist.
Further, described P type doped region junction depth 2.8-3.2 μm; Described termination environment groove and active area gash depth are 3.8-4.2 μm, and described termination environment groove is the closed annular trench being surrounded with source region groove.
Further, described oxide layer and oxide are silicon dioxide, and described oxidated layer thickness is 1.5-2.0 μm.
Further, described metal level is Ti/Ni/Ag composite bed, wherein, Ti layer thickness is 0.1-0.3 μm, Ni layer thickness be 0.1-0.3 μm, Ag layer thickness is 0.7-1.0 μm, described Ti layer contacts with N+ substrate layer 1, and Ni layer is arranged on Ti layer, and Ag layer is arranged on Ni layer.
Compared to existing technology, beneficial effect of the present invention is: the present invention adopts slot type structure, effectively decrease forward voltage drop, reduce the risk of electric leakage, ensure that the efficient and safety in its use procedure, and its production process only needs to adopt twice photo-mask process can complete, compared with the FRD chip preparation method needing 4-6 road photo-mask process with tradition, preparation process greatly reduces, and greatly saves the cost of manufacture of chip.
Accompanying drawing explanation
Fig. 1 is groove-shaped FRD chip cutaway view in the present invention;
Fig. 2 is step 1 in preparation method of the present invention) the intermediate products cutaway view that formed;
Fig. 3 is step 2 in preparation method of the present invention) the intermediate products structural representation that formed;
Fig. 4 is step 2 in preparation method of the present invention) the intermediate products cutaway view that formed;
Fig. 5 is step 3 in preparation method of the present invention) the intermediate products cutaway view that formed;
Fig. 6 is step 4 in preparation method of the present invention) the intermediate products cutaway view that formed;
Wherein, 1 be N+ substrate layer, 2 be N-epitaxial loayer, 3 be P type doped region, 41 be termination environment groove, 42 be active area groove, 5 be oxide layer, 6 be photoresist, 7 be aluminium lamination, 8 for metal level.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figure 1, groove-shaped FRD chip in one embodiment of the invention, comprise N+ substrate layer 1, N-epitaxial loayer 2, P type doped region 3, oxide layer 5, aluminium lamination 7 and metal level 8, N-epitaxial loayer 2 is arranged on N+ substrate layer 1, P type doped region 3 is arranged on N-epitaxial loayer 2, oxide layer 5 is arranged on the P type doped region 3 of termination environment, aluminium lamination 7 is arranged on the P type doped region 3 of active area, metal level 8 is arranged on the side of N+ substrate layer 1 away from N-epitaxial loayer 2, termination environment groove 41 is etched with in the P type doped region 3 of termination environment, active area groove 42 is etched with in the P type doped region 3 of active area, oxide is filled with in termination environment groove 41 and active area groove 42.P type doped region 3 junction depth 3.0 μm in this groove-shaped FRD chip, termination environment groove 41 and active area groove 42 degree of depth are 4.0 μm, termination environment groove 41 is for being surrounded with the closed annular trench of source region groove 42, active area groove 42 can be produced as different shapes according to product demand, oxide layer 5 and oxide are silicon dioxide, oxide layer 5 thickness is 1.6 μm, and oxide layer 5 makes groove-shaped FRD chip surface form passivation layer, makes chip from damages such as pollution, damages; Metal level 8 is Ti/Ni/Ag composite bed, and wherein, Ti layer thickness is 0.2 μm, and Ni layer thickness is 0.2 μm, and Ag layer thickness is 0.8 μm, and Ti layer contacts with N+ substrate layer 1, and Ni layer is arranged on Ti layer, and Ag layer is arranged on Ni layer.
Certainly, in above-described embodiment, each component specification size also has other to select, as: P type doped region 3 junction depth is 2.8-3.2 μm, and termination environment groove 41 and active area groove 42 degree of depth are 3.8-4.2 μm, and oxide layer 5 thickness is 1.5-2.0 μm, in metal level 8, Ti layer thickness is 0.1-0.3 μm, Ni layer thickness is 0.1-0.3 μm, Ag layer thickness is 0.7-1.0 μm, within the scope of these, in the present invention, all to have pressure drop low for groove-shaped FRD chip, the feature that electric leakage risk is lower.
Be more than the description of groove-shaped FRD chip structure in the present invention, below its preparation method be explained in further detail.
A preparation method for groove-shaped FRD chip, comprises the following steps:
1), after cleaning N+ substrate layer 1 and N-epitaxial loayer 2, at N-epitaxial loayer 2 diffusion into the surface or injection boron ion, form P type doped region 3, the intermediate products of formation as shown in Figure 2;
Further, in this step, P type doped region 3 junction depth is preferably 2.8-3.2 μm;
2) by gluing, exposure, development and etching technics, in the P type doped region of termination environment, 3 etchings form termination environment groove 41 respectively, after in the P type doped region 3 of active area, etching is formed with source region groove 42, removal gluing process is coated in the photoresist on P type doped region 3, and the intermediate products of formation as shown in Figure 3,4;
Further, in this step, termination environment groove 41 and active area groove 42 degree of depth are 3.8-4.2 μm, and termination environment groove 41 is for being surrounded with the closed annular trench of source region groove 42;
3) deposition oxide on P type doped region 3, by gluing, exposure, development and etching technics, etching removing is deposited on the oxide on the surface, P type doped region 3 of active area, retains the oxide being deposited on the surface, P type doped region 3 of termination environment, forms oxide layer 5; Reservation gluing process is coated in the photoresist 6 in oxide layer, and the intermediate products of formation as shown in Figure 5;
Further, in this step, oxide layer 5 and oxide are silicon dioxide, and oxide layer 5 thickness is preferably 1.5-2.0 μm, and oxide layer 5 makes groove-shaped FRD chip surface form passivation layer, makes chip from damages such as pollution, damages;
4) clean after splash-proofing sputtering metal aluminium on P type doped region 3, removal step 3) in be coated in the photoresist 6 in oxide layer 5 and the metallic aluminium above photoresist 6, retain the metallic aluminium sputtering at the surface, P type doped region 3 of active area, form aluminium lamination 7, the intermediate products of formation as shown in Figure 6;
Further, in this step, cleaning adopts chemical solvent cleaning, and described chemical solvent preferably removes photoresist liquid or acetone;
5), after reduction processing being carried out away from the side of N-epitaxial loayer 2 to N+ substrate layer 1, form metal level 8 at its surface sputtering or evaporation, obtain described groove-shaped FRD chip, as shown in Figure 1;
Further, in this step, metal level 8 is Ti/Ni/Ag composite bed, wherein, Ti layer thickness is preferably 0.1-0.3 μm, and Ni layer thickness is preferably 0.1-0.3 μm, and Ag layer thickness is preferably 0.7-1.0 μm, Ti layer contacts with N+ substrate layer 1, and Ni layer is arranged on Ti layer, and Ag layer is arranged on Ni layer.
Below in conjunction with an embodiment, the preparation method to FRD chip groove-shaped in the present invention is described, and comprises the following steps:
1) after cleaning N+ substrate layer 1 and N-epitaxial loayer 2, at N-epitaxial loayer 2 diffusion into the surface boron ion, forming type doped region 3, P type doped region 3, P junction depth is 3 μm;
2) by gluing, exposure, development and etching technics, in the P type doped region of termination environment, 3 etchings form termination environment groove 41 respectively, after in the P type doped region 3 of active area, etching is formed with source region groove 42, removal gluing process is coated in the photoresist on P type doped region 3, termination environment groove 41 and active area groove 42 degree of depth are 4.0 μm, and termination environment groove 41 is for being surrounded with the closed annular trench of source region groove 42;
3) deposition oxide on P type doped region 3, by gluing, exposure, development and etching technics, etching removing is deposited on the oxide on the surface, P type doped region 3 of active area, retains the oxide being deposited on the surface, P type doped region 3 of termination environment, forms oxide layer 5; Reservation gluing process is coated in the photoresist 6 in oxide layer, and oxide layer 5 and oxide are silicon dioxide, and oxide layer 5 thickness is preferably 1.6 μm;
4) clean after splash-proofing sputtering metal aluminium on P type doped region 3, removal step 3) in be coated in the photoresist 6 in oxide layer 5 and the metallic aluminium above photoresist 6, retain the metallic aluminium sputtering at the surface, P type doped region 3 of active area, form aluminium lamination 7, cleaning adopts chemical solvent cleaning, and described chemical solvent is acetone;
5) after reduction processing being carried out away from the side of N-epitaxial loayer 2 to N+ substrate layer 1, metal level 8 is formed at its surface sputtering, obtain described groove-shaped FRD chip, metal level 8 is Ti/Ni/Ag composite bed, wherein, Ti layer thickness is 0.2 μm, Ni layer thickness is 0.2 μm, and Ag layer thickness is 0.8 μm, and Ti layer contacts with N+ substrate layer 1, Ni layer is arranged on Ti layer, and Ag layer is arranged on Ni layer.
Above-mentioned preparation method is adopted to produce groove-shaped FRD chip in batches, because it adopts two road photo-mask processs namely to complete the production of finished product, production cost is significantly reduced, and adopt the structure of plough groove type, test the pressure drop recorded lower, leaky is obviously controlled, and ensure that low cost and the high-quality of production in enormous quantities, the method and product all have good promotion prospect.
To one skilled in the art, according to technical scheme described above and design, other various corresponding change and deformation can be made, and all these change and deformation all should belong within the protection range of the claims in the present invention.
Claims (10)
1. a groove-shaped FRD chip, it is characterized in that, comprise N+ substrate layer, N-epitaxial loayer, P type doped region, oxide layer, aluminium lamination and metal level, described N-epitaxial loayer is arranged on N+ substrate layer, described P type doped region is arranged on N-epitaxial loayer, described oxide layer is arranged on the P type doped region of termination environment, described aluminium lamination is arranged on the P type doped region of active area, described metal level is arranged on the side of N+ substrate layer away from N-epitaxial loayer, termination environment groove is etched with in the P type doped region of described termination environment, active area groove is etched with in the P type doped region of described active area, oxide is filled with in described termination environment groove and active area groove.
2. groove-shaped FRD chip as claimed in claim 1, is characterized in that, described oxide layer and oxide are silicon dioxide, and described oxidated layer thickness is 1.5-2.0 μm.
3. groove-shaped FRD chip as claimed in claim 1, is characterized in that, described P type doped region junction depth 2.8-3.2 μm.
4. groove-shaped FRD chip as claimed in claim 1, is characterized in that, described termination environment groove and active area gash depth are 3.8-4.2 μm, and described termination environment groove is the closed annular trench being surrounded with source region groove.
5. the groove-shaped FRD chip as described in any one of claim 1-4, it is characterized in that, described metal level is Ti/Ni/Ag composite bed, wherein, Ti layer thickness is 0.1-0.3 μm, Ni layer thickness is 0.1-0.3 μm, Ag layer thickness is 0.7-1.0 μm, described Ti layer contacts with N+ substrate layer 1, and Ni layer is arranged on Ti layer, and Ag layer is arranged on Ni layer.
6. the preparation method of groove-shaped FRD chip described in claim 1, comprises the following steps:
1), after N+ substrate layer and N-epitaxial loayer being cleaned, at the diffusion of N-epi-layer surface or injection boron ion, P type doped region is formed;
2) by gluing, exposure, development and etching technics, in the P type doped region of termination environment, etching forms termination environment groove respectively, after in the P type doped region of active area, etching is formed with source region groove, removal gluing process is coated in the photoresist on P type doped region;
3) deposition oxide on P type doped region, by gluing, exposure, development and etching technics, etching removing is deposited on the oxide on the surface, P type doped region of active area, retains the oxide being deposited on the surface, P type doped region of termination environment, forms oxide layer; Reservation gluing process is coated in the photoresist in oxide layer;
4) clean after splash-proofing sputtering metal aluminium on P type doped region, removal step 3) in be coated in the photoresist in oxide layer and the metallic aluminium above photoresist, retain and sputter at the metallic aluminium on the surface, P type doped region of active area, form aluminium lamination;
5), after reduction processing being carried out away from the side of N-epitaxial loayer to N+ substrate layer, form metal level at its surface sputtering or evaporation, obtain described groove-shaped FRD chip.
7. the preparation method of groove-shaped FRD chip as claimed in claim 6, is characterized in that, described step 4) cleaning of middle cleaning silicon chip employing chemical solvent, described chemical solvent is liquid or the acetone of removing photoresist.
8. the preparation method of groove-shaped FRD chip as claimed in claim 6, is characterized in that, described P type doped region junction depth 2.8-3.2 μm; Described termination environment groove and active area gash depth are 3.8-4.2 μm, and described termination environment groove is the closed annular trench being surrounded with source region groove.
9. the preparation method of groove-shaped FRD chip as claimed in claim 6, is characterized in that, described oxide layer and oxide are silicon dioxide, and described oxidated layer thickness is 1.5-2.0 μm.
10. the preparation method of groove-shaped FRD chip as claimed in claim 6, it is characterized in that, described metal level is Ti/Ni/Ag composite bed, wherein, Ti layer thickness is 0.1-0.3 μm, Ni layer thickness is 0.1-0.3 μm, Ag layer thickness is 0.7-1.0 μm, described Ti layer contacts with N+ substrate layer 1, and Ni layer is arranged on Ti layer, and Ag layer is arranged on Ni layer.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100230745A1 (en) * | 2009-03-16 | 2010-09-16 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| CN102867849A (en) * | 2011-07-08 | 2013-01-09 | 盛况 | Fast recovery diode and manufacturing method thereof |
| CN103489925A (en) * | 2012-06-12 | 2014-01-01 | 韩国电子通信研究院 | Semiconductor device and method for manufacturing same |
| CN205248281U (en) * | 2015-12-24 | 2016-05-18 | 张家港意发功率半导体有限公司 | Ditch cell type FRD chip |
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- 2015-12-24 CN CN201510990458.0A patent/CN105514149B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100230745A1 (en) * | 2009-03-16 | 2010-09-16 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| CN102867849A (en) * | 2011-07-08 | 2013-01-09 | 盛况 | Fast recovery diode and manufacturing method thereof |
| CN103489925A (en) * | 2012-06-12 | 2014-01-01 | 韩国电子通信研究院 | Semiconductor device and method for manufacturing same |
| CN205248281U (en) * | 2015-12-24 | 2016-05-18 | 张家港意发功率半导体有限公司 | Ditch cell type FRD chip |
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