CN105510794A - Heat resistance measurement method for pseudomorphic high electron mobility transistor (PHEMT) - Google Patents
Heat resistance measurement method for pseudomorphic high electron mobility transistor (PHEMT) Download PDFInfo
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- CN105510794A CN105510794A CN201610015695.XA CN201610015695A CN105510794A CN 105510794 A CN105510794 A CN 105510794A CN 201610015695 A CN201610015695 A CN 201610015695A CN 105510794 A CN105510794 A CN 105510794A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N25/00—Investigating or analyzing materials by the use of thermal means
- G01N25/20—Investigating or analyzing materials by the use of thermal means by investigating the development of heat, i.e. calorimetry, e.g. by measuring specific heat, by measuring thermal conductivity
Abstract
The invention discloses a heat resistance measurement method for a pseudomorphic high electron mobility transistor (PHEMT); by adopting the heat resistance measurement method, the temperature measurement is accurate, and damage to the PHEMT and measurement errors are not easy to cause. The method is implemented by the following technical scheme: a semiconductor heat resistance measurement instrument T3ster provides a current source to load current between a drain electrode and a source electrode of the PHEMT; a channel of the PHEMT is heated by the internal resistance of the transistor, then a T3ster peripheral control circuit performs instantaneous circuit switching, and the heating is stopped instantaneously; in the process, a voltage output end Ucb of the T3ster enables a fast recovery diode to be positively biased, under the effect of partial voltage of a divider resistor R1 connected with the Ucb on the Ucb, pinch-off voltage between a grid electrode G and the source electrode S of the PHEMT to be measured is generated, and reversal of biasing between the grid electrode G and the source electrode S of the PHEMT is realized; after the circuit switching, positive biasing between the grid electrode G and the source electrode S is realized, and the voltage drop reflects a temperature. Heat resistance is obtained according to a temperature change value measured by the T3ster by using data processing software Master of the T3ster in a computer.
Description
Technical field
The present invention relates to semiconductor thermal test field, for measuring measurement mechanism and the method for testing thereof of the thermal resistance of High Electron Mobility Transistor PHEMT chip.
Background technology
High Electron Mobility Transistor PHEMT is the core devices in solid-state amplifying circuit.High Electron Mobility Transistor PHEMT is as the one in field effect transistor, with its high frequency, at a high speed, low noise, the advantage such as high-power, start in field widespread uses such as communications, made gas sensor and radio-frequency power sensor as sensing unit is then multiplex.PHEMT is actually the appellation to a class field effect tube chip, although the inside has and can be used for electric method and carry out the thermometric Schottky shielding that formed by technique and Schottky.But the characteristic of Schottky causes carrying larger current, Schottky self cannot be utilized as heat source.Use the pattern being undertaken heating by electric current between PHEMT drain electrode and source electrode to carry out Thermal test so normal.When PHEMT drain electrode and source electrode energising, PHEMT pipe starts heating, because PHEMT pipe usually used is depletion type, needs in gate-source, add pre-pinch-off voltage, otherwise directly can cause the permanent damage of PHEMT transistor.
Owing to adopting the efficiency of the monolithic millimeter-wave integrated circuit mmic chip of PHEMT general not high, the thermal value of chip is comparatively large, and particularly in the application such as phased-array radar, this problem is more outstanding.Therefore must carry out thermal design to it, make the working junction temperature just obtaining device at the beginning of design.This improves application system as the important channel of radar and so on equipment performance, and PHEMT transistor chip raceway groove is the core devices parameter of carrying out thermal design to chip installed surface or heat sink thermal resistance.To common field effect transistor, usually adopt the parasitic diode in pipe, if the parasitic fly-wheel diode between drain-source is as sense temperature element (TE), measures its forward voltage drop and vary with temperature process, thus analyze its structure function.The testing tool adopted is generally the semiconductor thermal resistance dedicated testers such as Phase11 or T3ster.The thermo-resistance measurement method that the measurement of PHEMT chip thermal resistance is conventional has infrared scanning imaging method, thermochromic liquid crystal tempil pellets, electric method.
Infrared scanning imaging method is the infrared radiation on PHEMT transistor chip surface when being worked by measuring element and provides the two-dimension temperature distribution of chip surface, characterizes junction temperature and distribution thereof; Thermochromic liquid crystal tempil pellets utilizes liquid crystal at different temperature to the light of constant light source reflection different wave length, presents different colors to carry out temperature survey.The problem of Infrared survey method and infrared scanning imaging method is, needs to uncap process to PHEMT transistor device, destroys encapsulation, easily causes permanent damage to device; And for packaging, infrared imaging method changes the hot road of system, cause the junction temperature that records on the low side, partial heat is delivered to space outerpace, thus causes being difficult to estimate to the error measured; Infrared survey method is easily subject to the impact that other backgrounds invest the radiation energy of surface reflection to be measured, and background invests body surface, and the impact of radiation energy through body surface, cause the inaccurate of thermometric; Infrared survey method also affects by slin emissivity, and the body surface that the body surface emissivity that emissivity is low is high affects larger by ambient temperature, can cause very large measuring error when dut temperature and ambient temperature differ less.Infrared scan image is subject to thermal background emission impact, and the chip functions structure of being heated may be very poor by its imaging effect that affects of surrounding environment, possibly cannot obtain PHEMT transistor chip key structure image clearly.
Thermochromic liquid crystal tempil pellets adopts thermochromic liquid crystal to carry out the subject matter of problem and the Infrared survey measured roughly the same, wherein also relate to following other problems, that is: the thermochromic liquid crystal of employing needs to be coated in measured object surface, the most size of PHEMT chip is minimum and be bare chip, poor operability, and measuring error comparatively Infrared survey is larger.
The ultimate principle of general electric method utilizes existing diode or parasitic diode in PHEMT transistor device, device is placed on one constantly to change in environment temperature, retainer member is consistent with environment temperature, continue in the process to pass through small area analysis to diode, semiconductor PN variations injunction temperature Tj and forward junction change in voltage Vf is made to be good linear relationship, represent by temperature correction COEFFICIENT K, meet relational expression T
j=KV
f+ T
0, thus obtain k-factor value; Then, tested PHEMT transistor device is placed into normal temperature environment, applies power P to whole device, wait for that device reaches thermal equilibrium.The power applied causes variations injunction temperature, utilizes relational expression T
j=KV
f+ T
0, wherein T
0for applying the initial junction temperature before power, k-factor obtains at Part I, therefore can calculate the junction temperature Tj after reaching thermal equilibrium.Directly can be recorded the temperature of shell simultaneously by thermopair at the end of heating power, utilize the computing formula (1) of thermal resistance, device steady state thermal resistance can be obtained
Electricity rule adopts transient thermal to measure, utilize the forward voltage drop of diode and the relation of temperature, the structure function comprising thermal resistance, thermal capacitance is analyzed from transient thermal response curve, obtain the thermal resistance value of the inner each structural sheet of PHEMT transistor packaging, as positions such as chip soldering bed of material shells, judge the quality of PHEMT transistor device thermal behavior with this.The weak point that PHEMT transistor adopts electric method to carry out such chip thermo-resistance measurement is, need manual switching, the time of manual switching is level second, and speed is fast not, easily causes PHEMT transistor chip to damage or very large test error.As added current flow heats between PHEMT transistor drain and source class, grid and source electrode need add pinch-off voltage; Heat complete, heating current between hand off drain electrode and source class, and then manually turn off and make grid and the reverse-biased voltage of source electrode, simultaneously manually on grid and source electrode, load the small area analysis making the Isense of its positively biased.In this process, if gate source voltage across poles transfers positively biased to too early by reverse-biased, easily cause Schottky to damage, evening, then channel temperature decline stage process cannot arrive by complete measument excessively, caused measuring error.Electric method is adopted to be that its Schottky is very fragile to the subject matter that PHEMT tests, directly cannot utilize schottky diode parasitic between grid G, source S, if it can be used as thermal source to use, big current is adopted to carry out loading heating to parasitic diode, Schottky will breakdown, damage, cause measured device permanent damage.
Through retrieval, find that corresponding relevant patent of invention is less at present, and the application for a patent for invention that the present invention is correlated with the most is as follows:
[1] China Patent Publication No. CN201310185075.7 [P] .2013-9-4, name disclosed in Beijing University of Technology is called a kind of method measuring the material interface temperature rise of thin layer heterogeneous semiconductor and thermal resistance, what describe is that a kind of laser that utilizes carries out adding the method that heat utilization Schottky carries out temperature test, [1] have employed outside laser as thermal source, using Schottky as the temperature rise of sensor measurement small film heterogeneous interface, Schottky is always in forward bias condition, and avoiding heating when adopting common electric method to measure needs to use the problem of reverse-biased.But the method is not suitable for the measurement of practical devices, just must uncap if practical devices exists encapsulation, easily cause device failure, if device size is little, the power then heated cannot determine to be applied to MMIC on earth accurately, and that is tied, and test needs powerful optical device etc.The operability of itself and test is poor, and the cost of test is higher.
[2] Chinese patent application publication number CN201310591383.X [P] .2014-3-5 discloses the temperature rise of a kind of Schottky gate field effect transistor and thermal resistance measurement method and device.Describe the peripheral control circuits of [1], have employed FPGA control mode, devise power up accordingly, power-off, record control circuit, have employed FPGA as control core unit, coordinate voltage, current acquisition card and host computer, utilize the mode doing thermal source by electric current between drain-source to heat raceway groove.
[3] China Patent Publication No. CN201110066983.5 [P] .2011-10-5. discloses a kind of method and the device thereof that utilize the method for testing of Schottky measurement LED junction temperature and utilize pn knot measurement LED thermal resistance.Schottky in LED then only uses as temperature element by patented claim [3], as the foundation of design lamps.
Above-mentioned patented claim [1]-[3] are all adopt Schottky as temperature element ultimate principle, unlike on the Row control to measurement and in purposes.
Summary of the invention
The object of the invention is the weak point existed for prior art, in conjunction with the function of existing T3ster Thermal test instrument, a kind of good operability is provided, switch fast, thermometric is accurate, not easily causes the method for testing of the High Electron Mobility Transistor PHEMT thermal resistance of the damage of PHEMT transistor chip and test error.
The present invention realizes the solution of above-mentioned purpose: a kind of method of testing of High Electron Mobility Transistor PHEMT thermal resistance, it is characterized in that comprising the steps: to adopt the Schottky of PHEMT inside to use as sensor, by semiconductor thermal resistance testing tool T3ster provide current source directly between the drain D and source S of PHEMT transistor loading current PHEMT transistor channel is heated, then moment circuit switching is realized by PHEMT transistor outside T3ster thermo-resistance measurement peripheral control circuits, heating is stopped instantaneously, after circuit switches, positively biased between grid G and source S, control T3ster voltage output end Ucb makes fast recovery diode positively biased simultaneously, at drain D and the divider resistance R of described peripheral control circuits electrical connection PHEMT, under the dividing potential drop effect of the divider resistance R1 of voltage output end Ucb electrical connection, pinch-off voltage is produced between PHEMT transistor gate G to be measured and source S, reverse-biased is between PHEMT grid G and source S, after PHEMT transistor thermal equilibrium to be measured, stop heating, the heating current broken between drain D and source S, the voltage output end Ucb of control T3ster exports simultaneously, makes fast recovery diode reverse-biased, loaded the small area analysis of < 10mA between the grid G of PHEMT transistor and source S by the measuring current output terminal Sensorcurrent of T3ster simultaneously, the change in voltage of Schottky between grid and source electrode is measured by T3ster Measurement channel, measure temperature variation numerical value, the data recorded utilize the data processing software Master of T3ster and known heat sink temperature in a computer, obtain the junction temperature of PHEMT and the thermal resistance to PHEMT installed surface backboard according to measured temperature change curve.
A kind of High Electron Mobility Transistor PHEMT heat resistance test apparatus utilizing above-mentioned PHEMT thermo-resistance measurement method, comprise PHEMT thermo-resistance measurement circuit and utilize semiconductor thermal resistance testing tool T3ster PHEMT to be carried out to the peripheral control circuits of thermo-resistance measurement, it is characterized in that: PHEMT thermo-resistance measurement circuit is by two divider resistance R1, the R2 PHEMT transistor gate G that connects with fast recovery diode FRD forms, the positive pole IE+ of T3ster passes through the drain D of PHEMT transistor, connection terminal contact 1 between source S, 2 drain D and the divider resistance R1 being electrically connected PHEMT respectively, voltage output end Ucb is electrically connected on divider resistance R1, the connection terminal contact 6 of the connection terminal contact 5 between divider resistance R2 and resistance R2 input end, the output channel voltage output end Ucb of sensor current output terminal Sensorcurrent and T3ster of T3ster forms respectively by the connection terminal contact 3 between fast recovery diode FRD and PHEMT transistor gate G and the connection terminal contact between connection terminal contact 6 and connection terminal contact 24 closed loop calculated, the current source provided by T3ster is loading current between the drain D, source S of PHEMT transistor directly, T3ster voltage output end Ucb makes fast recovery diode positively biased, pinch-off voltage is produced between PHEMT transistor drain D to be measured and source S, reverse-biased is between grid source electrode, Schottky obtains the time dependent numerical value of temperature immediately as temperature probe, the change in voltage of Schottky between grid G and source S is measured by T3ster Measurement channel, measure temperature variation numerical value, obtain the thermal resistance value of corresponding PHEMT chip.
The present invention has following beneficial effect compared to prior art.
Quick switching.The present invention utilizes existing testing tool T3ster.The data acquisition platform provided based on T3ster tester and controller, utilize the Schottky in PHEMT to be measured to use as schottky diode and the temperature variant pass of its forward voltage drop is that sensor carries out junction temperature measurement.Base oneself upon Commercial semiconductors thermo-resistance measurement instrument; all give commercial apparatus by the part of data acquisition of a kind of Schottky gate field effect transistor temperature rise disclosed in Chinese patent application [2] publication number CN201310591383.X [P] .2014-3-5 and thermal resistance measurement method and control section to have come; adopt fast recovery diode to achieve in test the protection of Schottky and the conversion work of test signal, be mainly used in the measurement of depletion type pipe.Only in peripheral control circuits, increase the switching accurately and fast that bleeder circuit be made up of fast recovery diode just achieves ns magnitude, achieve the measurement of junction temperature to PHEMT to be measured and thermal resistance.Its precision is guaranteed.By the output interface of control T3ster, export different positive and negative voltage, measuring current coordinates peripheral control circuits, achieve the heating of PHEMT raceway groove to be measured, the measurement of channel temperature.
Good operability.The present invention utilizes the characteristic that diode fast recovery diode FRD switching characteristic is good, reverse recovery time is short as high-frequency rectification semiconductor diode, fly-wheel diode or damper diode, in the heating period, by current source directly loading current in the drain electrode and source electrode of PHEMT to be measured, fast recovery diode positively biased simultaneously in peripheral control circuits, pinch-off voltage is had between PHEMT grid to be measured and source electrode, and be in reverse-biased between PHEMT grid to be measured and source electrode, ensure that PHEMT crystal drains and between source electrode, unlikely electric current is excessive and caused cause thermal damage.At cooling stage, peripheral control circuits makes fast recovery diode reverse-biased soon, without pinch-off voltage between PHEMT grid to be measured and source electrode, logical small area analysis between PHEMT grid to be measured and source electrode simultaneously, and be in positively biased state between PHEMT grid and source electrode, the Measurement channel of surveying instrument T3ster measures the pressure drop of Schottky between the grid of PHEMT to be measured and source electrode, thus measure temperature variation numerical value, complete chip testing, well solve prior art and adopt problem the problems referred to above that special FPGA control circuit testing cost is high.Utilize direct-fired mode between the inner drain-source of PHEMT to be measured, just have employed fast recovery diode and carry out signal switching, avoid the deficiency of prior art operability difference.
Thermometric is accurate, the present invention utilizes inner structure to be different from common PN junction diode, base I is added in the middle of P-type silicon material and N-type silicon materials, form the fast recovery diode of PIN silicon chip, because base is very thin, QRR is very little, shorter with the reverse recovery time of fast recovery diode, forward voltage drop is lower, several output port of the peripheral control circuits that the feature that breakdown reverse voltage (withstand voltage) is higher designs and T3ster and controlling functions thereof, adopt the current source provided by T3ster directly in the drain D of PHEMT transistor, loading current between source S, T3ster voltage output end Ucb makes fast recovery diode positively biased, pinch-off voltage is produced between PHEMT transistor drain D to be measured and source S, reverse-biased is between grid source electrode, Schottky obtains the time dependent numerical value of temperature immediately as temperature probe, the change in voltage of Schottky between grid G and source S is measured by T3ster Measurement channel, measure temperature variation numerical value, obtain the thermal resistance value of corresponding PHEMT chip, thermometric is accurate.
PHEMT transistor chip is not easily caused to damage and test error.The present invention adopts by two divider resistance R1, R2 connects with fast recovery diode FRD the PHEMT thermo-resistance measurement circuit that PHEMT transistor gate G forms, the positive pole IE+ of T3ster passes through the drain D of PHEMT transistor, connection terminal contact 1 between source S, 2 drain D and the resistance R1 being electrically connected PHEMT respectively, voltage output end Ucb is electrically connected on divider resistance R1, the connection terminal contact 6 of the connection terminal contact 5 between divider resistance R2 and resistance R2 input end, the output channel voltage output end Ucb of sensor current output terminal Sensorcurrent and T3ster of T3ster forms respectively by the connection terminal contact 3 between fast recovery diode FRD and PHEMT transistor gate G and the connection terminal contact between connection terminal contact 6 and connection terminal contact 24 closed loop calculated, the Schottky in PHEMT is utilized to carry out Thermal test as sensor, can not to break a seal dress for PHEMT device, and when not producing any irreversible damage, side measures the thermal resistance of PHEMT device in a short period of time.Avoiding prior art directly uses Schottky to do thermal source, or directly between drain electrode and source electrode, heats the permanent damage of the PHEMT transistor to be measured caused with big current, damages the problem of measured device.
Accompanying drawing explanation
Fig. 1 is the peripheral control circuits principle of High Electron Mobility Transistor PHEMT heat resistance test apparatus of the present invention and the annexation schematic diagram with T3ster.
In figure: 1,2,3,4,5,6 is connection terminal contacts of peripheral control circuits.
Embodiment
Consult Fig. 1.In embodiment described below, being peripheral control circuits below dotted line, more than dotted line is commercial T3ster semiconductor thermal resistance tester.High Electron Mobility Transistor PHEMT heat resistance test apparatus, comprise: PHEMT thermo-resistance measurement circuit and utilize semiconductor thermal resistance testing tool T3ster PHEMT to be carried out to the peripheral control circuits of thermo-resistance measurement, wherein: PHEMT thermo-resistance measurement circuit is by two divider resistance R1, the R2 PHEMT transistor gate G that connects with fast recovery diode FRD forms, the positive pole IE+ of T3ster passes through the drain D of PHEMT transistor, connection terminal contact 1 between source S, 2 drain D and the resistance R1 being electrically connected PHEMT respectively, voltage output end Ucb is electrically connected on resistance R1, the connection terminal contact 6 of the connection terminal contact 5 between resistance R2 and resistance R2 input end, the output channel voltage output end Ucb of sensor current output terminal Sensorcurrent and T3ster of T3ster forms respectively by the connection terminal contact 3 between fast recovery diode FRD and PHEMT transistor gate G and the connection terminal contact between connection terminal contact 6 and connection terminal contact 24 closed loop calculated, the current source provided by T3ster is loading current between the drain D, source S of PHEMT transistor directly, T3ster voltage output end Ucb makes fast recovery diode positively biased, pinch-off voltage is produced between PHEMT transistor drain D to be measured and source S, reverse-biased is between grid source electrode, Schottky obtains the time dependent numerical value of temperature immediately as temperature probe, the change in voltage of Schottky between grid G and source S is measured by T3ster Measurement channel, measure temperature variation numerical value, obtain the thermal resistance value of corresponding PHEMT chip.
Utilize the method for testing of above-mentioned PHEMT heat resistance test apparatus High Electron Mobility Transistor PHEMT thermal resistance, mainly comprise the steps: to adopt the Schottky of PHEMT inside to use as sensor, current source directly loading current between the drain-source of PHEMT transistor is provided by T3ster, the drain D of recycling PHEMT transistor, the heating to Schottky is realized by electric current between source S, then realize the circuit of moment by PHEMT transistor external semiconductor thermo-resistance measurement instrument thermo-resistance measurement peripheral control circuits to switch, heating is stopped instantaneously, control semiconductor thermal resistance testing tool T3ster voltage output end Ucb simultaneously and make fast recovery diode positively biased, at drain D and the divider resistance R1 of described peripheral control circuits electrical connection PHEMT, under the dividing potential drop effect of the divider resistance R1 that voltage output end Ucb is electrically connected, pinch-off voltage is produced between PHEMT transistor drain D to be measured and source S, reverse-biased is between PHEMT drain D and source S, after PHEMT transistor thermal equilibrium, stop heating, the heating current broken between drain D and source S, the voltage output end Ucb of control T3ster exports simultaneously, make fast recovery diode reverse-biased, simultaneously add small area analysis by the measuring current output terminal Sensorcurrent of T3ster between the grid G of PHEMT transistor and source S, the change in voltage of Schottky between grid and source electrode is measured by T3ster Measurement channel, measure temperature variation numerical value, the data recorded utilize the data processing software Master of T3ster and known heat sink temperature in a computer, obtain the junction temperature of PHEMT and the thermal resistance to PHEMT installed surface backboard according to measured temperature change curve.
In specific implementation step, first, export as-U by the voltage output end Ucb output channel of the data processing software control T3ster tester on computing machine; The conducting of fast recovery diode D1 positively biased, PHEMT thermal resistance is under the dividing potential drop effect of peripheral control circuits divider resistance R2, the connection terminal 3 of PHEMT to be measured, connection terminal 4 have reverse bias voltage to cause PHEMT grid G, source S reverse-biased, provide the pre-pinch-off voltage between PHEMT grid G to be measured, source S;
Meanwhile, exporting larger heating current between connection terminal 1, connection terminal 2 by the IE+ of the data processing software control T3ster on computing machine, making there is heating current between the drain electrode of PHEMT to be measured and source electrode, for heating PHEMT raceway groove to be measured; To the PHEMT transistor channel heating period, by current source directly loading current in the drain D and source S of PHEMT to be measured, fast recovery diode positively biased simultaneously in peripheral control circuits, pinch-off voltage is had between PHEMT grid G to be measured, source S, and be in reverse-biased between PHEMT grid to be measured and source electrode, caused cause thermal damage to ensure between PHEMT crystal drain D and source S that unlikely electric current is excessive.
After being heated to steady state (SS), the output channel voltage output end Ucb of control T3ster tester exports as+U, cause the reverse-biased cut-off of fast recovery diode D1, PHEMT grid and source electrode between reversed bias voltage disappear, export < 10mA small area analysis by the sensor current output terminal Sensorcurrent of T3ster between connection terminal 3, connection terminal 4 simultaneously, make there is forward bias voltage between the grid G of PHEMT to be measured, source S; And simultaneously, it is 0 that T3ster controls heating current between the drain electrode of its IE+ current output terminal output and source electrode, stops the heating of PHEMT raceway groove to be measured simultaneously; At cooling stage, peripheral control circuits makes fast recovery diode reverse-biased soon, without pinch-off voltage between PHEMT grid to be measured and source electrode, logical small area analysis between PHEMT grid G to be measured and source S simultaneously, and be in positively biased state between PHEMT grid G and source S, the Measurement channel of surveying instrument T3ster measures the pressure drop of Schottky between the grid of PHEMT to be measured and source electrode, thus measures PHEMT temperature variation numerical value to be measured, completes PHEMT chip testing to be measured.
Owing to having small area analysis to pass through Schottky between the grid G of PHEMT to be measured and source S, Schottky interpolar produces forward voltage drop, change in pressure drop have recorded heating and stops rear channel temperature change procedure, and as sensor output temperature voltage signal, pass semiconductor thermal resistance tester T3ster record back by the test channel port Uch1 test channel of T3ster, test completes.
PHEMT to be measured has carried out change in pressure drop in advance and temperature relation k-factor is demarcated, the data recorded utilize the data processing software Master of T3ster and known heat sink temperature in a computer, can obtain the junction temperature of PHEMT and the thermal resistance to installed surface backboard according to measured temperature change curve.
Claims (9)
1. the method for testing of a High Electron Mobility Transistor PHEMT thermal resistance, it is characterized in that comprising the steps: to adopt the Schottky of PHEMT inside to use as sensor, by semiconductor thermal resistance testing tool T3ster provide current source directly between the drain D and source S of PHEMT transistor loading current PHEMT transistor channel is heated, then moment circuit switching is realized by PHEMT transistor outside T3ster thermo-resistance measurement peripheral control circuits, heating is stopped instantaneously, after circuit switches, positively biased between grid G and source S, control T3ster voltage output end Ucb makes fast recovery diode positively biased simultaneously, at drain D and the divider resistance R of described peripheral control circuits electrical connection PHEMT, under the dividing potential drop effect of the divider resistance R1 of voltage output end Ucb electrical connection, pinch-off voltage is produced between PHEMT transistor gate G to be measured and source S, reverse-biased is between PHEMT grid G and source S, after PHEMT transistor thermal equilibrium to be measured, stop heating, the heating current broken between drain D and source S, the voltage output end Ucb of control T3ster exports simultaneously, makes fast recovery diode reverse-biased, loaded the small area analysis of < 10mA between the grid G of PHEMT transistor and source S by the measuring current output terminal Sensorcurrent of T3ster simultaneously, the change in voltage of Schottky between grid and source electrode is measured by T3ster Measurement channel, measure temperature variation numerical value, the data recorded utilize the data processing software Master of T3ster and known heat sink temperature in a computer, obtain the junction temperature of PHEMT and the thermal resistance to PHEMT installed surface backboard according to measured temperature change curve.
2. the method for testing of High Electron Mobility Transistor PHEMT thermal resistance as claimed in claim 1, is characterized in that: the voltage output end Ucb output channel of the data processing software control T3ster tester on computing machine exports as-U; The conducting of fast recovery diode D1 positively biased, PHEMT thermal resistance is under the dividing potential drop effect of peripheral control circuits divider resistance R1, the connection terminal 3 of PHEMT to be measured, connection terminal 4 have reverse bias voltage to cause PHEMT grid G, source S reverse-biased, provide the pre-pinch-off voltage between PHEMT grid G to be measured, source S.
3. the method for testing of High Electron Mobility Transistor PHEMT thermal resistance as claimed in claim 1, it is characterized in that: the IE+ of the data processing software control T3ster on computing machine exports larger heating current between connection terminal 1, connection terminal 2, make there is heating current between the drain electrode of PHEMT to be measured and source electrode, for heating PHEMT raceway groove to be measured.
4. the method for testing of High Electron Mobility Transistor PHEMT thermal resistance as claimed in claim 1, it is characterized in that: to the PHEMT transistor heating period, by current source directly loading current in the drain D and source S of PHEMT to be measured, fast recovery diode positively biased simultaneously in peripheral control circuits, there is pinch-off voltage between PHEMT grid to be measured and source electrode, and be in reverse-biased between PHEMT grid G to be measured, source S.
5. the method for testing of High Electron Mobility Transistor PHEMT thermal resistance as claimed in claim 1, it is characterized in that: after being heated to steady state (SS), the output channel voltage output end Ucb of control T3ster tester exports as+U, the reverse-biased cut-off of fast recovery diode D1, PHEMT grid and source electrode between reversed bias voltage disappear, exported the small area analysis of < 10mA between connection terminal 3, connection terminal 4 by the sensor current output terminal Sensorcurrent of T3ster simultaneously, between the grid G of PHEMT to be measured, source S, produce forward bias voltage; Between the drain electrode of T3ster control IE+ current output terminal output simultaneously and source electrode, heating current is 0, stops the heating of PHEMT raceway groove to be measured.
6. the method for testing of High Electron Mobility Transistor PHEMT thermal resistance as claimed in claim 1, it is characterized in that: at cooling stage, peripheral control circuits makes fast recovery diode reverse-biased, Schottky for thermometric is present between grid G and source S, PHEMT grid G to be measured and source S are without pinch-off voltage, lead to the small area analysis of < 10mA between PHEMT grid to be measured and source electrode simultaneously, and be in positively biased state between PHEMT grid G and source S, the Measurement channel of surveying instrument T3ster measures the pressure drop of Schottky between the grid G of PHEMT to be measured and source S, thus measure PHEMT temperature variation numerical value to be measured, complete PHEMT chip testing to be measured.
7. the method for testing of High Electron Mobility Transistor PHEMT thermal resistance as claimed in claim 1, it is characterized in that: Schottky interpolar produces forward voltage drop, change in pressure drop have recorded heating and stops rear channel temperature change procedure, and as sensor output temperature voltage signal, pass semiconductor thermal resistance tester T3ster record back by the test channel port Uch1 test channel of T3ster, test completes.
8. one kind utilizes the High Electron Mobility Transistor PHEMT heat resistance test apparatus of method of testing described in claim 1, comprise PHEMT thermo-resistance measurement circuit and utilize semiconductor thermal resistance testing tool T3ster PHEMT to be carried out to the peripheral control circuits of thermo-resistance measurement, it is characterized in that: PHEMT thermo-resistance measurement circuit is by two divider resistance R1, the R2 PHEMT transistor gate G that connects with fast recovery diode FRD forms, wherein, the positive pole IE+ of T3ster passes through the drain D of PHEMT transistor, connection terminal contact 1 between source S, 2 drain D and the divider resistance R1 being electrically connected PHEMT respectively, voltage output end Ucb is electrically connected on divider resistance R1, the connection terminal contact 6 of the connection terminal contact 5 between divider resistance R2 and divider resistance R2 input end, the closed loop that the output channel voltage output end Ucb of sensor current output terminal Sensorcurrent and T3ster of T3ster forms respectively by the connection terminal contact 3 between fast recovery diode FRD and PHEMT transistor gate G and the connection terminal contact between connection terminal contact 6 and connection terminal contact 24.
9. the method for testing of High Electron Mobility Transistor PHEMT thermal resistance as claimed in claim 1, it is characterized in that: the current source provided by T3ster is directly in the drain D of PHEMT transistor, loading current between source S, T3ster voltage output end Ucb makes fast recovery diode positively biased, pinch-off voltage is produced between PHEMT transistor gate G to be measured and source S, reverse-biased is between grid source electrode, Schottky obtains the time dependent numerical value of temperature as temperature probe, measure the change in voltage of Schottky between grid G and source S by T3ster Measurement channel and measure temperature variation numerical value, the thermal resistance value of corresponding PHEMT chip can be obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610015695.XA CN105510794B (en) | 2016-01-11 | 2016-01-11 | High electron mobility transistor PHEMT thermo-resistance measurement methods |
Applications Claiming Priority (1)
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| CN105911447A (en) * | 2016-04-22 | 2016-08-31 | 全球能源互联网研究院 | Power semiconductor device internal contact thermal resistance measurement method and measurement clamp |
| CN106093744A (en) * | 2016-08-04 | 2016-11-09 | 中国科学院微电子研究所 | A kind of thermal resistance acquisition methods |
| CN106124955A (en) * | 2016-06-17 | 2016-11-16 | 中国电子科技集团公司第十研究所 | The transient electrical method of testing of liquid cold plate thermal resistance |
| CN106404828A (en) * | 2016-08-26 | 2017-02-15 | 中国电子科技集团公司第十研究所 | Testing method for thermal resistance of LRM cold plate |
| CN107192935A (en) * | 2017-07-07 | 2017-09-22 | 成都海威华芯科技有限公司 | A kind of measuring method of GaN HEMT devices thermal resistance and thermal capacitance |
| CN107422243A (en) * | 2017-08-28 | 2017-12-01 | 中国电子产品可靠性与环境试验研究所 | Gallium nitride HEMT device junction temperature test device, test board, test system and its method |
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