CN105474391A - 多管芯细粒度集成电压调节 - Google Patents

多管芯细粒度集成电压调节 Download PDF

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Publication number
CN105474391A
CN105474391A CN201480044455.1A CN201480044455A CN105474391A CN 105474391 A CN105474391 A CN 105474391A CN 201480044455 A CN201480044455 A CN 201480044455A CN 105474391 A CN105474391 A CN 105474391A
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semiconductor device
passive
power
terminal
power consuming
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CN201480044455.1A
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CN105474391B (zh
Inventor
J·L·泽尔贝
E·S·芳
翟军
S·赛尔雷斯
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Apple Inc
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Apple Computer Inc
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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Abstract

本发明描述了一种包括耗电器件(诸如SOC器件)的半导体器件封装件。耗电器件(120)可以包括一个或多个电流消耗元件。无源器件(100)可以耦接(110)到耗电器件。无源器件可以包括形成在半导体基板上的多个无源元件。无源元件可以在半导体基板上被布置成结构(102)的阵列。可以利用一个或多个端子(110)耦接耗电器件和无源器件。可以配置无源器件和耗电器件的耦接，使得耗电器件在功能上确定将使用无源器件元件的方式。

Description

多管芯细粒度集成电压调节
背景技术
技术领域
本发明涉及针对半导体器件用于电源调节的系统和方法。更具体地，本发明涉及利用无源半导体器件进行电压调节。
相关领域描述
当前的片上系统(SOC)器件正在向着更大的功能集成和功率/性能优化方向被推进。因为更大的功能集成的要求，所以越来越多地向SOC器件添加来自多种来源的多个IP块(IP块是可重新使用的逻辑单位、单元或芯片布局设计，有时它们来自不同的单方或来源)。每个个体IP块可以具有其自己独特的电源要求和电力递送挑战。例如，一个IP块可以利用与当前可用的其他供电电压不同的供电电压工作。不同的供电电压可以仅从当前供电电压稍微变化(例如，即使仅约100mV差异)，但不同的供电电压可以汲取大量电流。因为高的电流汲取以及能量效率的重要性，两个供电电压中更高一个的简单LDO(低压差)线性调节器对于低功率设计可能不是令人满意的解决方案。对功率效率的驱动和对SOC器件存在很多供电电压要求的组合可能针对SOC器件和电源管理单元(PMU)之间的连接产生相当复杂的设计。
使用单个IP块还可能在SOC器件中提供多个不同的复杂模拟功能。这些模拟功能中的一些模拟功能可能受益于更高的电压源下的操作。跨器件供应更高电压在一种特定的子部分中提供了模拟性能的改善，然而，可在总体器件操作方面导致功率效率低下。因此，直接为诸如放大器和电流源的模拟功能提供更高的供电电压(例如，独立于其他供电电压向模拟功能供应更高供电电压)可允许在共源共栅放大器、Wilson和/或其他配置中堆叠器件，这可以改善这些关键区域中的模拟性能。
复杂性增大的SOC器件的另一个问题在于，随着器件中耗电结构(例如晶体管)数量的增加，跨器件存在显著的电阻。为了为最后的耗电结构(例如，距PMU“最远”的耗电结构或经受最大电压降的最后耗电结构)维持最高的递送性能，跨SOC器件的供电电压需要尽可能高。然而，提高供电电压受到最靠近PMU的第一个耗电结构能够耐受的最高兼容电压的约束。因为供电电压上限是由最靠近耗电结构的容限设定的，所以最后耗电结构处的IR降(器件两端的电压降)变成不受补偿的损耗，这可能限制SOC器件的性能。由于电源电压降低，这个电压降随着其变成供电电压更大的百分比而变成更显著的问题。这种降低本身受到减小功率消耗的需求的驱动(例如，以减小电池消耗并增加电池寿命)。此外，性能的降低可能因为器件阈值电压(VT)不缩放而加剧。因此，例如，电源电压10％的降低可能导致栅极速度(例如，晶体管速度)20％-30％的减慢，从而进一步加剧SOC性能上的I*R降效应。
在更低电压下提供电力供应的另一个问题是在SOC器件的所选择子块过渡到高度活动模式时需要的电流显著增大。在所选择子块的高度活动模式期间，其他子块(例如，不同的CPU或GPU)可能是空闲的或消耗显著更低的电流。这些空闲子块将理想地保持在不同电力轨上，以便充分隔离电力递送，并提供独立的DVFS(动态电压频率缩放)设置和电力降低功能。分隔电力轨意味着在所选择的子块和空闲子块之间的SOC电力递送上没有共享资源。此类资源可包括封装件上的凸块或球，以及印刷电路板上的配线和部件。对SOC器件提出此类约束可能要求封装件有显著的设计复杂性，以便提供低电感电力递送网络的扩展组。
发明内容
在某些实施例中，半导体器件封装件包括耗电器件(例如，SOC器件)和耦接到耗电器件的无源器件。耗电器件可以包括一个或多个电流消耗元件(例如，块或IP块)。无源器件可以包括形成在半导体基板上的多个无源元件(例如，电容器)。可以将无源元件在半导体或其他基板上布置成结构的阵列。可以利用一个或多个端子(例如，凸块、球或TSV)耦接耗电器件和无源器件。在一些实施例中，半导体器件封装件包括第三半导体器件，诸如存储器器件(例如，DRAM器件)。在一些实施例中，无源器件包括第三半导体器件或存储器器件。
可以将耗电器件耦接到无源器件，使得耗电器件结合使用无源器件上个体无源元件和耗电器件上电流消耗元件的端子阵列以利用不同调节器产生不同的(例如，独立且局部化的)电压岛。可以使用不同的电压调节器在局部化且不同并可能优化的电平上向耗电器件上的不同电流消耗元件(例如，块)提供电力并控制电力。向块提供精细粒度的局部化和不同电压调节允许在离散的块层级上进行功率优化，这实现了系统功率的总体下降并减小了具有速度限制关键路径的块对性能的影响，从而实现了相对于常规外部粗糙电力递送技术的总体功率/性能改善。
附图说明
当结合附图时，参考根据本发明的目前优选的但仅为例示性的实施例的以下详细描述，将更充分地理解本发明的方法与装置的特征和优点，在该附图中：
图1示出了半导体器件封装件的一个实施例的分解图表示。
图2示出了半导体器件封装件的一个实施例的侧视图表示。
图3示出了无源器件的一个实施例的表示。
图4示出了结构的一个可能实施例的示例的放大图。
图5示出了结构的另一个可能实施例的示例的表示。
图6示出了针对图5中所示结构的一般性端子覆盖区。
图7示出了仅具有电容器和端子的结构的一个实施例的示例的表示。
图8示出了使用结构的阵列的端子覆盖区的一个实施例的表示。
图9示出了具有无源器件、耗电器件和存储器器件的封装件的一个实施例的侧视图表示。
图10示出了半导体器件封装件的另一个实施例的侧视图表示。
图11示出了半导体器件封装件的另一个实施例的侧视图表示。
图12示出了具有无源器件、耗电器件和存储器器件的封装件另一个实施例的侧视图表示。
尽管本发明易受各种修改形式和替代形式的影响，但附图中以举例的方式示出了其具体实施例并将在本文详细描述。附图可能不是按比例的。应当理解，附图和具体实施方式并非旨在将本发明限制于所公开的特定形式，而正相反，其目的在于覆盖落在由所附权利要求所限定的本发明的实质和范围内的所有修改形式、等同形式和替代形式。
具体实施方式
半导体器件封装件可以包括耦接在一起的两个或更多个半导体器件。在某些实施例中，封装件中的半导体器件中的至少一个半导体器件是无源半导体器件，并且半导体器件中的至少一个半导体器件是耗电半导体器件(例如，具有电流消耗元件诸如SOC器件的器件)。由于无源器件被集成到封装件中，因此可以将无源器件称为例如集成无源器件(IPD)。
图1示出了半导体器件封装件90的一个实施例的分解图表示。图2示出了半导体器件封装件90的一个实施例的侧视图表示。在某些实施例中，封装件90包括无源器件100、耗电(半导体)器件120和构造封装件122。在一些实施例中，无源器件100、耗电器件120和/或构造封装件122使用类似的基板(例如，硅基基板)。在无源器件100、耗电器件120和/或构造封装件122中使用类似基板可以在每个器件中提供基本类似的热膨胀属性，从而允许在广泛温度范围中工作而不对两个器件之间的连接造成应变。在某些实施例中，无源器件100的尺寸设定成装配在构造封装件122中的凹陷部内。无源器件100可以比耗电器件120小，以允许耗电器件上的区域不被待用于耗电器件的通用I/O的无源器件覆盖。
在某些实施例中，无源器件100和耗电器件120直接彼此耦接。例如，可以如图2所示，利用端子110耦接器件。端子110可以是诸如面对面凸块或球、硅通孔(TSV)或其他三维互连端子的端子。可以利用例如激光钻孔在构造层中形成TSV或其他通孔。在某些实施例中，存在于无源器件100上的某些TSV仅仅用作通过无源器件至封装件或印刷电路板的通路。直接耦接器件可以在无源器件上的元件和耗电器件120上的调节器元件和电流消耗元件之间提供短且非常高密度的连接。
端子110还可以将耗电器件120和/或无源器件100直接耦接到构造封装件122。在耗电器件120和构造封装件122之间耦接的端子110可用于通用I/O连接或用于不涉及集成调节器的电力连接。在一些实施例中，将无源器件100耦接到构造封装件122的一些端子是从耗电器件120直接到构造封装件122的通路(例如，三维通路)端子。如图2所示，构造封装件122可以包括通往封装端子126的配线124。封装端子126可用于将封装件90耦接到印刷电路板(PCB)或其他器件。
耗电器件120例如可以是SOC器件。在某些实施例中，无源器件100包括一个或多个无源元件(例如，无源结构或无源器件)。可以结合耗电器件120上的元件使用无源元件以控制和调节提供给耗电器件的电压。
图3示出了无源器件100的一个实施例的表示。在某些实施例中，无源器件100包括阵列102。阵列102可以包括结构104(例如，无源结构)的基本上规则图案(阵列)。例如，如图3所示，阵列102包括布置成平铺图案的结构104。然而，结构104可以布置成任何基本上规则的图案以在无源器件100上形成阵列102。在一些实施例中，结构104布置成半规则图案，以在无源器件100上形成阵列102。
在某些实施例中，结构104是包括一个或多个无源元件，诸如但不限于电容器(例如，沟槽或其他形式的高密度电容器)的规则图案。结构104可以包括诸如开关的其他元件。图4示出了结构104的一个可能实施例的示例的放大图。如图4所示，显示器104可包括电容器106和四个开关108。端子110可用于将结构104中的元件(例如，电容器106和/或开关108)耦接到另一个结构或另一个半导体器件。在一些实施例中，将通往阵列结构104的端子的连接经由局部面对面凸块或TSV直接耦接到阵列结构正上方或下方的耗电器件120的区域。
在一些实施例中，结构104包括附加元件，诸如电感器或双极器件，其可以提供作为无源器件100上的规则图案的一部分。例如，可以在整个阵列102上提供附加元件或者可以仅在阵列的一部分上提供它们(诸如，围绕器件104用于I/O周边环的环)，因为可能仅针对特定子功能才需要此类结构并可能使用过大区域。
在一些实施例中，阵列102包括阵列结构104的特定部分之间的其他低电阻耦接(例如，电力轨)。可以在无源器件100或在附加器件或半导体器件封装件中的配线层中提供低电阻耦接，该配线层可以通过例如TSV连接的双侧性质耦接到无源器件的后侧。可以使用低电阻耦接来降低电网电阻并改善无源器件100的可编程能力和/或可用性，同时使对耗电器件120的配线层的影响最小化。向低电阻耦接上转移功率可以允许耗电器件有效限定耗电器件和无源器件100之间的局部电压域。
图5示出了阵列元件结构104'的另一个可能实施例的示例的表示。图6示出了针对图5中所示结构104'的一般性端子覆盖区。如图5所示，结构104'可以包括一般6开关构型中的电容器106和开关108。结构104'可以包括八个端子110(图6中所示)，四个端子用于电力连接并且四个端子用于栅极控制。端子110可以是凸块或TSV。可以将一个或多个结构104'布置成一般布局阵列，并且可以利用通过端子110耦接到无源器件的另一个半导体器件(例如，图1和图2中所示的耗电器件120)的连通性来对使用该结构的无源器件进行有效“编程”。这样，可以为具有不同耗电器件120的不同功能使用图3中所示的无源器件100的相同设计。
在某些实施例中，将图3中所示的无源器件100中的若干开关(或其他有源元件)进行最小化。例如，无源器件100可以仅包括电容器(例如，无源元件)或无源器件可以包括电容器和仅几个开关或电力轨。可以在阵列102中的结构104内将电容器和几个开关耦接在一起，以增大阵列的粒度，直到阵列粒度最佳地匹配用于耦接到无源器件100的端子(TSV、凸块或其他连接)的粒度。
图7示出了仅具有电容器106和端子110的无源器件结构104”的一个实施例的另一个示例的表示。在某些实施例中，结构104”(和阵列102)可以被布局(例如设计)成正端子110CAT和负端子110ANO之间具有最大分隔距离。将正端子110CAT和负端子110ANO分隔对于给定电力连接密度最大可能的距离可以使电容器106之间发生短接的可能性最小化。在一些实施例中，分隔正端子110CAT和负端子110ANO基本上禁止电容器106之间发生短接。端子之间不对准可能导致阵列中特定单元的结构具有开路故障(例如，“软”故障)或阵列中两个单元之间发生短接。然而，开路故障可能仅导致电容的较小减少，可以在闭环调节器中对其进行补偿，而短接故障(由端子之间过小距离导致)可以导致无源器件100的产率损耗。
图8示出了针对利用类似于结构104”(图7中所示)的结构的阵列的端子覆盖区800的一个实施例的表示。如图8所示，阵列102'包括9(九)个结构104”'，该结构包括端子110的2×2网格。端子110可以是例如TSV或凸块。除了用于通路(“RT”)资源(例如，三维路由资源)、水平轨道(“HT”)或垂直轨道(“VT”)的端子之外，每个结构104”'包括用于结构中的电容器的阴极(“CAT”)和阳极(“ANO”)的端子。
可以将CAT和ANO端子置于每个结构104”'的对角，以降低端子之间发生短接的可能性。可以沿x方向和y方向在阵列102'中的结构104”'之间交替布置RT端子、HT端子和VT端子。可以为通往水平轨道和/或垂直轨道的连接提供HT端子和VT端子，可以将这些轨道用作电力轨。水平轨道和垂直轨道例如可以包括无源器件100内的金属配线(轨道)112，其提供将电力连接到一个或多个结构的能力。可以在更少的结构中提供HT端子和VT端子，因为低电阻水平轨道和垂直轨道通常比电容器连接需要得更少。在阵列沿x方向或y方向步进时，阵列102'中的无阴影结构104”'(例如，中心阴影结构外部的结构)可以是阵列的交叠区域(例如，在将阵列102'用作基础阵列以产生更大阵列时，这些区域可以重叠)。
在无源器件100中使用没有开关的结构(诸如结构104”或结构104”')可以允许开关元件或其他有源元件基本上(或完全)位于耦接到半导体器件封装件(例如，封装件90)中的无源器件的耗电器件(例如，图1和图2中所示的耗电器件120)上。因此，用于形成无源器件100的处理技术可以专注于产生更好的电容器(例如，产生尽可能接近理想电容器的电容器)和/或诸如电感器或低电阻电力轨的其他无源元件。将处理技术专注于产生无源器件而非产生这些器件与其他有源元件(诸如电压调节器的部件)的组合可以提供改善的可靠性和封装件90中电容器的操作。例如，电容器可以具有等价性较低的串联电阻(ESR)和/或具有从其阳极或阴极端子到地的较低寄生电容。此外，开关主要被移动到耗电器件120，其典型地具有用于生产开关的良好技术。在一些实施例中，无源器件100还可以包含利用与功耗器件120显著不同的工艺开发的开关或其他部件。例如，可以使用氮化镓(GaN)工艺以便支持更高导电性并耐受更高电压。可以使这种针对无源器件100的工艺优化独立于针对耗电器件120的工艺优化。
耗电器件120可以包括典型正常SOC器件的元件。在某些实施例中，耗电器件120耦接到无源器件100，如图1和图2中所示，使得耗电器件利用无源器件上的元件(例如，电容器)端子的网格(例如，阵列)来在调节器之间产生具有精细粒度的不同(例如独立且局部化)的电压调节器。可以为不同的电压调节器提供比耗电器件120上的结构或元件组(例如，诸如IP块的块)可能需要和/或可能直接耐受的更高输入电压。不同的电压调节器可以工作在更高输入电压下，因为分隔并局部化电压调节器允许每个电压调节器直接向其对应块(例如，选择的块)提供期望的输入电压，而不使用封装连接资源。
在使用面对面凸块或球作为端子的实施例中(例如，不使用通过无源器件100的TSV)，可能需要向耗电器件120提供高输入电压而不通过无源器件(例如，用于高输入电压的端子应必须位于被无源器件覆盖的区域的外部)。例如，对于图2中所示的实施例，直接连接无源器件100和耗电器件120的端子110可以是面对面凸块或球，因此，可以将无源器件边缘外部的端子(例如，端子110B)用作用于高输入电压的端子。然而，可以在比不具有无源器件100的封装件低的电流下提供这些高输入电压，因为利用来自无源器件100和耗电器件120的元件组合构建的不同电压调节器允许将电压局部降低到符合耗电器件120上的块的电平。由于功率＝电压*电流，因此提供更高的输入电压(例如，比用于耗电器件120上的块的电压高3-8倍)允许提供更少电流以在耗电器件中实现相同的功率水平，并且因此可以使用更少端子(例如，凸块或球)来向封装件提供电力和接地。
可以将不同电压调节器设计为不同类型的电压调节器，包括但不限于单级或多级开关帽转换器、降压转换器或混合转换器(例如，降压和开关帽转换器的组合)。混合或降压转换器可能需要使用无源器件100或耗电器件120上的电感器。
耗电器件120利用无源器件100上的阵列(例如，阵列102')以通过将阵列(和阵列的结构子集，诸如结构104”或结构104”')映射到为耗电器件产生电压调节器所需的属性中来产生不同的局部化电压调节器。可以通过利用耗电器件120上的逻辑、连通性或任何结构将阵列映射到“程序”或确定无源器件100上的结构或元件和耗电器件上的块之间的连通性。因此，耗电器件120可以根据耗电器件上对应块的需求来确定每个电压调节器中需要什么属性(例如，覆盖和连接的区域、分压比、操作频率、反馈点、使能控制等)。
在某些实施例中，结合耗电器件120上的所选择块使用的无源器件100上的结构在所选择块处或附近的区域中被局部化。例如，如果无源器件相对于耗电器件120垂直堆叠，结合所选择块使用的无源器件100上的结构可以恰好在所选择块下方或恰好在上方。对结合耗电器件120上的所选择块使用的无源器件100上的结构进行局部化减小(或最小化)了电压调节器和由电压调节器供电的所选择块之间的距离。减小电压调节器和所选择块之间的距离并减小连接的阻抗(在3D连通性情况下很大程度上由所选择块上方的端子阵列限定)可以减小或最小化选定块经受的电压I*R降并改善向所选择块配电的效率。减小距离还可以通过向电压调节环路中提供供应电压的极快和局部反馈(例如，高度局部化的反馈响应，这样使电压裕度要求最小化并减少了反馈时间)，利用TSV或凸块连通性提供低电阻并提供更短距离以实现更高电流、更低电压路径(例如，几乎没有或没有板迹线)来减少电压降。此外，减小到所选择块的电压I*R降可以允许增大器件的最大操作频率或允许降低最小操作电压。可以利用活动反馈控制来增大用于所选择块的操作频率或操作电压，以减弱耗电器件120中的老化效应。
在某些实施例中，分隔并局部化不同的电压调节器允许将用于所选择块的输入电压降低到针对期望操作频率的最低操作点。因此，可以向各个块提供独立的DVFS(动态电压和频率缩放)设置和功率降低功能而不影响耗电器件120中的其他块。在此类情况下，可能需要电平转换器用于在不同DVFS电压域中操作的块之间的连接。此外，使用不同的电压调节器允许较高的功率块利用来自具有速度限制关键路径并可以距PMU最远的块的不同电源电压。没有不同的电压调节器，高功率块和具有速度限制关键路径的块可能必须共享电源，并且从而向高功率块提供的电压必须维持在最低电平，以在具有速度限制关键路径的块中保持性能，从而在可能不包含相同关键路径的高功率块中浪费功率。将高功率块的电压调节与具有速度限制关键路径的块的电压调节分隔允许将高功率块提供的功率优化到其自己的关键路径(例如，通过降低电压)，而不影响具有速度限制关键路径的块的性能。根据操作模式或其他条件，不同的块可以具有大大不同的关键路径和功耗，使得在此类块之间共享电源成为优化功耗的不佳想法。
在一些实施例中，耗电器件120中的块的子部分(例如，独立功能诸如CPU或FPU内的ALU或MPY)能够脱离其自己的电压调节器而操作。例如，耗电器件120可以利用针对耗电器件中的块的子部分局部化且不同的无源器件100来限定电压调节器。针对子部分分隔并局部化电压调节允许针对受到不同子部分控制的每个功能优化电压。因此，可以进一步最小化期望操作频率下的功耗。例如，可以利用匹配路径、查找表、作为路径上的检测器的早/晚冗余触发器或其他类似方法来进行电压的此类关键路径优化(例如，基于子部分功能进行优化)。
在一些实施例中，不同电压调节器或调节器的某些子部件中的一个或多个子部件充当功率选通器件，以禁止低功率泄漏，并基本上替代用于减少耗电器件上的泄漏的现有功率选通器件。例如，在降低耗电器件120上的所选择块功率时，可以关闭不同电压调节器(例如，电压调节器的开关帽实施)中的一个或多个开关。关闭开关可以减少活动块中的泄漏而不需要附加功率选通器件，当前耗电器件120中包括该功率选通器件。
在一些实施例中，相邻的不同电压调节器能够根据耗电器件120上的块的需求来共享无源器件100上的资源。例如，已知耗电器件120上的某些功能不同时操作。在此类实施例中，可以通过经由例如通往行或列内的公共轨道的开关来继续行或列连接以包括共享器件来替代地将无源器件120(例如，电容器或无源器件上的铺片)上的结构或元件分配到一个不同的电压调节器或另一个。
在某些实施例中，无源器件100包括一般性结构的规则阵列(例如，可以将无源器件用于两种或更多不同设计的耗电结构)。可以由耦接到一般无源器件的耗电器件来控制使用一般无源器件创建的不同电压调节器的属性。例如，可以在耗电器件上放置用于电压调节器的粒度选择(例如，局部化图案)、控制和驱动电路。因此，可以将一般无源器件用于几种不同的耗电器件或几代不同的类似耗电器件之间，而不修改一般无源器件的设计。例如，可以使用图8中所示的覆盖区800来生成用于许多不同耗电器件(甚至是来自不同制造商的耗电器件)的一般无源器件和/或可以由不同制造商制造一般无源器件，使其具有相同的一般技术规格或一般无源器件连接的“覆盖区”。提供一般性无源器件设计允许优化一般性无源器件的设计和/或制造并降低生产一般性无源器件的成本，因为可以生产一般性无源器件作为可用于跨几种平台和/或几代器件可用的商品。
在一些实施例中，除了无源器件100和耗电器件120之外，半导体器件封装件还包括一个或多个附加器件。例如，除了无源器件100和耗电器件120之外，半导体器件封装件还可以包括存储器器件(例如，DRAM器件，诸如高速或低功率DRAM内核)。图9示出了具有无源器件100、耗电器件120和存储器器件250的封装件200的一个实施例的侧视图表示。封装件200可以包括顶部构造封装件122A和底部构造封装件122B。
存储器器件250可以耦接到顶部封装件122A，而无源器件100和耗电器件120耦接在一起并夹置于顶部封装件和底部封装件122B之间。在某些实施例中，无源器件100和耗电器件120位于顶部封装件122A中的凹陷部中。如图9所示，无源器件100和耗电器件120可以大致是相同的尺寸。因此，无源器件100可以包括通路端子(例如，TSV)，以提供底部封装件122B和耗电器件120之间的一般I/O连接。在一些实施例中，无源器件100比耗电器件120小，如前所述，向由无源器件100重叠的区域外部的耗电器件提供连接。
在一些实施例中，除无源器件阵列之外，无源器件100包括无源器件中的一个或多个其他结构。例如，无源器件100可以包括诸如存储器器件250的结构或其他结构。图10示出了具有集成在无源器件100中的存储器器件250的封装件90'的一个实施例的侧视图表示。图11示出了具有集成在无源器件100中的存储器器件250的封装件200'的一个实施例的侧视图表示。可以在用于形成存储器器件250的过程期间制造无源元件(例如，电容器)。在一些实施例中，对形成存储器器件250的过程稍微修改以包括形成无源元件。
因为无源器件100距耗电器件120相对较近，所以如图10和图11所示，无源器件与耗电器件具有高度连通性。因此，无源器件100可以利用面对面凸块连接或本文论述的其他封装连接来为无源器件(例如，存储器器件250)中的其他结构提供高带宽、低功率连接。因为图10和图11所示的封装件90'和封装件200'的实施例在无源器件100内部具有存储器器件250，所以此类实施例可以在存储器器件和耗电器件120以及将无源器件组合到本文所述的各种不同调节器结构(例如，不同的电压调节器)中时用于提供滤波或功率调节的无源器件之间同时提供高带宽、低功率存储器连接。
在一些实施例中，调节器结构完全容纳在无源器件100内。在其他实施例中，调节器结构的部分位于耗电器件120上。在某些实施例中，如图10中所示，无源器件100(和存储器器件250)比耗电器件120小。在一些实施例中，无源器件100显著小于耗电器件120。在无源器件100比耗电器件120小时，耗电器件的凸块区域的一部分可用于I/O或其他输电连接。在一些实施例中，如图11中所示，无源器件100(具有存储器器件250)尺寸与耗电器件120基本上相似。
图12示出了具有包含TSV的无源器件100、耗电器件120和存储器器件250的封装件200”的一个实施例的侧视图表示。封装件200”可以包括夹置于构造封装件122和耗电器件120之间的无源器件100和存储器器件250。无源器件100可以包括通路端子，以提供耗电器件120和存储器器件250之间的连接。在一些实施例中，无源器件100与耗电器件120偏移，以允许耗电器件和构造封装件122之间具有直接一般I/O连接。在一些实施例中，构造封装件122可以包括用于耗电器件120和存储器器件250之间连接，而不穿过无源器件100的配线。在一些实施例中，TSV被构造到无源器件100中，或耗电器件120或者两个器件中。在一些实施例中，将存储器器件250和无源器件100的功能组合到单个管芯上。如果存储器器件是包含高密度电容器阵列作为其基本过程一部分的DRAM，这可能尤其有用。管芯功能的其他组合是可能的，并且对于本领域的技术人员而言将是显而易见的。
在一些实施例中，标准封装技术，诸如使用构造材料、交错和面对面连通性，可以与系统要求结合，并由本领域的技术人员用于从系统中的不同器件消除TSV，由此降低成本。
根据本说明书，本发明各个方面的其他修改和替代实施例对于本领域的技术人员而言将是显而易见的。因此，将本说明书理解为仅是例示性的并且目的是用于教导本领域的技术人员执行本发明的一般方式。应当理解，本文所示和所述的本发明形式将被当做目前优选的实施例。元件与材料可被本文所示和所述的那些元件与材料所替代，可反向部件和过程并且可独立地利用本发明的某些特征，在受益于本发明的本说明书之后，所有这些对于本领域的技术人员而言都将是显而易见的。可在不脱离以下权利要求书中所描述的本发明的实质和范围的情况下对本文所述的元件进行更改。

Claims (15)

1.一种半导体器件，包括：
半导体基板；
多个无源元件，所述多个无源元件形成在所述半导体基板上，其中所述无源元件在所述半导体基板上布置成阵列；和
一个或多个端子，所述一个或多个端子用于将所述无源元件耦接到至少一个附加半导体器件。
2.根据权利要求1所述的器件，其中所述无源元件包括电容器。
3.根据权利要求1所述的器件，其中所述阵列中的所述无源元件中的两个或更多个无源元件耦接在一起。
4.根据权利要求1所述的器件，还包括形成在所述半导体基板上的一个或多个开关。
5.根据权利要求1所述的器件，其中所述端子间隔开最小距离，以禁止在所述无源元件之间发生短接。
6.根据权利要求1所述的器件，其中所述端子中的至少一个端子包括硅通孔(TSV)。
7.根据权利要求1所述的器件，还包括形成在所述半导体基板上的存储器器件。
8.一种半导体器件封装件，包括：
第一半导体器件，所述第一半导体器件包括：
第一半导体基板；
一个或多个无源元件，所述一个或多个无源元件形成在所述第一半导体基板上；和
一个或多个端子；和
第二半导体器件，所述第二半导体器件使用所述端子中的一个或多个端子耦接到所述第一半导体器件，所述第二半导体器件包括：
第二半导体基板；和
一个或多个电流消耗元件，所述一个或多个电流消耗元件形成在所述第二半导体基板上。
9.根据权利要求8所述的器件，其中所述无源元件在所述第一半导体基板上布置成阵列。
10.根据权利要求8所述的器件，其中所述第二半导体器件包括片上系统(SOC)器件。
11.根据权利要求8所述的器件，其中所述阵列中的所述无源元件中的两个或更多个无源元件耦接在一起。
12.根据权利要求8所述的器件，还包括形成在所述第二半导体基板上的一个或多个开关。
13.根据权利要求8所述的器件，其中所述第一半导体器件包括位于所述第一半导体基板上的金属配线，并且其中在所述第一半导体器件耦接到所述第二半导体器件时，所述金属配线被用作电力轨。
14.根据权利要求8所述的器件，其中所述第一半导体器件和所述第二半导体器件耦接，使得所述第二半导体器件限定所述无源元件和所述电流消耗元件的一个或多个操作属性。
15.根据权利要求8所述的器件，其中所述第一半导体器件和所述第二半导体器件耦接，使得所述无源元件和所述电流消耗元件被分隔成一个或多个局部化电压调节结构，其中每个局部化电压调节结构包括不同的电压电源调节器。
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