CN105450178A - Mixer circuit capable of correcting IQ mismatch - Google Patents
Mixer circuit capable of correcting IQ mismatch Download PDFInfo
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- CN105450178A CN105450178A CN201511017499.8A CN201511017499A CN105450178A CN 105450178 A CN105450178 A CN 105450178A CN 201511017499 A CN201511017499 A CN 201511017499A CN 105450178 A CN105450178 A CN 105450178A
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- mixer
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
Abstract
The invention discloses a mixer circuit capable of correcting an IQ mismatch. The mixer circuit is characterized by comprising a first-stage mixer circuit on an I signal channel, a second-stage mixer circuit on a Q signal channel, and a biasing circuit providing DC biases for the first-stage mixer circuit and the second-stage mixer circuit. The mixer circuit capable of correcting IQ mismatch provided by the invention has the advantages that on the basis of the conventional mixer, the mixer circuit achieves IQ mismatch correction only by changing the on-off characteristics of mixer switches, so that the structure is simple; no additional correction-stage circuit is included, so that additional power consumption and additional noise are avoided; a part of the original switch width-length ratio of the conventional mixer is removed for adjustment, so that the total width-length ratio of each switch is the same as the switch width-length ratio of the conventional mixer, which avoids additional parasitic capacitance.
Description
Technical field
The present invention is a kind of mixer of recoverable IQ mismatch.Object is based on conventional mixer, realizes the correction to IQ mismatch.
Background technology
The fields such as receiver circuit is widely used in wireless telecommunications, satellite navigation are the core circuits receiving process radiofrequency signal.In receiver, an important circuit is exactly frequency mixer, and its major function is that radiofrequency signal is down-converted to intermediate-freuqncy signal, so as signal to be amplified, the process such as filtering.
In mixer, due to domain do not mate, the reason such as fabrication error, between intermediate frequency I road signal and intermediate frequency Q road signal, there is mismatch to a certain degree.Traditional solution is, after mixer, connect one-level IQ correcting circuit, can solve IQ mismatch problems like this by the IQ correcting circuit corrected below.But extra stage circuit can produce extra power consumption, increase extra noise.
The mixer of a kind of recoverable IQ of the present invention mismatch, on conventional mixer basis, does not introduce additional corrections level circuit, by means of only change mixer switches on state characteristic, realizes the correction to IQ mismatch.Therefore mixer of the present invention has structure simply, does not increase extra power consumption, does not increase the feature of additional noise.
Summary of the invention
The mixer of a kind of recoverable IQ mismatch of the present invention, object is based on conventional mixer circuit, realizes the correction to IQ mismatch.
The mixer of a kind of recoverable IQ mismatch of the present invention is achieved through the following technical solutions: a kind of mixer of recoverable IQ mismatch, and described mixer comprises:
First order mixer in the signalling channel of I road, the second level mixer in the signalling channel of Q road, and provide the biasing circuit of direct current biasing to respectively first order mixer and second level mixer.
Preferably, described first order mixer, radio-frequency input signals high level is V
rFIP, radio-frequency input signals low level is V
rFIN; Local oscillator input signals high level is V
lOIP, local oscillator input signals low level is V
lOIN; Direct current biasing input signal is V
bI; IF output signal high level is V
iFIP, IF output signal low level is V
iFIN;
Described second level mixer, radio-frequency input signals high level is V
rFIP, radio-frequency input signals low level is V
rFIN; Local oscillator input signals high level is V
lOQP, local oscillator input signals low level is V
lOQN; Direct current biasing input signal is V
bQ; IF output signal high level is V
iFQP, IF output signal low level is V
iFQN;
Described first order mixer and second level mixer, the two ends of high level input capacitance CP respectively with radio-frequency input signals high level V
rFIPbe connected with the drain terminal of the first transistor M1, transistor seconds M2, the 5th transistor M5, the 6th transistor M6, the two ends of low level input capacitance CN respectively with radio-frequency input signals low level V
rFINbe connected with the drain terminal of third transistor M3, the 4th transistor M4, the 7th transistor M7, the 8th transistor M8; First order mixer local oscillator input signals high level V
lOIPthe coupling circuit consisted of the first electric capacity C1 and the first resistance R1 is connected with the grid of the first transistor M1, the 4th transistor M4, first order mixer local oscillator input signals low level V
lOINthe coupling circuit consisted of the second electric capacity C2 and the second resistance R2 is connected with the grid of transistor seconds M2, third transistor M3; Second level mixer local oscillator input signals high level V
lOQPthe coupling circuit consisted of the 3rd electric capacity C3 and the 3rd resistance R3 is connected with the grid of the 5th transistor M5, the 8th transistor M8, second level mixer local oscillator input signals low level V
lOQNthe coupling circuit consisted of the 4th electric capacity C4 and the 4th resistance R4 is connected with the grid of the 6th transistor M6, the 7th transistor M7; First order mixer IF output signal high level V
iFIPbe connected with the source of the first transistor M1, third transistor M3, first order mixer IF output signal low level V
iFINbe connected with the source of transistor seconds M2, the 4th transistor M4; Second level mixer IF output signal high level V
iFQPbe connected with the source of the 5th transistor M5, the 7th transistor M7, second level mixer IF output signal low level V
iFQNbe connected with the source of the 6th transistor M6, the 8th transistor M8.
Preferably, the biasing circuit of direct current biasing is provided to be to respectively first order mixer and second level mixer: the reference voltage V that current source IBI and resistance RBI produces
bI<5>, be connected to V respectively by interrupteur SW HI<1-4>
bI<1-4>, be connected to V with reference to ground by interrupteur SW LI<1-4>
bI<1-4>; The reference voltage V that current source IBQ and resistance RBQ produces
bQ<5>, be connected to V respectively by interrupteur SW HQ<1-4>
bQ<1-4>, be connected to V with reference to ground by interrupteur SW LQ<1-4>
bQ<1-4>; DC offset voltage V
bI<1-4>, V
bQ<1-4>at reference voltage V
bI<5>, V
bQ<5>and switch with reference between ground, realize the gating function of switch; By the gating of control IQ double switch, realize the correction of frequency mixer IQ mismatch.
Preferably, wherein resistance R1-R4, electric capacity C1-C4 and transistor M1-M8 form the regulating circuit of array format, and regulate number of bits equal, the regulating circuit of the array format be made up of the first resistance R1, the first electric capacity C1 and the first transistor M1: wherein the drain electrode of the first transistor array M1<1-5> is all connected to input capacitance CP, the source electrode of the first transistor array M1<1-5> is all connected to IF output signal high level V
iFIP; Local oscillator input signals high level V
lOIPbe connected with the grid of the first transistor array M1<1-5> respectively by the first capacitor array C1<1-5>, DC bias signal V
bI<1-5>be connected with the grid of the first transistor array M1<1-5> respectively by the first electric resistance array R1<1-5>.Remaining circuit, on the basis of such scheme, according to above-mentioned arrayed rule, arranges with identical bit and precision.
The invention has the advantages that:
(1) the present invention is on conventional mixer basis, and by means of only change mixer switches on state characteristic, realize the correction to IQ mismatch, therefore mixer of the present invention has the simple advantage of structure;
(2) the present invention is not containing extra adjusting level circuit, therefore has and do not increase extra power consumption, do not increase the advantage of additional noise;
(3) the present invention is under the original switch breadth length ratio of conventional mixer, and take out a part of breadth length ratio with making adjustments, therefore for each switch, its total breadth length ratio is the same with conventional mixer switch breadth length ratio, does not produce extra parasitic capacitance.
Accompanying drawing explanation
Fig. 1 is the mixer figure of the technical program;
Fig. 2 is the correction array circuit figure in the technical program frequency mixer;
Fig. 3 is the DC bias circuit figure of the technical program;
Embodiment
The technical program is further illustrated as follows below in conjunction with accompanying drawing and embodiment:
Described frequency mixer comprises the first order mixer in the signalling channel of I road, the second level mixer in the signalling channel of Q road, and provides the biasing circuit of direct current biasing to respectively first order mixer and second level mixer.
Described first order mixer, radio-frequency input signals high level is V
rFIP, radio-frequency input signals low level is V
rFIN; Local oscillator input signals high level is V
lOIP, local oscillator input signals low level is V
lOIN; Direct current biasing input signal is V
bI; IF output signal high level is V
iFIP, IF output signal low level is V
iFIN;
Described second level mixer, radio-frequency input signals high level is V
rFIP, radio-frequency input signals low level is V
rFIN; Local oscillator input signals high level is V
lOQP, local oscillator input signals low level is V
lOQN; Direct current biasing input signal is V
bQ; IF output signal high level is V
iFQP, IF output signal low level is V
iFQN;
Described first order mixer and second level mixer, the two ends of high level input capacitance CP respectively with radio-frequency input signals high level V
rFIPbe connected with the drain terminal of the first transistor M1, transistor seconds M2, the 5th transistor M5, the 6th transistor M6, the two ends of low level input capacitance CN respectively with radio-frequency input signals low level V
rFINbe connected with the drain terminal of third transistor M3, the 4th transistor M4, the 7th transistor M7, the 8th transistor M8; First order mixer local oscillator input signals high level V
lOIPthe coupling circuit consisted of the first electric capacity C1 and the first resistance R1 is connected with the grid of the first transistor M1, the 4th transistor M4, first order mixer local oscillator input signals low level V
lOINthe coupling circuit consisted of the second electric capacity C2 and the second resistance R2 is connected with the grid of transistor seconds M2, third transistor M3; Second level mixer local oscillator input signals high level V
lOQPthe coupling circuit consisted of the 3rd electric capacity C3 and the 3rd resistance R3 is connected with the grid of the 5th transistor M5, the 8th transistor M8, second level mixer local oscillator input signals low level V
lOQNthe coupling circuit consisted of the 4th electric capacity C4 and the 4th resistance R4 is connected with the grid of the 6th transistor M6, the 7th transistor M7; First order mixer IF output signal high level V
iFIPbe connected with the source of the first transistor M1, third transistor M3, first order mixer IF output signal low level V
iFINbe connected with the source of transistor seconds M2, the 4th transistor M4; Second level mixer IF output signal high level V
iFQPbe connected with the source of the 5th transistor M5, the 7th transistor M7, second level mixer IF output signal low level V
iFQNbe connected with the source of the 6th transistor M6, the 8th transistor M8.
Wherein resistance R1-R4, electric capacity C1-C4 and transistor M1-M8 form the regulating circuit of array format, and regulate number of bits equal, the regulating circuit of the array format be made up of the first resistance R1, the first electric capacity C1 and the first transistor M1 in Fig. 1 as shown in Figure 2, wherein the drain electrode of the first transistor array M1<1-5> is all connected to input capacitance CP, and the source electrode of the first transistor array M1<1-5> is all connected to IF output signal high level V
iFIP; Local oscillator input signals high level V
lOIPbe connected with the grid of the first transistor array M1<1-5> respectively by the first capacitor array C1<1-5>, DC bias signal V
bI<1-5>be connected with the grid of transistor array M1<1-5> respectively by the first electric resistance array R1<1-5>.
Circuit shown in Fig. 2 is only the part in integrated circuit shown in Fig. 1, and remaining circuit, on the basis of connection scheme shown in Fig. 1, according to the arrayed rule shown in Fig. 2, arranges with identical bit and precision.
There is provided the biasing circuit of direct current biasing as shown in Figure 3, the reference voltage V that current source IBI and resistance RBI produces to respectively first order mixer and second level mixer
bI<5>, be connected to V respectively by interrupteur SW HI<1-4>
bI<1-4>, be connected to V with reference to ground by interrupteur SW LI<1-4>
bI<1-4>.The reference voltage V that current source IBQ and resistance RBQ produces
bQ<5>, be connected to V respectively by interrupteur SW HQ<1-4>
bQ<1-4>, be connected to V with reference to ground by interrupteur SW LQ<1-4>
bQ<1-4>.
By controlling DC offset voltage V
bI<1-4>, V
bQ<1-4>at reference voltage V
bI<5>, V
bQ<5>and switch with reference between ground, realize the gating function of switch; By the gating of control IQ double switch, realize the correction of frequency mixer IQ mismatch.
When IQ two-way is without mismatch, circuit is without the need to tuber function, and default standard state is V
bI<1-4>=V
bI<5>, V
bQ<1-4>=V
bQ<5>; Now in array, all switches all normally work, and the total switch breadth length ratio of array is 47*W/L, so M1-M8 breadth length ratio is 47*W/L; When IQ two-way loses timing, according to size and the positive-negative relationship of IQ two-way mismatch, optionally by V
bI<1-4>in one or more ground connection or by V
bQ<1-4>in one or more ground connection, namely compensate IQ mismatch by reducing the breadth length ratio of M1-M4 or M5-M8.
Claims (3)
1. a mixer for recoverable IQ mismatch, is characterized in that described mixer comprises:
First order mixer in the signalling channel of I road, the second level mixer in the signalling channel of Q road, and provide the biasing circuit of direct current biasing to respectively first order mixer and second level mixer.
2. the mixer of recoverable IQ mismatch as claimed in claim 1, is characterized in that
Described first order mixer, radio-frequency input signals high level is V
rFIP, radio-frequency input signals low level is V
rFIN; Local oscillator input signals high level is V
lOIP, local oscillator input signals low level is V
lOIN; Direct current biasing input signal is V
bI; IF output signal high level is V
iFIP, IF output signal low level is V
iFIN;
Described second level mixer, radio-frequency input signals high level is V
rFIP, radio-frequency input signals low level is V
rFIN; Local oscillator input signals high level is V
lOQP, local oscillator input signals low level is V
lOQN; Direct current biasing input signal is V
bQ; IF output signal high level is V
iFQP, IF output signal low level is V
iFQN;
Described first order mixer and second level mixer, the two ends of high level input capacitance CP respectively with radio-frequency input signals high level V
rFIPbe connected with the drain terminal of the first transistor M1, transistor seconds M2, the 5th transistor M5, the 6th transistor M6, the two ends of low level input capacitance CN respectively with radio-frequency input signals low level V
rFINbe connected with the drain terminal of third transistor M3, the 4th transistor M4, the 7th transistor M7, the 8th transistor M8; First order mixer local oscillator input signals high level V
lOIPthe coupling circuit consisted of the first electric capacity C1 and the first resistance R1 is connected with the grid of the first transistor M1, the 4th transistor M4, first order mixer local oscillator input signals low level V
lOINthe coupling circuit consisted of the second electric capacity C2 and the second resistance R2 is connected with the grid of transistor seconds M2, third transistor M3; Second level mixer local oscillator input signals high level V
lOQPthe coupling circuit consisted of the 3rd electric capacity C3 and the 3rd resistance R3 is connected with the grid of the 5th transistor M5, the 8th transistor M8, second level mixer local oscillator input signals low level V
lOQNthe coupling circuit consisted of the 4th electric capacity C4 and the 4th resistance R4 is connected with the grid of the 6th transistor M6, the 7th transistor M7; First order mixer IF output signal high level V
iFIPbe connected with the source of the first transistor M1, third transistor M3, first order mixer IF output signal low level V
iFINbe connected with the source of transistor seconds M2, the 4th transistor M4; Second level mixer IF output signal high level V
iFQPbe connected with the source of the 5th transistor M5, the 7th transistor M7, second level mixer IF output signal low level V
iFQNbe connected with the source of the 6th transistor M6, the 8th transistor M8.
3. the mixer of recoverable IQ mismatch as claimed in claim 2, is characterized in that providing the biasing circuit of direct current biasing to be to first order mixer and second level mixer respectively: the reference voltage V that current source IBI and resistance RBI produces
bI<5>, be connected to V respectively by interrupteur SW HI<1-4>
bI<1-4>, be connected to V with reference to ground by interrupteur SW LI<1-4>
bI<1-4>; The reference voltage V that current source IBQ and resistance RBQ produces
bQ<5>, be connected to V respectively by interrupteur SW HQ<1-4>
bQ<1-4>, be connected to V with reference to ground by interrupteur SW LQ<1-4>
bQ<1-4>; DC offset voltage V
bI<1-4>, V
bQ<1-4>at reference voltage V
bI<5>, V
bQ<5>and switch with reference between ground, realize the gating function of switch; By the gating of control IQ double switch, realize the correction of frequency mixer IQ mismatch.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511017499.8A CN105450178B (en) | 2015-12-29 | 2015-12-29 | A kind of mixer of recoverable IQ mismatches |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511017499.8A CN105450178B (en) | 2015-12-29 | 2015-12-29 | A kind of mixer of recoverable IQ mismatches |
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| CN105450178A true CN105450178A (en) | 2016-03-30 |
| CN105450178B CN105450178B (en) | 2018-05-25 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106253854A (en) * | 2016-08-03 | 2016-12-21 | 电子科技大学 | A kind of mixer with local oscillator phase mismatch compensation function |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103516371A (en) * | 2013-09-18 | 2014-01-15 | 清华大学 | Configurable wireless transmitter |
| US20140162580A1 (en) * | 2012-12-10 | 2014-06-12 | Qualcomm Incorporated | Reconfigurable receiver circuits for test signal generation |
| CN103916343A (en) * | 2012-12-28 | 2014-07-09 | 北京中电华大电子设计有限责任公司 | I/Q unbalance correction method and device used for wireless local area network device |
| CN205283496U (en) * | 2015-12-29 | 2016-06-01 | 江苏星宇芯联电子科技有限公司 | First detector circuit of recoverable IQ mismatch |
-
2015
- 2015-12-29 CN CN201511017499.8A patent/CN105450178B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140162580A1 (en) * | 2012-12-10 | 2014-06-12 | Qualcomm Incorporated | Reconfigurable receiver circuits for test signal generation |
| CN103916343A (en) * | 2012-12-28 | 2014-07-09 | 北京中电华大电子设计有限责任公司 | I/Q unbalance correction method and device used for wireless local area network device |
| CN103516371A (en) * | 2013-09-18 | 2014-01-15 | 清华大学 | Configurable wireless transmitter |
| CN205283496U (en) * | 2015-12-29 | 2016-06-01 | 江苏星宇芯联电子科技有限公司 | First detector circuit of recoverable IQ mismatch |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106253854A (en) * | 2016-08-03 | 2016-12-21 | 电子科技大学 | A kind of mixer with local oscillator phase mismatch compensation function |
| CN106253854B (en) * | 2016-08-03 | 2018-10-23 | 电子科技大学 | A kind of mixer with local oscillator phase mismatch compensation function |
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| CN105450178B (en) | 2018-05-25 |
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