CN105450178B - A kind of mixer of recoverable IQ mismatches - Google Patents
A kind of mixer of recoverable IQ mismatches Download PDFInfo
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- CN105450178B CN105450178B CN201511017499.8A CN201511017499A CN105450178B CN 105450178 B CN105450178 B CN 105450178B CN 201511017499 A CN201511017499 A CN 201511017499A CN 105450178 B CN105450178 B CN 105450178B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
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Abstract
The invention discloses a kind of mixers of recoverable IQ mismatches, it is characterised in that the mixer includes：First order mixer in the signal path of I roads, second level mixer in the signal path of Q roads and the biasing circuit that direct current biasing is provided respectively to first order mixer with second level mixer.The present invention is on the basis of conventional mixer, only by changing mixer switches on state characteristic, realizes the correction to IQ mismatches, thus the mixer of the present invention have the advantages that it is simple in structure；The present invention has the advantages of not increasing extra power consumption, not increasing additional noise without additional adjusting level circuit；The present invention is under the original switch breadth length ratio of conventional mixer, takes out a part of breadth length ratio with making adjustments, therefore for each switch, and total breadth length ratio does not generate additional parasitic capacitance as with conventional mixer switching breadth length ratio.
Description
Technical field
The present invention is a kind of mixer of recoverable IQ mismatches.Purpose is based on conventional mixer, realizes and IQ is lost
The correction matched somebody with somebody.
Background technology
Receiver circuit is widely used in the fields such as wireless telecommunications, satellite navigation, is the core for receiving processing radiofrequency signal
Circuit.An important circuit is exactly frequency mixer in receiver, and major function is that radiofrequency signal is down-converted to intermediate-freuqncy signal,
The processing such as to be amplified, filter to signal.
In mixer, due to domain mismatch, fabrication error etc., intermediate frequency I road signals and intermediate frequency Q roads signal
Between, there are a degree of mismatches.Traditional solution is that level-one IQ correcting circuits are connect behind mixer, this
Sample can solve IQ mismatch problems by the IQ correcting circuits corrected below.But additional stage circuit can generate additional work(
Consumption, increases additional noise.
A kind of mixer of recoverable IQ mismatches of the present invention, on the basis of conventional mixer, does not introduce additional corrections
Grade circuit, only by changing mixer switches on state characteristic, realizes the correction to IQ mismatches.Therefore the mixer of the present invention
With simple in structure, the characteristics of not increasing extra power consumption, not increasing additional noise.
The content of the invention
The mixer of a kind of recoverable IQ mismatches of the present invention, it is therefore an objective to based on conventional mixer circuit, realization pair
The correction of IQ mismatches.
A kind of mixer of recoverable IQ mismatches of the present invention is achieved through the following technical solutions：One kind can
The mixer of IQ mismatches is corrected, the mixer includes：
First order mixer in the signal path of I roads, second level mixer in the signal path of Q roads and
The biasing circuit of direct current biasing is provided respectively to first order mixer with second level mixer.
Preferably, the first order mixer, radio-frequency input signals high level are VRFIP, the low electricity of radio-frequency input signals
It puts down as VRFIN；Local oscillator input signals high level is VLOIP, local oscillator input signals low level is VLOIN；Direct current biasing input signal is
VBI；IF output signal high level is VIFIP, IF output signal low level is VIFIN；
The second level mixer, radio-frequency input signals high level are VRFIP, radio-frequency input signals low level is
VRFIN；Local oscillator input signals high level is VLOQP, local oscillator input signals low level is VLOQN；Direct current biasing input signal is VBQ；In
Frequency output signal high level is VIFQP, IF output signal low level is VIFQN；
The first order mixer and second level mixer, the both ends of high level input capacitance CP respectively with
Radio-frequency input signals high level VRFIPWith the first transistor M1, second transistor M2, the 5th transistor M5, the 6th transistor M6
Drain terminal is connected, the both ends of low level input capacitance CN respectively with radio-frequency input signals low level VRFINWith third transistor M3,
Four transistor M4, the 7th transistor M7, the drain terminal of the 8th transistor M8 are connected；First order mixer local oscillator input signals are high
Level VLOIPPass through the termination power that the first capacitance C1 and first resistor R1 are formed and the first transistor M1, the 4th transistor M4
Grid is connected, first order mixer local oscillator input signals low level VLOINIt is made up of the second capacitance C2 and second resistance R2
Termination power be connected with the grid of second transistor M2, third transistor M3；Second level mixer local oscillator input signals
High level VLOQPPass through the termination power that the 3rd capacitance C3 and 3rd resistor R3 is formed and the 5th transistor M5, the 8th transistor M8
Grid be connected, second level mixer local oscillator input signals low level VLOQNPass through the 4th capacitance C4 and the 4th resistance R4 groups
Into termination power be connected with the grid of the 6th transistor M6, the 7th transistor M7；First order mixer intermediate frequency output letter
Number high level VIFIPIt is connected with the source of the first transistor M1, third transistor M3, first order mixer intermediate frequency output letter
Number low level VIFINIt is connected with the source of second transistor M2, the 4th transistor M4；Second level mixer intermediate frequency output letter
Number high level VIFQPIt is connected with the source of the 5th transistor M5, the 7th transistor M7, second level mixer intermediate frequency output letter
Number low level VIFQNIt is connected with the source of the 6th transistor M6, the 8th transistor M8.
Preferably, the biasing circuit of direct current biasing is provided to first order mixer and second level mixer respectively
For：The reference voltage V that current source IBI and resistance RBI is generatedBI<5>, respectively by switching SWHI<1-4>It is connected to VBI<1-4>, ginseng
Examine by switching SWLI<1-4>It is connected to VBI<1-4>；The reference voltage V that current source IBQ and resistance RBQ is generatedBQ<5>, lead to respectively
Cross switch SWHQ<1-4>It is connected to VBQ<1-4>, reference ground is by switching SWLQ<1-4>It is connected to VBQ<1-4>；DC offset voltage
VBI<1-4>、VBQ<1-4>In reference voltage VBI<5>、VBQ<5>Switch between reference ground, realize the gating function of switch；Pass through control
The gating of IQ double switches realizes the correction of frequency mixer IQ mismatches.
Preferably, the adjusting circuit of wherein resistance R1-R4, capacitance C1-C4 and transistor M1-M8 composition array formats,
And adjusting number of bits is equal, by the adjusting of first resistor R1, the first capacitance C1 and the first transistor the M1 array format formed
Circuit：Wherein the first transistor array M1<1-5>Drain electrode be connected to input capacitance CP, the first transistor array M1<1-5>
Source electrode be connected to IF output signal high level VIFIP；Local oscillator input signals high level VLOIPPass through the first capacitance battle array respectively
Arrange C1<1-5>With the first transistor array M1<1-5>Grid connection, DC bias signal VBI<1-5>Pass through first resistor respectively
Array R1<1-5>With the first transistor array M1<1-5>Grid connection.Remaining circuit on the basis of said program, according to
Above-mentioned array queueing discipline is arranged with identical bit and precision.
The advantage of the invention is that：
(1) present invention, only by changing mixer switches on state characteristic, is realized to IQ mismatches on the basis of conventional mixer
Correction, therefore the present invention mixer have the advantages that it is simple in structure；
(2) present invention does not increase additional noise without additional adjusting level circuit, therefore with extra power consumption is not increased
Advantage；
(3) present invention is under the original switch breadth length ratio of conventional mixer, takes out a part of breadth length ratio with making adjustments, therefore
For each switch, total breadth length ratio does not generate additional parasitic capacitance as conventional mixer switch breadth length ratio.
Description of the drawings
Fig. 1 is the mixer figure of the technical program；
Fig. 2 is the correction array circuit figure in the technical program frequency mixer；
Fig. 3 is the DC bias circuit figure of the technical program；
Specific embodiment
The technical program is further described below with specific embodiment below in conjunction with the accompanying drawings：
The frequency mixer includes the first order mixer in the signal path of I roads, and the second level in the signal path of Q roads is mixed
Frequency device circuit and the biasing circuit that direct current biasing is provided respectively to first order mixer with second level mixer.
The first order mixer, radio-frequency input signals high level are VRFIP, radio-frequency input signals low level is
VRFIN；Local oscillator input signals high level is VLOIP, local oscillator input signals low level is VLOIN；Direct current biasing input signal is VBI；In
Frequency output signal high level is VIFIP, IF output signal low level is VIFIN；
The second level mixer, radio-frequency input signals high level are VRFIP, radio-frequency input signals low level is
VRFIN；Local oscillator input signals high level is VLOQP, local oscillator input signals low level is VLOQN；Direct current biasing input signal is VBQ；In
Frequency output signal high level is VIFQP, IF output signal low level is VIFQN；
The first order mixer and second level mixer, the both ends of high level input capacitance CP respectively with
Radio-frequency input signals high level VRFIPWith the first transistor M1, second transistor M2, the 5th transistor M5, the 6th transistor M6
Drain terminal is connected, the both ends of low level input capacitance CN respectively with radio-frequency input signals low level VRFINWith third transistor M3,
Four transistor M4, the 7th transistor M7, the drain terminal of the 8th transistor M8 are connected；First order mixer local oscillator input signals are high
Level VLOIPPass through the termination power that the first capacitance C1 and first resistor R1 are formed and the first transistor M1, the 4th transistor M4
Grid is connected, first order mixer local oscillator input signals low level VLOINIt is made up of the second capacitance C2 and second resistance R2
Termination power be connected with the grid of second transistor M2, third transistor M3；Second level mixer local oscillator input signals
High level VLOQPPass through the termination power that the 3rd capacitance C3 and 3rd resistor R3 is formed and the 5th transistor M5, the 8th transistor M8
Grid be connected, second level mixer local oscillator input signals low level VLOQNPass through the 4th capacitance C4 and the 4th resistance R4 groups
Into termination power be connected with the grid of the 6th transistor M6, the 7th transistor M7；First order mixer intermediate frequency output letter
Number high level VIFIPIt is connected with the source of the first transistor M1, third transistor M3, first order mixer intermediate frequency output letter
Number low level VIFINIt is connected with the source of second transistor M2, the 4th transistor M4；Second level mixer intermediate frequency output letter
Number high level VIFQPIt is connected with the source of the 5th transistor M5, the 7th transistor M7, second level mixer intermediate frequency output letter
Number low level VIFQNIt is connected with the source of the 6th transistor M6, the 8th transistor M8.
The adjusting circuit of wherein resistance R1-R4, capacitance C1-C4 and transistor M1-M8 composition array formats, and adjust ratio
Special digit is equal, by the adjusting circuit of first resistor R1, the first capacitance C1 and the first transistor the M1 array format formed in Fig. 1
As shown in Fig. 2, wherein the first transistor array M1<1-5>Drain electrode be connected to input capacitance CP, the first transistor array M1<
1-5>Source electrode be connected to IF output signal high level VIFIP；Local oscillator input signals high level VLOIPPass through the first electricity respectively
Hold array C1<1-5>With the first transistor array M1<1-5>Grid connection, DC bias signal VBI<1-5>Pass through first respectively
Electric resistance array R1<1-5>With transistor array M1<1-5>Grid connection.
Circuit shown in Fig. 2 is only the part in integrated circuit shown in Fig. 1, remaining circuit connection scheme shown in Fig. 1
On the basis of, according to array queueing discipline shown in Fig. 2, arranged with identical bit and precision.
Biasing circuit such as Fig. 3 institutes of direct current biasing are provided respectively to first order mixer with second level mixer
Show, the reference voltage V that current source IBI and resistance RBI is generatedBI<5>, respectively by switching SWHI<1-4>It is connected to VBI<1-4>, ginseng
Examine by switching SWLI<1-4>It is connected to VBI<1-4>.The reference voltage V that current source IBQ and resistance RBQ is generatedBQ<5>, lead to respectively
Cross switch SWHQ<1-4>It is connected to VBQ<1-4>, reference ground is by switching SWLQ<1-4>It is connected to VBQ<1-4>。
By controlling DC offset voltage VBI<1-4>、VBQ<1-4>In reference voltage VBI<5>、VBQ<5>Switch between reference ground,
Realize the gating function of switch；By controlling the gating of IQ double switches, the correction of frequency mixer IQ mismatches is realized.
When IQ two-way is without mismatch, for circuit without tuber function, default standard state is VBI<1-4>=VBI<5>, VBQ<1-4>=
VBQ<5>；All switches all work normally in array at this time, and the total switch breadth length ratio of array is 47*W/L, so M1-M8 breadth length ratios
It is 47*W/L；It is selective by V according to the size and positive-negative relationship of IQ two-way mismatches when IQ two-way loses timingBI<1-4>
In one or more ground connection or by VBQ<1-4>In one or more ground connection, i.e. the width by reducing M1-M4 or M5-M8
Ratio is grown to compensate IQ mismatches.
Claims (1)
1. a kind of mixer of recoverable IQ mismatches, it is characterised in that the mixer includes：
First order mixer in the signal path of I roads, second level mixer in the signal path of Q roads and respectively
The biasing circuit of direct current biasing is provided to first order mixer and second level mixer；
The first order mixer, radio-frequency input signals high level are VRFIP, radio-frequency input signals low level is VRFIN；This
Input signal of shaking high level is VLOIP, local oscillator input signals low level is VLOIN；Direct current biasing input signal is VBI；Intermediate frequency exports
Signal high level is VIFIP, IF output signal low level is VIFIN；
The second level mixer, radio-frequency input signals high level are VRFIP, radio-frequency input signals low level is VRFIN；This
Input signal of shaking high level is VLOQP, local oscillator input signals low level is VLOQN；Direct current biasing input signal is VBQ；Intermediate frequency exports
Signal high level is VIFQP, IF output signal low level is VIFQN；
The first order mixer and second level mixer, the both ends of high level input capacitance CP respectively with radio frequency
Input signal high level VRFIPWith the first transistor M1, second transistor M2, the 5th transistor M5, the 6th transistor M6 drain terminal
Be connected, the both ends of low level input capacitance CN respectively with radio-frequency input signals low level VRFINWith third transistor M3, the 4th crystalline substance
Body pipe M4, the 7th transistor M7, the drain terminal of the 8th transistor M8 are connected；First order mixer local oscillator input signals high level
VLOIPPass through the termination power that the first capacitance C1 and first resistor R1 is formed and the first transistor M1, the grid of the 4th transistor M4
It is connected, first order mixer local oscillator input signals low level VLOINThe coupling being made up of the second capacitance C2 and second resistance R2
Circuit is closed with the grid of second transistor M2, third transistor M3 to be connected；The high electricity of second level mixer local oscillator input signals
Flat VLOQPPass through the termination power that the 3rd capacitance C3 and 3rd resistor R3 is formed and the 5th transistor M5, the grid of the 8th transistor M8
Extremely it is connected, second level mixer local oscillator input signals low level VLOQNIt is made up of the 4th capacitance C4 and the 4th resistance R4
Termination power is connected with the grid of the 6th transistor M6, the 7th transistor M7；First order mixer IF output signal is high
Level VIFIPIt is connected with the source of the first transistor M1, third transistor M3, first order mixer IF output signal is low
Level VIFINIt is connected with the source of second transistor M2, the 4th transistor M4；Second level mixer IF output signal is high
Level VIFQPIt is connected with the source of the 5th transistor M5, the 7th transistor M7, second level mixer IF output signal is low
Level VIFQNIt is connected with the source of the 6th transistor M6, the 8th transistor M8；The first order mixer is mixed with the second level
Frequency device circuit provide direct current biasing biasing circuit be：The reference voltage VBI that current source IBI and resistance RBI is generated<5>, respectively
By switching SWHI<1-4>It is connected to VBI<1-4>, reference ground is by switching SWLI<1-4>It is connected to VBI<1-4>；Current source
The reference voltage VBQ that IBQ and resistance RBQ is generated<5>, respectively by switching SWHQ<1-4>It is connected to VBQ<1-4>, reference ground leads to
Cross switch SWLQ<1-4>It is connected to VBQ<1-4>；DC offset voltage VBI<1-4>、VBQ<1-4>In reference voltage VBI<5>、
VBQ<5>Switch between reference ground, realize the gating function of switch；Eventually by frequency mixer I road transistor arrays and frequency mixer
The differentiation conducting of Q roads transistor array, to realize the correction on frequency mixer I roads and Q roads mismatch.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201511017499.8A CN105450178B (en) | 2015-12-29 | 2015-12-29 | A kind of mixer of recoverable IQ mismatches |
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| CN201511017499.8A CN105450178B (en) | 2015-12-29 | 2015-12-29 | A kind of mixer of recoverable IQ mismatches |
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| CN105450178B true CN105450178B (en) | 2018-05-25 |
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| CN106253854B (en) * | 2016-08-03 | 2018-10-23 | 电子科技大学 | A kind of mixer with local oscillator phase mismatch compensation function |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103516371A (en) * | 2013-09-18 | 2014-01-15 | 清华大学 | Configurable wireless transmitter |
| CN103916343A (en) * | 2012-12-28 | 2014-07-09 | 北京中电华大电子设计有限责任公司 | I/Q unbalance correction method and device used for wireless local area network device |
| CN205283496U (en) * | 2015-12-29 | 2016-06-01 | 江苏星宇芯联电子科技有限公司 | First detector circuit of recoverable IQ mismatch |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8774745B2 (en) * | 2012-12-10 | 2014-07-08 | Qualcomm Incorporated | Reconfigurable receiver circuits for test signal generation |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103916343A (en) * | 2012-12-28 | 2014-07-09 | 北京中电华大电子设计有限责任公司 | I/Q unbalance correction method and device used for wireless local area network device |
| CN103516371A (en) * | 2013-09-18 | 2014-01-15 | 清华大学 | Configurable wireless transmitter |
| CN205283496U (en) * | 2015-12-29 | 2016-06-01 | 江苏星宇芯联电子科技有限公司 | First detector circuit of recoverable IQ mismatch |
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