CN105449004B - 一种AlGaAs梁式引线PIN二极管及其制备方法 - Google Patents
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- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 title claims abstract description 10
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 18
- 230000000873 masking effect Effects 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 239000011148 porous material Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 229910018885 Pt—Au Inorganic materials 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 238000007669 thermal treatment Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 239000002131 composite material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
Abstract
本发明是一种AlGaAs梁式引线PIN二极管及其制备方法,其特征在于,它是采用P+‑Al0.3Ga0.7As/I‑GaAs/N+‑GaAs异质结PIN结构制作的GaAs基梁式引线PIN二极管。本发明的有益效果是,1)采用P+‑Al0.3Ga0.7As/I‑GaAs/N+‑GaAs异质结PIN结构代替传统的P+‑GaAs/I‑GaAs/N+‑GaAs的GaAs同质结PIN结构,利用异质结的高载流子注入比,有效降低器件的串联电阻。2)采用空气桥工艺,降低器件附加电容。3)器件结构采用梁式引线结构,无管壳封装,使用方便,微波性能优异。制作方法对器件获得的良好效果有:微波测试结果表明,采用P+‑Al0.3Ga0.7As/I‑GaAs/N+‑GaAs异质结PIN结构比相同设计参数的常规器件,串联电阻小10%~20%。
Description
技术领域
本发明是涉及的是一种AlGaAs梁式引线PIN二极管及其制备方法,属于半导体微电子设计制造技术领域。
背景技术
微波PIN二极管是微波系统中极为重要的控制器件,广泛应用于各类微波控制电路中,如微波开关、电调衰减器、移相器、限幅器等。
制作微波PIN二极管的材料主要有Si和GaAs,GaAs PIN二极管相较Si PIN二极管,由于电子迁移率高,开关速度更快,可工作于更高的工作频率下。但其RC乘积已近极限,在高频应用中,尤其是3mm频段应用中,损耗偏大,应用受限。
发明内容
本发明提出的是一种AlGaAs梁式引线PIN二极管及其制备方法,利用P+-AlGaAs/I-GaAs异质结较高的载流子注入比,相比GaAs同质结PIN二极管,在相同物理尺寸下(即电容相同),实现更小的串联电阻,从而其RC乘积更小,可应用于更高的工作频率下。
本发明的技术解决技术方案:采用P+-Al0.3Ga0.7As/I-GaAs/N+-GaAs异质结PIN结构代替传统的P+-GaAs/I-GaAs/N+-GaAs的GaAs同质结PIN结构,利用异质结的高载流子注入比,有效降低器件的串联电阻;采用空气桥工艺,降低器件附加电容;器件结构采用梁式引线结构。
本发明的有益效果:器件参数设计与原常规的参数设计完全兼容,并且不增加额外工艺流程情况下实现器件更小的串联电阻。制作工艺方法对器件获得的良好效果:微波测试结果表明,采用P+-Al0.3Ga0.7As/I-GaAs/N+-GaAs异质结PIN结构比相同设计参数的常规器件,串联电阻小10%~20%。
附图说明
附图1是AlGaAs梁式引线PIN二极管的结构示意图。
附图2是P+-Al0.3Ga0.7As/I-GaAs/N+-GaAs/SI-GaAs的结构示意图。
附图3是小台形成的结构示意图。
附图4是大台形成的结构示意图。
附图5是淀积复合介质膜钝化保护结构示意图。
附图6是N+区欧姆电极形成示意图。
附图7是P+区欧姆电极形成示意图。
附图8是电镀Au形成阴极和阳极空气桥示意图。
附图9是电镀形成金梁示意图。
附图10是GaAs背孔工艺,干法刻蚀图形外GaAs和介质的示意图。
图中的1是Si-GaAs衬底,2是N+-GaAs,3是I-GaAs,4是P+-Al0.3Ga0.7As,5是SiO2/Si3N4复合介质膜,6是空气桥,7是金梁。
具体实施方式
如附图所示,AlGaAs梁式引线PIN二极管,其结构在于,材料结构采用P+-Al0.3Ga0.7As/I-GaAs/N+-GaAs结构,器件结构采用梁式引线结构,并采用空气桥工艺降低器件附加电容。
AlGaAs梁式引线PIN二极管的制备方法,包括如下工艺步骤:
1)选择P+-Al0.3Ga0.7As/I-GaAs/N+-GaAs/SI-GaAs外延材料 (图2),其中P+-Al0.3Ga0.7As掺杂杂质为Be,掺杂浓度≥5E19cm-3,厚度为(0.5±0.1)μm;I-GaAs掺杂杂质为Si,掺杂浓度≤5E14cm-3,厚度为(4.0±0.1)μm;N+-GaAs参杂杂质为Si,掺杂浓度≥5E18cm-3,厚度为(2.0±0.1)μm;SI-GaAs衬底电阻率≥1E7Ω·cm,晶向<100>(图2);
2)光刻掩蔽进行ICP刻蚀,刻蚀深度(5.0±0.2)μm,形成小台(图3);
3)光刻掩蔽进行湿法腐蚀,刻蚀深度(2.5±0.2)μm,形成大台(图4);
4)用PECVD工艺在晶圆表面淀积(10000±500)Å SiO2,(2000±100)Å Si3N4,形成复合介质钝化层(图5);
5)光刻掩蔽,刻蚀形成N+区欧姆接触孔,蒸发欧姆接触金属AuGeNi-Au,其中AuGeNi厚度为(1000±100)Å,Au厚度为(2000±200)Å,剥离形成N+区欧姆接触电极(图6);
6)光刻掩蔽,刻蚀形成P+区欧姆接触孔,溅射欧姆接触金属Ti-Pt-Au,其中Ti厚度为(1000±100)Å,Pt厚度为(1500±150)Å,Au厚度为(1000±100)Å,剥离形成P+区欧姆接触电极(图7);
7)光刻掩蔽,采用电镀Au工艺形成阳极和阴极空气桥(图8);
8)快速热处理,使P+区和N+区形成欧姆接触;
9)用PECVD工艺在晶圆表面淀积(1000±100)Å Si3N4,保护晶片表面和空气桥部分,光刻掩蔽刻蚀形成金梁窗口;
10)溅射TiAuTi,进行光刻掩蔽,电镀形成金梁,并湿法去除金梁外金属(图9);
11)减薄晶片,将晶片机械减薄至(100±10)μm;
12)采用双面对准光刻工艺进行背面光刻胶掩蔽,进行GaAs背孔工艺,干法刻蚀图形外GaAs和复合介质层;
13)分离管芯(图10)。
Claims (1)
1.AlGaAs梁式引线PIN二极管的制备方法,其特征是包括如下工艺步骤:
1)选择P+-Al0.3Ga0.7As/I-GaAs/N+-GaAs/SI-GaAs外延材料,其中P+-Al0.3Ga0.7As掺杂杂质为Be,掺杂浓度≥5E19cm-3,厚度为(0.5±0.1)μm;I-GaAs掺杂杂质为Si,掺杂浓度≤5E14cm-3,厚度为(4.0±0.1)μm;N+-GaAs参杂杂质为Si,掺杂浓度≥5E18cm-3,厚度为(2.0±0.1)μm;SI-GaAs衬底电阻率≥1E7Ω·cm,晶向<100>;
2)光刻掩蔽进行ICP刻蚀,刻蚀深度(5.0±0.2)μm,形成小台;
3)光刻掩蔽进行湿法腐蚀,刻蚀深度(2.5±0.2)μm,形成大台;
4)用PECVD工艺在晶圆表面淀积(10000±500)Å SiO2,(2000±100)Å Si3N4,形成复合介质钝化层;
5)光刻掩蔽,刻蚀形成N+区欧姆接触孔,蒸发欧姆接触金属AuGeNi-Au,其中AuGeNi厚度为(1000±100)Å,Au厚度为(2000±200)Å,剥离形成N+区欧姆接触电极;
6)光刻掩蔽,刻蚀形成P+区欧姆接触孔,溅射欧姆接触金属Ti-Pt-Au,其中Ti厚度为(1000±100)Å,Pt厚度为(1500±150)Å,Au厚度为(1000±100)Å,剥离形成P+区欧姆接触电极;
7)光刻掩蔽,采用电镀Au工艺形成阳极和阴极空气桥;
8)快速热处理,使P+区和N+区形成欧姆接触;
9)用PECVD工艺在晶圆表面淀积(1000±100)Å Si3N4,保护晶片表面和空气桥部分,光刻掩蔽刻蚀形成金梁窗口;
10)溅射TiAuTi,进行光刻掩蔽,电镀形成金梁,并湿法去除金梁外金属;
11)减薄晶片,将晶片机械减薄至(100±10)μm;
12)采用双面对准光刻工艺进行背面光刻胶掩蔽,进行GaAs背孔工艺,干法刻蚀图形外GaAs和复合介质层;
13)分离管芯;
GaAs基梁式引线PIN二极管是采用P+-Al0.3Ga0.7As/I-GaAs/N+-GaAs异质结PIN结构制作的。
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