CN105448918A - 互补金属氧化物半导体与其制作方法 - Google Patents

互补金属氧化物半导体与其制作方法 Download PDF

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CN105448918A
CN105448918A CN201410524514.7A CN201410524514A CN105448918A CN 105448918 A CN105448918 A CN 105448918A CN 201410524514 A CN201410524514 A CN 201410524514A CN 105448918 A CN105448918 A CN 105448918A
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oxide semiconductor
barrier layer
cmos
metal oxide
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CN105448918B (zh
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赖建铭
黄建中
曾于庭
蔡雅卉
王裕平
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US15/194,577 priority patent/US9721840B2/en
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Abstract

本发明公开一种互补金属氧化物半导体与其制作方法，包含一P型晶体管以及一N型晶体管。P型晶体管具有一P型金属栅极，该P型金属栅极包含一底阻障层、一P型功函数金属层、一N型调和层、一N型功函数金属层以及一金属层。N型晶体管包含一N型金属栅极，该N型金属栅极包含该N型调和层、该N型功函数金属层以及该金属层。本发明还另外提供了一种形成所述互补式金属氧化物半导体的方法。

Description

互补金属氧化物半导体与其制作方法
技术领域
本发明涉及一种互补式金属氧化物半导体与其制作方法，特别是涉及一种具有N型调和层的互补式金属氧化物半导体与其制作方法。
背景技术
在现有半导体产业中，多晶硅广泛地应用于半导体元件如金属氧化物半导体(metal-oxide-semiconductor，MOS)晶体管中，作为标准的栅极材料选择。然而，随着MOS晶体管尺寸持续地微缩，传统多晶硅栅极因硼穿透(boronpenetration)效应导致元件效能降低，及其难以避免的空乏效应(depletioneffect)等问题，使得等效的栅极介电层厚度增加、栅极电容值下降，进而导致元件驱动能力的衰退等困境。因此，半导体业界更尝以新的栅极材料，例如利用功函数(workfunction)金属来取代传统的多晶硅栅极，用以作为匹配高介电常数(High-K)栅极介电层的控制电极。
而在互补式金属氧化物半导体(complementarymetal-oxidesemiconductor，CMOS)元件中，双功函数金属栅极一方面需与NMOS元件搭配，另一方面则需与PMOS元件搭配，因此使得相关元件的整合技术以及制作工艺控制更形复杂，且各材料的厚度与成分控制要求也更形严苛。双功函数金属栅极的制作方法可大概分为前栅极(gatefirst)制作工艺及后栅极(gatelast)制作工艺两大类。其中前栅极制作工艺会在形成金属栅极后始进行源极/漏极超浅接面活化回火以及形成金属硅化物等高热预算制作工艺，因此使得材料的选择与调整面对较多的挑战。为避免上述高热预算环境并获得较宽的材料选择，业界提出以后栅极制作工艺取代前栅极制作工艺的方法。
而现有后栅极制作工艺中，先形成一牺牲栅极(sacrificegate)或取代栅极(replacementgate)，并在完成一般MOS晶体管的制作后，将牺牲/取代栅极移除而形成一栅极凹槽(gatetrench)，再依电性需求于栅极凹槽内填入不同的金属。但由于后栅极制作工艺相当复杂，需要多道制作工艺才能完成，且容易造成电性的不稳定，因此目前厂商都致力开发更好品质的金属栅极的制作工艺。
发明内容
本发明的目的在于提供一种制作具有金属栅极的半导体元件的方法，可得到优选的制作工艺可靠度。
为达上述目的，根据本发明的其中一个实施方式，本发明提供了一种互补式金属氧化物半导体结构，包含一P型晶体管以及一N型晶体管。P型晶体管具有一P型金属栅极，该P型金属栅极包含一底阻障层、一P型功函数金属层、一N型调和层、一N型功函数金属层以及一金属层。N型晶体管包含一N型金属栅极，该N型金属栅极包含该N型调和层、该N型功函数金属层以及该金属层。
根据本发明另一实施例，本发明另外提供一种形成互补式金属氧化物半导体的方法。首先提供一介电层，其具有一第一沟槽以及一第二沟槽，然后在第一沟槽以及第二沟槽中形成一底阻障层以及一P型功函数金属层。接着移除第二沟槽中的底阻障层以及P型功函数金属层，并在第一沟槽以及第二沟槽中形成一N型调和层以及一N型功函数金属层。最后，形成一金属层以完全填满第一沟槽以及第二沟槽。
本发明考虑到N型晶体管特殊的电性需求，因此会将原先形成在第二沟槽中的底阻障层以及P型功函数金属层移除，并重新形成N型调和层并搭配N型功函数金属层，以获得N型晶体管的最佳电性表现。
附图说明
图1至图10为本发明的一实施例中形成互补式金属氧化物半导体的步骤示意图。
主要元件符号说明
300基底410第一间隙壁
302浅沟槽隔离412第一轻掺杂漏极
306接触洞蚀刻停止层414第一源极/漏极
308层内介电层416第一沟槽
317底阻障层418第一金属栅极
317a第一底阻障层500第二主动区域
317b第二底阻障层502第二导电型晶体管
318P型功函数金属层504第二介质层
320N型调和层505第二高介电常数层
322N型功函数金属层507第二蚀刻停止层
326金属层506第二牺牲栅极
400第一主动区域508第二盖层
402第一导电型晶体管510第二间隙壁
404第一介质层512第二轻掺杂漏极
405第一高介电常数层514第二源极/漏极
407第一蚀刻停止层516第二沟槽
408第一盖层518第二金属栅极
406第一牺牲栅极
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的数个优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
请参考图1至图10，所绘示为本发明的一实施例中一种形成互补式金属氧化物半导体的步骤示意图。如图1所示，首先提供一基底300，例如是一硅基底、含硅基底或硅覆绝缘(silicon-on-insulator，SOI)基底等。基底300上具有多个浅沟槽隔离(shallowtrenchisolation，STI)302。通过浅沟槽隔离302所包围的区域，可定义出彼此电性绝缘的一第一主动区域400以及一第二主动区域500。接着分别于第一主动区域400与第二主动区域500的基底300上形成一第一导电型晶体管402与一第二导电型晶体管502。在本实施例中，第一导电型晶体管402为一P型晶体管，而第二导电型晶体管502为一N型晶体管。
如图1所示，第一导电型晶体管402包含一第一介质层404、一第一高介电常数层405、一第一蚀刻停止层407、一第一牺牲栅极406、一第一盖层408、一第一间隙壁410、一第一轻掺杂漏极(lightdopeddrain，LDD)412以及一第一源极/漏极414。在本发明优选实施例中，第一介质层404为一二氧化硅层，第一高介电常数层405的介电常数大约大于4，其可以是稀土金属氧化物层或镧系金属氧化物层，例如氧化铪(hafniumoxide,HfO2)、硅酸铪氧化合物(hafniumsiliconoxide,HfSiO4)、硅酸铪氮氧化合物(hafniumsiliconoxynitride,HfSiON)、氧化铝(aluminumoxide,Al2O3)、氧化镧(lanthanumoxide,La2O3)、铝酸镧(lanthanumaluminumoxide,LaAlO)、氧化钽(tantalumoxide,Ta2O5)、氧化锆(zirconiumoxide,ZrO2)、硅酸锆氧化合物(zirconiumsiliconoxide,ZrSiO4)、锆酸铪(hafniumzirconiumoxide,HfZrO)、氧化镱(yttriumoxide,Yb2O3)、氧化硅镱(yttriumsiliconoxide,YbSiO)、铝酸锆(zirconiumaluminate,ZrAlO)、铝酸铪(hafniumaluminate,HfAlO)、氮化铝(aluminumnitride,AlN)、氧化钛(titaniumoxide,TiO2),氮氧化锆(zirconiumoxynitride,ZrON)、氮氧化铪(hafniumoxynitride,HfON)、氮氧硅锆(zirconiumsiliconoxynitride,ZrSiON)、氮氧硅铪(hafniumsiliconoxynitride,HfSiON)、锶铋钽氧化物(strontiumbismuthtantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconatetitanate,PbZrxTi1-xO3,PZT)或钛酸钡锶(bariumstrontiumtitanate,BaxSr1-xTiO3,BST)，但不以上述为限。第一蚀刻停止层407包含金属层或金属氮化物层，例如是氮化钛(TiN)。而于其他实施例中，第一蚀刻停止层407也可以省略。第一牺牲栅极406则例如是多晶硅栅极，但也可以是由多晶硅层、非晶硅(amorphousSi)或者锗层所组合的复合栅极。第一盖层408则例如是一氮化硅层。第一间隙壁410可为一复合膜层的结构，其可包含高温氧化硅层(hightemperatureoxide,HTO)、氮化硅、氧化硅或使用六氯二硅烷(hexachlorodisilane,Si2Cl6)形成的氮化硅(HCD-SiN)。第一轻掺杂漏极412以及第一源极/漏极414则以适当浓度的掺杂加以形成。
第二导电型晶体管502包含一第二介质层504、一第二高介电常数层505、一第二蚀刻停止层507、一第二牺牲栅极506、一第二盖层508、一第二间隙壁510、一第二轻掺杂漏极512以及一第二源极/漏极514。第二导电型晶体管502中各元件的实施方式大致与第一导电型晶体管402相同，在此不加以赘述。此外，虽然图1中未明白绘出，但第一导电型晶体管402与第二导电型晶体管502仍可包含其他半导体结构，例如金属硅化物层(salicide)、以选择性外延成长(selectiveepitaxialgrowth,SEG)而形成具有六面体(hexagon，又叫sigmaΣ)或八面体(octangon)截面形状的源极/漏极或是其他保护层。在形成了第一导电型晶体管402与第二导电型晶体管502后，于基底300上依序形成一接触洞蚀刻停止层(contactetchstoplayer,CESL)306与一内层介电层(inter-layerdielectric,ILD)308，覆盖在第一导电型晶体管402与第二导电型晶体管502上。
如图2所示，接着进行一平坦化制作工艺，例如一化学机械平坦化(chemicalmechanicalpolish,CMP)制作工艺或者一回蚀刻制作工艺或两者的组合，以依序移除部分的内层介电层308、部分的接触洞蚀刻停止层306、部分的第一间隙壁410、部分的第二间隙壁510，并完全移除第一盖层408、第二盖层508，直到暴露出第一牺牲栅极406与第二牺牲栅极506的顶面。
如图3所示，进行一蚀刻制作工艺例如是湿蚀刻制作工艺以移除第一牺牲栅极406以及第二牺牲栅极506，此蚀刻步骤优选会停止在第一蚀刻停止层407以及第二蚀刻停止层507，并在第一导电型晶体管402中形成一第一沟槽(trench)416，在第二导电型晶体管502中形成一第二沟槽516。
如图4所示，在基底300上全面形成一底阻障层(barrierlayer)317，其会沿着第一沟槽416以及第二沟槽516的表面形成，但并不完全填满第一沟槽416以及第二沟槽516。底阻障层317可以是单层或多层结构，在本发明优选实施例中，底阻障层317包含一第一底阻障层317a以及一第二底阻障层317b，两者的材料包含金属层或金属氮化物层，例如第一底阻障层317a是氮化钽(TaN)，而第二顶底阻障层317b是氮化钛(TiN)。在本发明优选实施例中，底阻障层317，特别是第一底阻障层317a和第二蚀刻停止层507具有蚀刻选择比。
接着如图5所示，在底阻障层317上形成一P型功函数金属层318，使P型功函数金属层318同时填入第一沟槽416以及第二沟槽516中，但不会完全填满第一沟槽416与第二沟槽516。P型功函数金属层318为一满足P型晶体管所需功函数要求的金属，例如是氮化钛(TiN)，也可以是镍(Ni)、钯(Pd)、铂(Pt)、铍(Be)、铱(Ir)、碲(Te)、铼(Re)、钌(Ru)、铑(Rh)、钨(W)、钼(Mo)；钨、钌、钼、钽(Ta)的氮化物，或是钨、钽、钛的碳化物等。
如图6所示，移除位于第二主动区域500，特别是第二沟槽516中的P型功函数金属层318、底阻障层317(包含底底阻障层317a以及顶底阻障层317b)。而由于底阻障层317和第二蚀刻停止层507具有蚀刻选择比，因此移除步骤优选不会影响下方的第二高介电常数层505。
如图7所示，在基底300上形成一N型调和层(Ntypeworkfunctiontuninglayer)320。N型调和层320会在第一主动区域400中沿着P型功函数金属层318的表面，以及第二主动区域500中沿着第二沟槽516以及第二蚀刻停止层507的表面形成，但并不完全填满第二沟槽516以及第一沟槽416。在本发明优选实施例中，N型调和层320为一调和N型晶体管功函数金属层的材料，例如是氮化钛(TiN)或是氮化钽(TaN)，且由于电性搭配考虑，可以是氮浓度高(Nrich)或是钛/钽浓度高(TirichorTarich)的材料。若是氮浓度高的材料，形成方法例如是先形成氮化钛(TiN)或氮化钽(TaN)层，接着再进行氮处理(nitridationtreatment)。而于本发明另一实施例中，在进行氮处理时可利用掩模将第一主动区域400覆盖，而仅使第二主动区域500的N型调和层320接受氮处理。而于本发明又一实施例中，在进行氮处理之后，也可选择性地移除位于第一主动区域400中的N型调和层320。本发明所提供的各种实施型态的N型调和层，考虑到N型晶体管特殊的电性需求，且将原先形成在第二沟槽516中的底阻障层317以及P型功函数金属层318移除，并重新形成适合调节N型功函数金属层322的N型调和层320，因此N型晶体管可以获得最佳电性表现。
如图8所示，在基底300上全面形成一N型功函数金属层322，填入在第一沟槽416以及第二沟槽516中，以覆盖N型调和层320。在本发明优选实施例中，N型功函数金属层322为一满足N型晶体管所需功函数要求的金属，例如是铝化钛(titaniumaluminides,TiAl)、铝化锆(aluminumzirconium,ZrAl)、铝化钨(aluminumtungsten,WAl)、铝化钽(aluminumtantalum,TaAl)或铝化铪(aluminumhafnium,HfAl)，但不以上述为限。后续，可选择性的在N型功函数金属层322上形成一顶阻障层324，例如是氮化钛(TiN)、碳化铝钛(TiAlC)、氮化铝钛(TiAlN)、氮化钽(TaN)、碳化铝钽(TaAlC)、氮化铝钽(TaAlN)、碳化铜钛(TiCuC)、氮化铜钛(TiCuN)、碳化铜钽(TaCuC)、氮化铜钽(TaCuN)等，但并不以此为限。
如图9所示，在基底300上全面形成一低电阻的金属层326。金属层326会形成于顶阻障层324上，并填满第二沟槽516以及第一沟槽416。在本发明优选实施例中，金属层326包含铝(Al)、钛(Ti)、钽(Ta)、钨(W)、铌(Nb)、钼(Mo)、铜(Cu)、氮化钛(TiN)、碳化钛(TiC)、氮化钽(TaN)、钛钨(Ti/W)或钛与氮化钛(Ti/TiN)等复合金属层料，但不以此为限。
最后，如图10所示，进行一平坦化制作工艺以同时移除第一沟槽416以及第二沟槽516以外的金属层326、顶阻障层324、N型功函数金属层322、N型调和层320、P型功函数金属层318、底阻障层317。如此一来，位于第一沟槽416内的第一蚀刻停止层407、底阻障层317、P型功函数金属318、N型调和层320、N型功函数金属322、顶阻障层324以及块状的金属层326会形成第一导电型晶体管402(P型晶体管)中的第一金属栅极418，且其功函数大致上介于4.8eV与5.2eV之间；而位于第二沟槽518内的第二蚀刻停止层507、N型调和层320、N型功函数金属层322以及块状的金属层326会形成第二导电型晶体管502(N型晶体管)中的第二金属栅极518，且其功函数大致上介于3.9eV与4.3eV之间。
值得注意的是，前述实施方式先形成高介电常数的栅极介电层为例(即high-Kfirst制作工艺)，而本领域技术人士应当了解，本发明也可在形成金属栅极之前再次形成高介电常数的栅极介电层(即high-Klast制作工艺)，例如在第一沟槽416与第二沟槽516内形成P型功函数金属层318、底阻障层317之前，可先去除原先生成的高介电常数层405，然后在第一沟槽416以及第二沟槽516的表面上形成高介电常数的栅极介电层，然后再依序形成P型功函数金属层318以及金属层326等结构。此位于第一沟槽416内的高介电常数的栅极介电层会和P型功函数金属层318一样具有U型剖面。并且，前述实施例都以平面晶体管(planartransistor)为示例，本领域具有通常知识者也可了解，本发明的结构与制作工艺也可应用在非平面晶体管(non-planartransistor)上，例如是鳍状晶体管(Fin-FET)等。
综上而言，本发明提出了一种形成互补式金属氧化物半导体晶体管以及其形成方法。由于本发明考虑到N型晶体管特殊的电性需求，因此会将原先形成在第二沟槽中的底阻障层以及P型功函数金属层移除，并重新形成N型调和层并搭配N型功函数金属层，以获得N型晶体管最佳电性表现。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种互补式金属氧化物半导体(complementarymetaloxidesemiconductor,CMOS)，包含：
P型晶体管，其具有P型金属栅极，该P型金属栅极包含底阻障层、P型功函数金属层、N型调和层、N型功函数金属层以及金属层；以及
N型晶体管，其包含N型金属栅极，该N型金属栅极包含该N型调和层、该N型功函数金属层以及该金属层。
2.如权利要求1所述的互补式金属氧化物半导体，其中该P型金属栅极依序包含该底阻障层、该P型功函数金属层、该N型调和层、该N型功函数金属层以及该金属层。
3.如权利要求1所述的互补式金属氧化物半导体，其中该N型金属栅极依序包含该N型调和层、该N型功函数金属层以及该金属层。
4.如权利要求1所述的互补式金属氧化物半导体，其中该N型金属栅极不包含该底阻障层以及该P型功函数金属层。
5.如权利要求1所述的互补式金属氧化物半导体，其中该N型调和层包含氮化钛(TiN)或氮化钽(TaN)。
6.如权利要求5所述的互补式金属氧化物半导体，其中该N型调和层的氮浓度大于钛或钽的浓度。
7.如权利要求5所述的互补式金属氧化物半导体，其中该N型调和层的氮浓度小于钛或钽的浓度。
8.如权利要求1所述的互补式金属氧化物半导体，其中该P型金属栅极以及N型金属栅极还包含顶阻障层，设置在该N型功函数金属层以及该金属层之间。
9.如权利要求1所述的互补式金属氧化物半导体，其中该底阻障层包含第一底阻障层以及第二底阻障层。
10.如权利要求9所述的互补式金属氧化物半导体，其中该第一底阻障层包含氮化钛，该第二底阻障层包含氮化钽。
11.如权利要求1所述的互补式金属氧化物半导体，其中该N型金属栅极还包含蚀刻停止层，该N型调和层位于该蚀刻停止层以及该N型功函数金属层之间，且该蚀刻停止层与该N型调和层具有蚀刻选择比。
12.一种形成互补式金属氧化物半导体的方法，包含：
提供一介电层，其具有一第一沟槽以及一第二沟槽；
在该第一沟槽以及该第二沟槽中形成一底阻障层以及一P型功函数金属层；
移除该第二沟槽中的该底阻障层以及该P型功函数金属层；
在该第一沟槽以及该第二沟槽中形成一N型调和层以及一N型功函数金属层；以及
形成一金属层以完全填满该第一沟槽以及该第二沟槽。
13.如权利要求12所述的形成互补式金属氧化物半导体的方法，其中在形成该底阻障层之前，还包含在该第二沟槽中形成一蚀刻停止层。
14.如权利要求13所述的形成互补式金属氧化物半导体的方法，其中移除该第二沟槽中的该底阻障层以及该P型功函数金属层的步骤，是以该蚀刻停止层为停止层。
15.如权利要求12所述的形成互补式金属氧化物半导体的方法，其中该N型调和层包含氮化钛(TiN)或氮化钽(TaN)。
16.如权利要求15所述的形成互补式金属氧化物半导体的方法，其中形成该N型调和层的步骤包含一氮处理。
17.如权利要求16所述的形成互补式金属氧化物半导体的方法，其中进行该氮处理时，以一掩模覆盖该第一沟槽。
18.如权利要求12所述的形成互补式金属氧化物半导体的方法，其中在形成该金属层之前，还包含形成一顶阻障层在该N型功函数金属层上。
19.如权利要求12所述的形成互补式金属氧化物半导体的方法，其中该底阻障层包含第一底阻障层以及第二底阻障层。
20.如权利要求19所述的形成互补式金属氧化物半导体的方法，其中该第一底阻障层包含氮化钛，该第二底阻障层包含氮化钽。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108123034A (zh) * 2016-11-28 2018-06-05 台湾积体电路制造股份有限公司 具有复合式顶部电极的内嵌式存储器装置
CN108538837A (zh) * 2018-03-29 2018-09-14 上海华力集成电路制造有限公司 半导体器件及其形成方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160054830A (ko) * 2014-11-07 2016-05-17 삼성전자주식회사 반도체 소자의 제조 방법
CN106409830B (zh) * 2015-07-27 2020-05-05 联华电子股份有限公司 具有金属栅极的半导体元件及其制作方法
CN106684041B (zh) * 2015-11-10 2020-12-08 联华电子股份有限公司 半导体元件及其制作方法
US9876083B2 (en) * 2016-01-29 2018-01-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices, FinFET devices and methods of forming the same
US9825122B1 (en) 2017-02-23 2017-11-21 International Business Machines Corporation Multiple work function device using GeOx/TiN cap on work function setting metal
US11114347B2 (en) 2017-06-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Self-protective layer formed on high-k dielectric layers with different materials
US10283417B1 (en) * 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Self-protective layer formed on high-k dielectric layers with different materials
US20190096679A1 (en) * 2017-09-22 2019-03-28 Globalfoundries Inc. Gate stack processes and structures
KR102403723B1 (ko) 2017-12-15 2022-05-31 삼성전자주식회사 반도체 장치 및 그의 제조 방법
US10204828B1 (en) 2018-02-09 2019-02-12 International Business Machines Corporation Enabling low resistance gates and contacts integrated with bilayer dielectrics
US11489059B2 (en) * 2020-01-14 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, FinFET devices and methods of forming the same
US20220208974A1 (en) * 2020-12-30 2022-06-30 Changxin Memory Technologies, Inc. Method for manufacturing semiconductor structure and semiconductor structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347216A (zh) * 2010-07-27 2012-02-08 三星电子株式会社 使用酸扩散制造半导体器件的方法
US20120319205A1 (en) * 2011-06-16 2012-12-20 Globalfoundries Inc. High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technology
US20140252423A1 (en) * 2013-03-05 2014-09-11 United Microelectronics Corp. Semiconductor device having metal gate and manufacturing method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101178166B1 (ko) * 2009-04-28 2012-08-30 캐논 아네르바 가부시키가이샤 반도체 장치 및 그 제조 방법
JP5442332B2 (ja) * 2009-06-26 2014-03-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8580641B2 (en) * 2011-07-26 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Techniques providing high-k dielectric metal gate CMOS
US8895434B2 (en) * 2012-11-14 2014-11-25 International Business Machines Corporation Replacement metal gate structure for CMOS device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347216A (zh) * 2010-07-27 2012-02-08 三星电子株式会社 使用酸扩散制造半导体器件的方法
US20120319205A1 (en) * 2011-06-16 2012-12-20 Globalfoundries Inc. High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technology
US20140252423A1 (en) * 2013-03-05 2014-09-11 United Microelectronics Corp. Semiconductor device having metal gate and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108123034A (zh) * 2016-11-28 2018-06-05 台湾积体电路制造股份有限公司 具有复合式顶部电极的内嵌式存储器装置
CN108123034B (zh) * 2016-11-28 2022-11-22 台湾积体电路制造股份有限公司 具有复合式顶部电极的内嵌式存储器装置
CN108538837A (zh) * 2018-03-29 2018-09-14 上海华力集成电路制造有限公司 半导体器件及其形成方法

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