CN105426336A - Data processing system and data reading output method - Google Patents
Data processing system and data reading output method Download PDFInfo
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- CN105426336A CN105426336A CN201510759529.6A CN201510759529A CN105426336A CN 105426336 A CN105426336 A CN 105426336A CN 201510759529 A CN201510759529 A CN 201510759529A CN 105426336 A CN105426336 A CN 105426336A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- Programmable Controllers (AREA)
Abstract
The invention provides a data processing system and a data reading output method. The data processing system comprises an embedded processor and a programmable logic device, wherein the embedded processor comprises an SPI (Serial Peripheral Interface) bus and an interrupt signal line; a first data line of the programmable logic device is connected to the SPI bus of the embedded processor; a second data line of the programmable logic device is connected to the interrupt signal line of the embedded processor; and a third data line of the programmable logic device is taken as a general input/output port of the data processing system. The data reading output method comprises the following steps that the embedded processor outputs data through the SPI bus; and the first data line of the programmable logic device controls a corresponding status register to update the status data according to the received data. According to the data processing system, extension of the general input/output port o is carried out through the programmable logic device, the cost is low and the application range of the embedded processor is greatly expanded.
Description
Technical field
The present invention relates to a kind of data processing field, particularly relate to a kind of data handling system, digital independent output intent.
Background technology
At present, a processor is generally all needed to be used for the operation of control and management whole system in Ethernet switch.But along with the development of science and technology and the raising of chip technology technology, increasing processor is that user provides that more and more higher single-chip performance, simultaneously single-chip size are more and more less and power consumption is more and more lower, thus thus the design had great convenience for the user, also effectively reduces cost.
Along with switch function from strength to strength, to GPIO (General-PurposeInput/OutputPorts, general input/output port) quantity required also grow with each passing day, certain customers run into the not enough situation of such as GPIO in actual design.
SPI is the abbreviation of Serial Peripheral Interface (SPI) (SerialPeripheralInterface).SPI is a kind of high speed, full duplex, synchronous communication bus, and on the pin of chip, only take four lines, SDI (data input), SDO (data output), SCLK (clock), CS (sheet choosing).Save the pin of chip, simultaneously for the layout of PCB saves space, provided convenience, just for this characteristic be simple and easy to, nowadays this communication protocol of increasing integrated chip.
Now a lot of CPU is integrated with SPI interface, the GPIO of extension CPU can be carried out by spi bus.Prior art has expands GPIO by special SPI chip.But this special SPI chip price is high, and the quantity of expansion is certain, does not have dirigibility.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of data handling system, method for reading data and data output method, for solving the problem that in prior art, the general input/output port of flush bonding processor is inadequate.
For achieving the above object and other relevant objects, the invention provides a kind of data handling system, described data handling system comprises: flush bonding processor, and described flush bonding processor comprises: spi bus and look-at-me line; Programmable logic device, its first data line connects the spi bus of described embedded device; Second data line connects the look-at-me line of described flush bonding processor; 3rd data line is as the general input/output port of described data handling system.
In one embodiment of the invention, the data input signal line of described spi bus, data output signal line, clock cable and chip selection signal line connect the first data line of described programmable logic device respectively.
In one embodiment of the invention, described data handling system also comprises: jtag circuit, and described jtag circuit comprises: connector, the first resistance, the second resistance and the 3rd resistance; First pin of described connector connects the test clock input end of described programmable logic controller (PLC) and the first end of described 3rd resistance; Second end ground connection of described 3rd resistance; 3rd pin of described connector connects the test data output terminal of described programmable logic controller (PLC); 5th pin of described connector connects the test pattern selecting side of described programmable logic controller (PLC) and the first end of described first resistance; Second end of described first resistance connects power supply; 9th pin of described connector connects the test data input end of described programmable logic controller (PLC) and the first end of described second resistance; Second end of described second resistance connects power supply; Second pin of described connector and the tenth pin ground connection; 4th pin of described connector connects power supply.
In one embodiment of the invention, described jtag circuit also comprises the first electric capacity, and the first end of described first electric capacity connects power supply; Second end ground connection of described first electric capacity.
In one embodiment of the invention, the 6th pin of described connector, the 7th pin and the 8th pin are unsettled.
In one embodiment of the invention, described data handling system also comprises: crystal oscillating circuit, and the clock signal output terminal of described crystal oscillating circuit connects the clock signal input terminal of described programmable logic controller (PLC); The voltage input end of described crystal oscillating circuit is all connected power supply with Enable Pin.
In one embodiment of the invention, described crystal oscillating circuit also comprises the second electric capacity, and the first end of described second electric capacity connects power supply, the second end ground connection of described second electric capacity.
In one embodiment of the invention, described data handling system also comprises: status register and interrupt register; Described status register is connected with interrupt register is corresponding with the 3rd data line of described programmable logic controller (PLC).
The invention provides a kind of digital independent output intent, be applicable to aforesaid data handling system; When reading the data, described digital independent output intent comprises the following steps: the 3rd data line of programmable logic device receives input signal; With the corresponding data position in the corresponding status register connected of described 3rd data line according to described input signal more new state data, and become high level with the respective flag position in the corresponding interrupt register connected of described 3rd data line; Second data line of described programmable logic device exports look-at-me; Described embedded device reads the status data upgraded in described status register by spi bus according to described look-at-me; Respective flag position in described interrupt register becomes low level; When exporting data, described digital independent output intent comprises the following steps: flush bonding processor exports data by spi bus; 3rd data line of programmable logic device is according to the corresponding status register of the described Data Control more new state data received.
As mentioned above, data handling system of the present invention, method for reading data and data output method, have following beneficial effect:
In data handling system of the present invention, by the expansion of general input/output port can be carried out by snoop logic controller, both achieved low cost, greatly expanded again the usable range of flush bonding processor.
Accompanying drawing explanation
Fig. 1 is shown as the structural representation of data handling system of the present invention in an embodiment.
Fig. 2 is shown as the structural representation of data handling system of the present invention in another embodiment.
Fig. 3 is shown as the schematic flow sheet of digital independent output intent of the present invention in an embodiment.
Fig. 4 is shown as the schematic flow sheet of digital independent output intent of the present invention in another embodiment.
Element numbers explanation
1 other equipment
2 data handling systems
21 flush bonding processors
22 programmable logic devices
23JTAG circuit
24 crystal oscillating circuits
S11 ~ S15 step
S21 ~ S22 step
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this instructions can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this instructions also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.It should be noted that, when not conflicting, the feature in following examples and embodiment can combine mutually.
It should be noted that, the diagram provided in following examples only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As described in the background art; the situation that the input/output end port of flush bonding processor is inadequate usually can be run in prior art; thus limit the usable range of flush bonding processor, and when special SPI chip carries out ports-Extending, considerably increase cost again.
Refer to Fig. 1, the invention provides a kind of data handling system, described data handling system 2 comprises:
Flush bonding processor 21, described flush bonding processor 21 comprises: spi bus and look-at-me line INT;
Programmable logic device 22, its first data line I/O connects the spi bus of described embedded device 21; Second data line I/O connects the look-at-me line INT of described flush bonding processor 21; 3rd data line I/O is as the general input/output port of described data handling system.3rd data line I/O of described Programmadle logic device can connect other equipment 1.
It should be noted that, described 3rd data line I/O can be that multiple, concrete quantity can be selected according to the actual requirements.
Particularly, with reference to figure 2, the data input signal line SDI of described spi bus, data output signal line SDO, clock cable SCLK and chip selection signal line CS connect the first data line I/O of described programmable logic device 22 respectively.
Continue with reference to figure 2, described data handling system 2 can also comprise: jtag circuit 23, and described jtag circuit 23 comprises: connector J1, the first resistance R1, the second resistance R2 and the 3rd resistance R3.
First pin of described connector J1 connects the test clock input end TCLK of described programmable logic controller (PLC) 22 and the first end of described 3rd resistance R3; The second end ground connection GND of described 3rd resistance R3;
3rd pin of described connector J1 connects the test data output terminal TDO of described programmable logic controller (PLC) 22;
5th pin of described connector J1 connects the test pattern selecting side TMS of described programmable logic controller (PLC) 22 and the first end of described first resistance R1; Second end of described first resistance R1 connects power supply VCC;
9th pin of described connector J1 connects the test data input end TDI of described programmable logic controller (PLC) 22 and the first end of described second resistance R2; Second end of described second resistance R2 connects power supply VCC;
Second pin of described connector J1 and the tenth pin ground connection GND; Described connector J1 the 4th pin connects power supply VCC.
6th pin of described connector J1, the 7th pin and the 8th pin are unsettled.
In the present embodiment, described jtag circuit 23 also comprises the first electric capacity C1, and the first end of described first electric capacity C1 connects power supply VCC; The second end ground connection of described first electric capacity C1.
In the present embodiment, described data handling system 2 can also comprise: crystal oscillating circuit 24.Particularly, with reference to figure 2, the clock signal output terminal OUT of described crystal oscillating circuit 24 connects the clock signal input terminal CLK of described programmable logic controller (PLC) 22; The voltage input end VCC of described crystal oscillating circuit 24 is all connected power supply VCC with Enable Pin EN.
Described crystal oscillating circuit 24 also comprises the second electric capacity C2, and the first end of described second electric capacity CW connects power supply VCC, the second end ground connection GND of described second electric capacity C2.
In the present embodiment, described data handling system also comprises: status register and interrupt register (not shown); Described status register is connected with interrupt register is corresponding with the 3rd data line of described programmable logic controller (PLC).Particularly, all corresponding status register of each article the 3rd data line and an interrupt register.For example, 8 positions of the 3rd data line IO1 ~ IO8 respectively corresponding 8 bit status registers, this state post device everybody reflect the level state of the 3rd data line IO1 ~ IO8 respectively; Correspondingly, 8 positions of the 3rd data line IO1 ~ IO8 respectively corresponding 8 interrupt registers, thus post every of device by described interruption and reflect whether the level of the 3rd data line IO1 ~ IO8 changes, when level changes, carry out interrupt processing.
Below the principle of work of above-mentioned data handling system is described further.
First, when having data to input in the 3rd data line of programmable logic controller (PLC), such as, the level of the 3rd data line IO1 becomes 1 from 0, corresponding positions in the status register that then this data line IO1 is corresponding becomes 1, and zone bit corresponding to the interrupt register of correspondence becomes 1 from 0, the look-at-me alignment programmable logic controller (PLC) of flush bonding processor sends look-at-me simultaneously, after described programmable logic controller gets look-at-me, know that port level changes, flush bonding processor starts spi bus, the level of this port is read from the status register that data line IO1 is corresponding, thus complete the reading of data.Then, the zone bit clear 0 that corresponding interrupt register is corresponding.
And when if the 3rd data line IO1 output will be allowed to become 1 from 0, first programmable logic controller (PLC) triggers described flush bonding processor startup spi bus, only need post to the state that this data line IO1 is corresponding in device and write 1, then namely the output of IO become 1 from 0.
Data handling system of the present invention, the expansion of general input/output port is carried out by programmable logic controller (PLC), when substantially not increasing cost, extending the available general output/output port of flush bonding processor greatly, thus improve the range of application of flush bonding processor.
With reference to figure 3, the present invention also provides a kind of digital independent output intent, is applicable to aforesaid data handling system; When reading the data, described digital independent output intent comprises the following steps:
S11, the 3rd data line of programmable logic device receives input signal;
S12, with the corresponding data position in the corresponding status register connected of described 3rd data line according to described input signal more new state data, and becomes high level with the respective flag position in the corresponding interrupt register connected of described 3rd data line;
S13, the second data line of described programmable logic device exports look-at-me;
S14, described embedded device reads the status data upgraded in described status register by spi bus according to described look-at-me;
S15, the respective flag position in described interrupt register becomes low level.
The detailed process of method for reading data of the present invention with reference to the specific descriptions of the aforementioned principle of work about data handling system, can not repeat them here.
With reference to figure 4, when exporting data, described digital independent output intent comprises the following steps:
S21, flush bonding processor exports data by spi bus;
S22, the 3rd data line of programmable logic device is according to the corresponding status register of the described Data Control more new state data received.
The detailed process of data output method of the present invention with reference to the specific descriptions of the aforementioned principle of work about data handling system, can not repeat them here.
In sum, data handling system of the present invention, digital independent output intent, achieve the expansion of the general input/output port of flush bonding processor, not only substantially increases the usable range of flush bonding processor, and reduce the cost of system.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (9)
1. a data handling system, is characterized in that, described data handling system comprises:
Flush bonding processor, described flush bonding processor comprises: spi bus and look-at-me line;
Programmable logic device, its first data line connects the spi bus of described embedded device; Second data line connects the look-at-me line of described flush bonding processor; 3rd data line is as the general input/output port of described data handling system.
2. data handling system according to claim 1, is characterized in that: the data input signal line of described spi bus, data output signal line, clock cable and chip selection signal line connect the first data line of described programmable logic device respectively.
3. data handling system according to claim 1, is characterized in that, described data handling system also comprises: jtag circuit, and described jtag circuit comprises: connector, the first resistance, the second resistance and the 3rd resistance;
First pin of described connector connects the test clock input end of described programmable logic controller (PLC) and the first end of described 3rd resistance; Second end ground connection of described 3rd resistance;
3rd pin of described connector connects the test data output terminal of described programmable logic controller (PLC);
5th pin of described connector connects the test pattern selecting side of described programmable logic controller (PLC) and the first end of described first resistance; Second end of described first resistance connects power supply;
9th pin of described connector connects the test data input end of described programmable logic controller (PLC) and the first end of described second resistance; Second end of described second resistance connects power supply;
Second pin of described connector and the tenth pin ground connection; 4th pin of described connector connects power supply.
4. data handling system according to claim 3, is characterized in that, described jtag circuit also comprises the first electric capacity, and the first end of described first electric capacity connects power supply; Second end ground connection of described first electric capacity.
5. data handling system according to claim 3, is characterized in that, the 6th pin of described connector, the 7th pin and the 8th pin are unsettled.
6. data handling system according to claim 1, is characterized in that, described data handling system also comprises: crystal oscillating circuit, and the clock signal output terminal of described crystal oscillating circuit connects the clock signal input terminal of described programmable logic controller (PLC); The voltage input end of described crystal oscillating circuit is all connected power supply with Enable Pin.
7. data handling system according to claim 6, is characterized in that: described crystal oscillating circuit also comprises the second electric capacity, and the first end of described second electric capacity connects power supply, the second end ground connection of described second electric capacity.
8. data handling system according to claim 1, is characterized in that, described data handling system also comprises: status register and interrupt register; Described status register is connected with interrupt register is corresponding with the 3rd data line of described programmable logic controller (PLC).
9. a digital independent output intent, be applicable to as arbitrary in claim 1 ~ 8 as described in data handling system; It is characterized in that, when reading the data, described digital independent output intent comprises the following steps:
3rd data line of programmable logic device receives input signal;
With the corresponding data position in the corresponding status register connected of described 3rd data line according to described input signal more new state data, and become high level with the respective flag position in the corresponding interrupt register connected of described 3rd data line;
Second data line of described programmable logic device exports look-at-me;
Described embedded device reads the status data upgraded in described status register by spi bus according to described look-at-me;
Respective flag position in described interrupt register becomes low level;
When exporting data, described digital independent output intent comprises the following steps:
Flush bonding processor exports data by spi bus;
3rd data line of programmable logic device is according to the corresponding status register of the described Data Control more new state data received.
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| CN201510759529.6A CN105426336A (en) | 2015-11-09 | 2015-11-09 | Data processing system and data reading output method |
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Cited By (1)
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