CN105374873B - MOSFET with multiple dislocation planes - Google Patents
MOSFET with multiple dislocation planes Download PDFInfo
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- CN105374873B CN105374873B CN201410770305.0A CN201410770305A CN105374873B CN 105374873 B CN105374873 B CN 105374873B CN 201410770305 A CN201410770305 A CN 201410770305A CN 105374873 B CN105374873 B CN 105374873B
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- dislocation plane
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- effect transistor
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- 239000007924 injection Substances 0.000 claims abstract description 33
- 230000005669 field effect Effects 0.000 claims abstract description 23
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- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 2
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
- Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region
Abstract
The present invention provides a kind of method, this method includes forming mos field effect transistor (MOSFET).This method includes implementing injection to form pre-amorphous injection (PAI) area of the gate electrode of neighbouring MOSFET, and strain coating is formed above PAI areas, and implements annealing to strain coating and PAI areas to form dislocation plane.Since annealing forms dislocation plane, the inclination angle of its Dislocations plane is less than about 65 degree.The invention further relates to the MOSFET with multiple dislocation planes.
Description
Cross reference to related applications
The application be submit on October 24th, 2011 it is entitled " have multiple dislocation planes MOSFET " the U.S. it is special
Profit applies for the part continuation application of the 13/280th, No. 094, and entire contents are hereby expressly incorporated by reference.
Technical field
The present invention relates to the MOSFET with multiple dislocation planes.
Background technology
In order to improve the performance of metal-oxide semiconductor (MOS) (MOS) device, the raceway groove of MOS device can be introduced a stress into
To improve carrier mobility in area.General it is desired that in the raceway groove of N-shaped MOS (" NMOS ") device on source electrode to drain directions
Tensile stress is introduced in area, and introduces compression in the channel region of p-type MOS (" PMOS ") device on source electrode to drain directions and answers
Power.Therefore the technology for improving the stress in MOS device is developed.
The content of the invention
In order to solve the problems in the existing technology, according to an aspect of the invention, there is provided a kind of method, bag
Include：Mos field effect transistor (MOSFET) is formed, it includes：It is neighbouring described to be formed to implement the first injection
First pre-amorphous injection (PAI) area of the gate electrode of MOSFET；The first strain covering is formed above the first PAI areas
Layer；And implement the first annealing to the described first strain coating and the first PAI areas to form the first dislocation plane, its
In, since the described first annealing forms the first dislocation plane, the inclination angle of the first dislocation plane is less than about 65 degree.
In the above-mentioned methods, in the first strain coating is formed, hydrogen (H is added2) it is used as process gas.
In the above-mentioned methods, in the described first annealing, the described first strain coating is exposed to ultraviolet light.
In the above-mentioned methods, the second dislocation plane of the gate electrode to form the neighbouring MOSFET is further included, wherein, it is described
First dislocation plane and the second dislocation plane are located at the same side of the gate electrode, and extend to the source of the MOSFET
In pole/drain region.
In the above-mentioned methods, the formation of the second dislocation plane is implemented after the first dislocation plane is formed, and
And the first dislocation plane and the second dislocation plane are substantially parallel to each other.
In the above-mentioned methods, the formation of the second dislocation plane is implemented after the first dislocation plane is formed, and
And the first dislocation plane and the second dislocation plane are not parallel each other.
In the above-mentioned methods, forming the second dislocation plane includes：The first strain coating is etched to remove
The horizontal component of the first strain coating is stated, wherein, the vertical component of the first strain coating of the neighbouring gate electrode
Offset spacer is not etched to form；After the etching, the second injection is implemented to form the 2nd PAI of the neighbouring gate electrode
Area；The second strain coating is formed above the 2nd PAI areas；And to the described second strain coating and described second
PAI areas implement the second annealing, wherein, since the described second annealing forms the two dislocations plane.
In the above-mentioned methods, the inclination angle of the first dislocation plane is less than about 45 degree.
In the above-mentioned methods, further include：After the first dislocation plane is formed, implement epitaxial growth with described
Epitaxial semiconductor layer is formed above the source/drain regions of MOSFET；And implement silication to be formed on the source/drain regions
Silicide area, wherein, the top of the epitaxial semiconductor layer is consumed in silication, and do not consume the extension half in silication
The bottom of conductor layer.
In the above-mentioned methods, neighbouring MOSFET etching shallow trenches isolation (STI) area is further included to be formed described in adjoining
The groove of MOSFET, wherein, the STI region has the recessed top surface below groove, and the first dislocation plane
Pinching line be higher than the STI region recessed top surface.
According to another aspect of the present invention, a kind of method is additionally provided, including：Form metal oxide semiconductor field-effect
Transistor (MOSFET), including：Implement the first injection to form the first pre-amorphous note of the gate electrode of the neighbouring MOSFET
Enter (PAI) area；The first strain coating is formed above the first PAI areas, will in the first strain coating is formed
Hydrogen is used as process gas；And the first annealing is implemented to the described first strain coating and the first PAI areas to form the
One dislocation plane, wherein, since the described first annealing forms the first dislocation plane.
In the above-mentioned methods, further include：Implement the second injection to form the 2nd PAI areas of the neighbouring gate electrode；Institute
State and the second strain coating is formed above the 2nd PAI areas；And the described second strain coating and the 2nd PAI areas are implemented
Second anneals to form the second dislocation plane, wherein, since the described second annealing forms the second dislocation plane, and it is described
Channel region of the second dislocation plane than the first dislocation plane further from the MOSFET.
In the above-mentioned methods, in the second strain coating is formed, hydrogen (H is added2) it is used as process gas.
In the above-mentioned methods, the first dislocation plane has the inclination angle less than about 45 degree.
In the above-mentioned methods, in the described first annealing, the described first strain coating is exposed to ultraviolet light.
In the above-mentioned methods, neighbouring MOSFET etching shallow trenches isolation (STI) area is further included to be formed described in adjoining
The groove of MOSFET, wherein, the STI region has the recessed top surface below the groove, and wherein, described first
The pinching line of dislocation plane is higher than the recessed top surface of the STI region.
According to another aspect of the invention, a kind of device is additionally provided, including：Metal oxide semiconductor field effect transistor
Manage (MOSFET), including：Semiconductor region；Gate electrode, including the part above the semiconductor region；And first dislocation put down
Face, adjacent to the gate electrode and in the semiconductor region, wherein, the first dislocation plane has less than about 65 degree
Inclination angle.
In the devices set out in the foregoing, the inclination angle is less than about 45 degree.
In the devices set out in the foregoing, further include the neighbouring gate electrode and the second dislocation in the semiconductor region is put down
Face, wherein, the first dislocation plane and the second dislocation plane are not parallel each other.
In the devices set out in the foregoing, further include the neighbouring gate electrode and the second dislocation in the semiconductor region is put down
Face, wherein, the first dislocation plane and the second dislocation plane are connected to each other.
Brief description of the drawings
When reading in conjunction with the accompanying drawings, various aspects of the invention are best understood from described in detail below.Should
Note that the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, various parts
Size arbitrarily can increase or reduce.
Fig. 1 shows the top view of mos field effect transistor (MOSFET)；
Fig. 2 to Figure 11 is the sectional view in the interstage of manufacture according to the MOSFET of each embodiment；
Figure 12 is technological process according to the embodiment；And
Figure 13 to Figure 21 C is the sectional view in the interstage of manufacture according to the MOSFET of alternative embodiment.
Embodiment
Disclosure below provides the different embodiments or example of many different characteristics for being used for realization the present invention.Below
The instantiation for describing component and arrangement is of the invention to simplify.Certainly, these are only example, and are not intended to be limited to this hair
It is bright.For example, in the following description, above second component or upper formation first component can include first component and second
The embodiment that part is formed in a manner of directly contacting, and can also be included between first component and second component and can be formed
Extra component, so that the embodiment that first component and second component can be not directly contacted with.In addition, the present invention can be each
Repeat reference numerals and/or character in a example.The repetition is that for purposes of simplicity and clarity, and itself does not indicate institute
Relation between each embodiment discussed and/or configuration.
Moreover, can use herein " in ... lower section ", " ... below ", " lower part ", " ... on ", " top " etc.
Spatially relative term is to be easy to describe an element or component as depicted and another (or other) element or component
Relation.In addition to the orientation shown in figure, spatially relative term is intended to include the different azimuth of device in use or operation.Dress
Putting can otherwise orient and (be rotated by 90 ° or in other orientation), and spatial relative descriptor as used herein can be with
Similarly make corresponding explanation.
According to each embodiment, there is provided mos field effect transistor (MOSFET) and its formation side
Method.Show to form the interstage of MOSFET.Discuss the change and operation of embodiment.Through each view and illustrative reality
Example is applied, identical label is used to indicate identical element.
Fig. 1 shows the top view of the N-shaped MOSFET 100 according to each embodiment.MOSFET100 is three grids
MOSFET (sometimes referred to as FinFET), and including at least one and possible multiple semiconductor fins 20.Semiconductor fin 20 is to each other
Separate, there is insulation layer (can be shallow trench isolation (STI) area) 24 between semiconductor fin 20.Formed in semiconductor fin 20
Gate electrode 22 and gate electrode 22 cover the top surface of semiconductor fin 20.Side wall of the gate electrode 22 also around semiconductor fin 20.It is block
Active area 26 is located on the opposite end of semiconductor fin 20, wherein block active area 26A interconnecting semiconductors fin 20 is in gate electrode 22
Left side on part.Block 20 part on the right side of gate electrode 22 of active area 26B interconnecting semiconductors fin.
Fig. 2 to Figure 11 is the sectional view in interstages of the N-shaped MOSFET 100 in accordance with some embodiments in manufacture.Section
Figure is intercepted from the level-crossing line 2-2 in Fig. 1.With reference to Fig. 2, there is provided Semiconductor substrate 102, and STI region 24 is formed as
Extended to from the top surface of Semiconductor substrate 102 in Semiconductor substrate 102.Semiconductor substrate 102 can be silicon substrate, SiGe lining
Bottom or other semi-conducting materials that such as III-V compound semiconductor material can be included.In gate electrode 22 and gate electrode 25
Side wall on be formed selectively master shift distance piece 30.Master shift distance piece 30 can be by the dielectric material shape of such as silica
Into, but other dielectric materials of silicon nitride, silicon oxynitride etc. can also be used.STI region 24 includes groove 36, by making
The adjacent semiconductor substrate 102 of STI region 24 is partially recessed to form groove 36.Therefore, STI region 24 has top surface 24A and recessed
Into top surface 24B, wherein recessed top surface 24B is less than top surface 24A.Therefore, substrate 102 above recessed top surface 24B
Part form semiconductor fin 20 (refer to Fig. 1) and bulk semiconductor area 26A and 26B (Fig. 1).In certain embodiments, it is recessed
Groove 36 can surround semiconductor fin 20 and bulk semiconductor area 26A and 26B.Therefore, channel region is formed in the semiconductor substrate 102
23, and channel region 23 is located at below gate electrode 22.
As indicated by arrows 32, the first pre-amorphous injection (PAI, otherwise referred to as pre- amorphous note is then implemented
Enter).In certain embodiments, silicon or germanium are injected.In other embodiments, the inert gas of such as neon, argon, xenon and radon is injected.
It is pre-amorphous to inject the lattice structure for destroying Semiconductor substrate 102.When injecting germanium, Implantation Energy can in about 25keV and
Between about 40keV, and implantation dosage can be in about 1E14/cm2About 1E15/cm2Between.In some exemplary embodiments,
It can implement to inject when Semiconductor substrate 102 is at a temperature of between about -60 DEG C of -100 DEG C of peace treaties.
After the first PAI, (exposed tops include semiconductor fin 20 and block half to the exposed tops of Semiconductor substrate 102
Conductor region 26A and 26B) due to PAI it is transformed into amorphous state.Therefore PAI areas 40 are formed.In embodiment, note is vertically implemented
Enter.In an alternative embodiment, can implement to inject with inclined angle alpha, inclined angle alpha can be less than about 20 degree.Such as the institute of dotted arrow 32
Show, when implementing to tilt injection, it is possible to implement two inclinations are injected and two tilt injection and are inclined to opposite direction.
The bottom surface 40A in PAI areas 40 can ensure dislocation pinching line 48 (Fig. 3) higher than the recessed top surface 24B of STI region 24
Higher than recessed STI top surfaces 24B.When implementing vertical injection and when no offset spacer 30 is formed, the inward flange in PAI areas 40
It can be substantially aligned with the edge of gate electrode 22 (so that distance S1 is substantially equal to zero nanometer).Alternatively, PAI areas 40 can be with
Hithermost edge spaced apart S1 corresponding with gate electrode 22, distance S1 are nonzero value.On the other hand, when implementation tilts
During injection, PAI areas 40 may or may not be extended to below gate electrode 22.
Fig. 3 shows the formation of the first strain coating 42.Silicon nitride, nitridation can be included by straining the material of coating 42
Titanium, nitrogen oxides, oxide, SiGe, SiC, SiON and combinations thereof.Straining coating 42 can have inherent stretching should
Power.Formation process is adjusted with by stress changes to desired value.In certain embodiments, strain coating 42 includes individual layer.At it
In his embodiment, strain coating 42 can include the laminar structure with multilayer.
According to some embodiments, for being formed in the process gas of strain coating 42, not comprising there is hydrogen.For example,
When strain coating 42 includes silicon nitride, process gas can include silane (SiH4) (or SiCl4) and ammonia (NH3), without adding
Add or do not add hydrogen substantially.In the strain coating 42 of generation, do not include or do not include hydrogen substantially.
For example, then implement annealing using rapid thermal annealing (RTA), thermal spike RTA annealing or other method for annealing.Implementing
In example, for example, real using spike RTA (wherein annealing temperature lasts about 3 milliseconds to 5 seconds between about 950 DEG C and about 1050 DEG C)
Apply annealing.In an alternative embodiment, it is, for example, possible to use long-time RTA (wherein annealing temperature about 550 DEG C and about 950 DEG C it
Between, the duration is between about 10 seconds and about 5 minutes) implement annealing.Due to annealing, if Fig. 2 Zhong PAI areas 40 are by from strain
The stress recrystallization for the storage that coating 42 obtains.Therefore, Semiconductor substrate 102 can be to the raceway groove of the MOSFET 100 of generation
Area 23 applies tensile stress, so as to improve the driving current of MOSFET 100.
Due to annealing, dislocation plane 46 is formed.Although figure 3 illustrates section be illustrated as line, dislocation is put down
Face 46 is the plane extended on the longitudinal direction (and Y-direction in Fig. 1) of gate electrode 22.The bottom point 48 of dislocation plane 46 can
With the recessed top surface 24B higher than STI region 24.This can minimize the influence of STI region 24, and STI region 24 is adversely to raceway groove
23 apply compression stress.Bottom point 48 forms in Y-direction in Fig. 1 the line extended, and is therefore hereinafter referred to as pinching line
48。
According to some embodiments, dislocation plane 46 and the horizontal plane parallel with the main top surface of substrate 102 or main bottom surface are formed
Angle beta.Angle beta can be in the range of about 45 degree to about 90 degree, and can be between about 50 degree and about 60 degree.According to some examples
Property embodiment, angle beta is about 55 degree.
Next, with reference to Fig. 4, implement etching step, and remove the horizontal component of strain coating 42, and retain strain
Some vertical components of coating 42.The remainder of strain coating 42 is hereinafter referred to as offset spacer 49.Between offset
Spacing body 49 is located on the side wall of master shift sidewall spacer 30, or (if do not formed main inclined on the side wall of gate electrode 22
Move sidewall spacer 30).It should be noted that the remainder of strain coating 42 can also include being located at substrate 102 and STI region 24
Side wall on part, and these parts are not shown.
Fig. 5 shows the formation in the 2nd PAI areas 50 by the 2nd PAI injections, shows that PAI injects using arrow 52.With
Offset spacer 49 stops that the member of some injections usually implements the 2nd PAI injections.Therefore, the inward flange 50A in PAI areas 50 is than corresponding
PAI areas 40 (Fig. 2) further from corresponding gate electrode 22.In other words, the inward flange in PAI areas 50 and corresponding gate electrode 22 be most
The level interval S2 of spacing between near edge is more than the level interval S1 in Fig. 2.In addition, each dislocation plane 46 is at least
Bottom 46A is not in the PAI areas 50 newly formed.This can be realized by making PAI areas 50 be shallower than pinching line 48.Alternatively,
As shown in figure 5, this can also be by being spaced apart in the 2nd PAI using 49 Yi Jiang PAI areas 50 of offset spacer with gate electrode 22
To realize.Since PAI areas 50 are amorphous area, so the crystal structure quilt in the part of the dislocation plane 46 overlapping with PAI areas 50
Destroy.The 2nd PAI areas, or the inclination using the inclined angle alpha (Fig. 2) for being equal to or less than the first PAI injections can be vertically formed
Form to overturning angle the 2nd PAI areas.This may insure that the dislocation plane 56 (Fig. 6) that subsequently forms is not overlapping with dislocation plane 46.
The element of injection can be selected from similar available element workable for the first PAI.When injecting germanium, Implantation Energy can be about
Between 15keV and about 50keV, and implantation dosage can be in about 1E14/cm2About 1E15/cm2Between.Work as Semiconductor substrate
102 can implement to inject when being at a temperature of between about -60 DEG C of -100 DEG C of peace treaties.
Fig. 6 shows the formation of the second strain coating 54.The candidate material and forming method of second strain coating 54
Can be essentially identical with the candidate material and forming method for forming strain coating 42.Forming the second strain coating 54
Afterwards, the second annealing is implemented.Similarly, the second annealing can anneal essentially identical with first shown in Fig. 3.Move back due to second
Fire, occurs to recrystallize and produce dislocation plane 56 in PAI areas 50.Simultaneously as the crystalline substance in the bottom 46A of dislocation plane 46
Body structure is not destroyed by the 2nd PAI, and the crystal structure in the part of the destruction of dislocation plane 46 is given birth to again in PAI areas 50
Long, it is again transformed into crystal region.In the structure of the generation of such as Fig. 6, two dislocation planes 46 and 56 coexist and put down each other
OK, its Dislocations plane 56 is located at the outside of corresponding dislocation plane 46.In addition, the pinching line of corresponding dislocation plane 46 and 56
48 and 58 are higher than the recessed STI top surfaces 24B of STI region 24.In other words, pinching line 48 and 58 can be higher than the bottom of corresponding fin 20
Portion, fin bottom is with the recessed STI top surfaces 24B of STI region 24 at identical horizontal plane.
Next, as shown in fig. 7, implementation etching step, so that removing the horizontal component of strain coating 54, and is answered
Some vertical components for becoming coating 54 are stayed in offset spacer 49 to form offset spacer 59.It is as shown in Figure 8 with
In processing step afterwards, implement the 3rd PAI 62 to form the 3rd PAI areas 60.3rd PAI can be with the 2nd PAI bases in Fig. 5
This is identical.Equally, each of dislocation plane area 46 and 56 is respectively provided with the overlapping bottom in Bu Yu PAI areas 60, and in the 3rd PAI
Without the crystal structure in the bottom for destroying dislocation plane 46 and 56 during 62.The process detail of 3rd PAI 62 can be with second
PAI 52 (Fig. 5) is essentially identical.Due to the addition of offset spacer 49 and 59, PAI areas 60 are than PAI area 50 (Fig. 5) further from grid
Electrode 22, wherein, interval S 3 is more than interval S 1 and interval S 2 respectively as shown in Figure 2 and Figure 5.
With reference to Fig. 9, the 3rd strain coating 64 is formed, then implements the 3rd annealing steps with dislocation plane 46 and 56
Outside forms dislocation plane 66.In addition, dislocation plane 46,56 and 66 are parallel to each other.The pinching line 68 of dislocation plane 66 can be high
In the recessed top surface 24B of STI region 24.
The formation of dislocation plane 46,56 and 66 can cause the increasing of the tensile stress in the channel region 23 of MOSFET 100
Greatly.The formation of multiple dislocation planes can cause tensile stress further to increase.It is simulated to study channel stress and MOS
Relation between the quantity of dislocation plane in device.The result shows that with two dislocation planes (in each of gate electrode 22
Side) the channel stress of MOSFET be 1.5 times of channel stress of the MOSFET with dislocation plane, and with three
The channel stress of the MOSFET of dislocation plane is 1.7 times of the channel stress of the MOSFET with two dislocation planes.Therefore, shape
The channel stress in corresponding MOSFET can effectively be increased into multiple dislocation planes.
Fig. 2 to Fig. 9 shows the formation of the MOSFET with three dislocation planes.In an alternative embodiment, MOSFET can
With with two dislocation planes on every side of gate electrode or more than three dislocation planes.
With reference to Figure 10, strain coating 64 and offset spacer 49 and 59 are removed.For example, when strain coating 64 and
When offset spacer 49 and 59 includes silicon nitride, H can be used3PO4Implement the removal of offset spacer 49 and 59.Pass through injection
Also form source/drain regions 110.Then epitaxial growth can be implemented to grow extension half on the top surface of source/drain regions 110
Conductor layer 70.In embodiment, epitaxial semiconductor layer 70 includes silicon, silicon phosphorus, silicon-carbon phosphorus etc..
Next, as shown in figure 11, implement silication to form silicide area 72.In embodiment, consumed in silication
The top of epitaxial semiconductor layer 70, and do not consume the bottom of epitaxial semiconductor layer 70 in silication.Therefore, the silicide of generation
The top surface of channel region 23 of the bottom surface in area 72 higher than MOSFET 100.Analog result is it has been shown that when the bottom surface of silicide area 72 is high
When the top surface of channel region 23, the driving current of MOSFET 100 can be improved, and when the bottom surface of silicide area is higher, should
Improve increase.
Figure 12 shows the exemplary process flow for forming dislocation.First, master shift distance piece (step is formed
120).Step 120 in Figure 12 can correspond to the step in Fig. 2.Then first is implemented by step 122,124 and 126
Mistake is formed.In step 122, implement pre- amorphous to inject, then implement as being used to be formed answering for dislocation in step 124 and 126
Power film deposits and annealing.Step 122,124 and 126 can correspond to the step of Fig. 2 is shown into Fig. 4.Next, etching stress
Film is to expand the size of offset spacer.The step can correspond to the etching step in Fig. 4.Pass through step 130,132,134
Formed with 136 the second dislocations of implementation.In step 130, implement extra pre- amorphous injection, then implement to be used to form dislocation
Extra stress film deposition and extra annealing (step 132 and 134).In step 136, extra stress film is etched to expand
The size of offset spacer.Step 130,132,134 and 136 can correspond to the step of Fig. 5 is shown into Fig. 7.Step 130,
132nd, 134 and 136 can be repeated one or more times.For example, the step of being shown in Fig. 8 and Fig. 9 shows step 130,132,134
With 136 exemplary repetition.Step 138 shows the removal of stress film and selectable master shift sidewall spacer.Step 138
It can correspond to the illustrative steps shown in Figure 10.
Figure 13 to Figure 21 C shows the sectional view in the interstage of formation according to the MOSFET of alternative embodiment.Unless
State otherwise, the material of component in these embodiments and forming method and their same components are essentially identical, identical
Identical reference number in the embodiment that component is shown by Fig. 1 into Figure 12 represents.Therefore, shown in Fig. 1 into Figure 12
The formation process of component and the details of material on being shown in Figure 13 to Figure 21 C can be found in the discussion of embodiment.
The initial configuration and forming step of these embodiments are with shown in Figure 2 essentially identical, wherein forming PAI areas 40.
Next, Figure 13 shows the formation of the first strain coating 42.Silicon nitride, nitridation can be included by straining the material of coating 42
Titanium, nitrogen oxides, oxide, SiGe, SiC, SiON and combinations thereof.In addition to other materials, coating 42 is strained
Including hydrogen.For example, strain coating 42 can be hydrogeneous silicon nitride, hydrogeneous titanium nitride, containing silicon hydroxide, hydrogeneous silicon oxynitride,
Hydrogeneous SiGe, hydrogeneous SiC, hydrogeneous SiON, combinations thereof or their multilayer.
In the formation of hydrogeneous strain coating 42, in addition to other process gas, process gas includes hydrogen (H2)。
For example, when strain coating 42 includes silicon nitride, process gas can include silane (SiH4) (or SiCl4), ammonia (NH3) and
Hydrogen.Depositing temperature can be between about 400 DEG C and about 500 DEG C.Process gas has the pressure of about 1 support to about 15 supports.Therefore,
The strain coating 42 of generation includes hydrogen.In some exemplary embodiments, in the deposition of strain coating 42, hydrogen
Flow velocity is greater than about 100sccm to improve the hydrogen concentration in hydrogeneous strain coating 42.In an alternative embodiment, it is initially formed strain
Coating 42.It can be hydrogen-free or hydrogeneous to strain coating 42.After strain coating 42 is formed, implement extra expansion
Day labor skill (more) hydrogen is attached to strain coating 42 and increases the hydrogen concentration strained in coating 42 with further.
In the hydrogeneous strain coating 42 produced, hydrogen concentration can be greater than about 1E19/cm3, greater than about 1E20/cm3Or greater than about 1E19/
cm3。
For example, then implement annealing using RTA, thermal spike RTA annealing or other method for annealing.Annealing temperature can be about
Between 400 DEG C and about 500 DEG C.Such as O can used2、N2、H2Deng process gas environment in implement annealing.Process gas
Pressure with about 1 support to about 15 supports.In addition, in annealing, hydrogeneous strain coating 42 is exposed to ultraviolet (UV)) light.Due to
Annealing, Fig. 2 Zhong PAI areas 40 are recrystallized by the stress of the storage obtained from strain coating 42.Therefore, Semiconductor substrate
102 can apply tensile stress to the channel region 23 of the MOSFET 100 of generation, so as to improve the driving current of MOSFET 100.
Due to annealing, dislocation plane 46 is formed.According to some embodiments, due to the formation of hydrogeneous strain coating 42, institute
With in annealing, hydrogen strains degasification in coating 42 from hydrogeneous.For example, UV light contributes to degasification.This causes in different knots
The growth rate of solid phase epitaxial phase regrowth (SPER) on Jinping face is different from the growth rate in the embodiment in Fig. 3.Example
Such as, in the embodiment illustrated in figure 3, the growth rate in (100) plane of Semiconductor substrate 102 can be more than semiconductor and serve as a contrast
Growth rate in (110) plane at bottom 102, this causes, and the angle beta (Fig. 3) of dislocation plane 46 is bigger, and angle beta can be about 55
Degree.Figure 13 illustrates embodiment in, for example, the growth rate in (100) plane of Semiconductor substrate 102 is decreased to low
Growth rate in (110) plane of Semiconductor substrate 102,
This causes the angle γ (Figure 13) of dislocation plane 46 smaller (being less than about 65 degree).In certain embodiments, angle γ is small
In about 45 degree and in the range of 0 degree to about 45 degree.Angle γ can also be in the range of from about 20 degree to about 40 degree.At some
In exemplary embodiment, angle γ is about 35 degree.Advantageously, small angle γ causes the stress for being applied to channel region 23 higher.Therefore, the phase
Hope the angle γ for reducing dislocation plane 46.
The bottom point 48 of dislocation plane can be higher than the recessed top surface 24B of STI region 24.This can make the influence of STI region 24
Minimize, it adversely applies compression stress to raceway groove 23.Bottom point 48 forms in Y-direction in Fig. 1 the line extended, and because
This is hereinafter referred to as pinching line 48.
Next, implementing etching step, and the horizontal component of strain coating 42 is removed, and retain strain coating 42
Some vertical components to be formed such as the offset spacer 49 in Figure 14.Equally, offset spacer 49 is between master shift side wall
On the side wall of spacing body 30, or on the side wall of gate electrode 22 (if not forming master shift sidewall spacer 30).It should note
Meaning, the remainder of strain coating 42 can also be located on substrate 102 and the side wall of STI region 24 including (or can not include)
Part, and these parts are not shown.
Figure 15 shows the formation in the 2nd PAI areas 50 by the 2nd PAI injections, shows that the PAI injects using arrow 52.
Stop that the member of some injections usually implements the 2nd PAI injections with offset spacer 49.Therefore, the inward flange 50A in PAI areas 50 compares phase
Ying PAI areas 40 (Fig. 2) are further from corresponding gate electrode 22.In other words, for PAI areas 50 inward flange and gate electrode 22 it is corresponding
Nearest edge between spacing level interval S2 (Figure 15) be more than Fig. 2 in level interval S1.In addition, each dislocation is put down
At least bottom 46A in face 46 is not in the PAI areas 50 newly formed.This can be by making PAI areas 50 be shallower than pinching line 48 come real
It is existing.Alternatively, as shown in figure 15, this in the 2nd PAI by using between 49 Yi Jiang PAI areas 50 of offset spacer and gate electrode 22
Separate to realize.Since PAI areas 50 are amorphous area, so the crystal in dislocation plane 46 in the overlapping part in Yu PAI areas 50
It is destructurized.Injection technology can be similar to the injection technology with reference to Fig. 5 discussion.
Figure 16 A show the formation of the second strain coating 54.The candidate material and formation process for straining coating 54 can
With essentially identical with the candidate material and formation process for forming strain coating 42.According to some embodiments, strain covering
Layer 54 includes hydrogen, and hydrogen can be incorporated into strain coating 54 during or after strain coating 54 is formed.In optional reality
Apply in example, strain coating 54 is not hydrogeneous or is substantially free of hydrogen.
After strain coating 54 is formed, implement the second annealing.Second annealing can use with figure 13 illustrates
The essentially identical process conditions of first process conditions that use of annealing, or the technique bar that the with being shown in Figure 13 first annealing uses
The different process conditions of part.Due to the second annealing, recrystallized in PAI areas 50, and produce dislocation plane 56.Meanwhile
Since the bottom 46A (Figure 15) of dislocation plane 46 is not destroyed by the 2nd PAI, the part of the destruction of dislocation plane 46 is in PAI areas
Regrow in 50, it is again transformed into crystal region.In such as structure of the generation of Figure 16 A, dislocation plane 46 and 56 coexists simultaneously
And can be parallel to each other, its Dislocations plane 56 is located at the outside of corresponding dislocation plane 46.In addition, corresponding dislocation plane 46
Pinching line 48 and 58 with 56 is higher than the recessed STI top surfaces 24B of STI region 24.In other words, pinching line 48 and 58 can be higher than phase
The bottom for the fin 20 answered, the bottom of fin 20 is with the recessed STI top surfaces 24B of STI region 24 at identical horizontal plane.
It is some embodiments of hydrogeneous layer according to wherein strain coating 54, the dislocation plane 56 of generation has inclination angle
γ, the angle γ of dislocation plane 56 can be identical or different with the angle γ of dislocation plane 46.Therefore, dislocation plane 46 can with or can be with
It is not parallel with corresponding dislocation plane 56.In an alternative embodiment, as shown in fig 16b, dislocation plane 56, which can have, is more than angle
The angle θ of γ.In certain embodiments, angle θ is equal to such as the angle beta in Fig. 3.Can be not hydrogeneous by making to strain coating 54 accordingly
Or hydrogen is substantially free of to realize the difference between angle θ and angle γ.
Figure 16 C show the sectional view of alternative embodiment, and the inclination angle of its Dislocations plane 56 is less than dislocation plane 46
Inclination angle.According to some exemplary embodiments, the inclination angle of dislocation plane 56 is γ, and the inclination angle of dislocation plane 46 is β.
In these embodiments, dislocation plane 56 may or may not contact dislocation plane 46.
Next, as shown in figure 17, implementing etching step, so as to remove the horizontal component of strain coating 54, and strain
Some vertical components of coating 54 are stayed in offset spacer 49 to form offset spacer 59.As shown in figure 18, subsequent
Processing step in, implement the 3rd PAI 62 to form the 3rd PAI areas 60.3rd PAI can be basic with the 2nd PAI in Figure 15
It is identical.Equally, each dislocation plane area 46 and 56 has the overlapping bottom in Bu Yu PAI areas 60, and during the 3rd PAI 62
The crystal structure of the bottom of dislocation plane area 46 and 56 is not destroyed.The process detail of 3rd PAI 62 can be with the 2nd PAI 52
(Figure 15) is essentially identical.
Due to the addition of offset spacer 49 and 59, PAI areas 60 than PAI area 50 (Fig. 5) further from gate electrode 22, wherein,
Interval S 3 is more than the interval S 1 and interval S 2 as shown in Fig. 2 and Figure 15 respectively.
With reference to Figure 19, the 3rd strain coating 64 is formed, then implements the 3rd annealing steps with dislocation plane 46 and 56
Outside form dislocation plane 66.In addition, dislocation plane 46,56 and 66 can be parallel to each other or can not be parallel to each other.Dislocation
The pinching line 68 of plane 66 can be higher than the recessed top surface 24B of STI region 24.According to some embodiments, strain coating 64 is
Hydrogeneous.In an alternative embodiment, strain coating 64 is free from hydrogen.As a result, the angle of strain coating 64 can be about
In the range of 45 degree to 90 degree or in the range of 0 degree to about 45 degree.
With reference to Figure 20, strain coating 64 and offset spacer 49 and 59 are removed.Then can implement epitaxial growth with
Epitaxial semiconductor layer 70 is grown on the top surface of source/drain regions 110.Source/drain regions 110 can also be formed by injection.
Dislocation plane 46,56 and 66 can be grown into epitaxial semiconductor layer 70.Epitaxial semiconductor layer 70 can include silicon, silicon phosphorus, silicon
Carbon phosphorus etc..
Next, as shown in Figure 21 A, Figure 21 B and Figure 21 C, implement silication to form silicide area 72.Silicification technics and phase
Silicification technics in embodiment and details in the details and Figure 11 answered is essentially identical, and does not repeat herein.
Figure 21 A, Figure 21 B and Figure 21 C show each embodiment of the present invention.Each dislocation plane can have their own
Inclination angle (such as β, γ and θ), inclination angle can be identical or different with the inclination angle of other dislocation planes.Adjusting can be passed through
It is corresponding to strain the hydrogen concentration in coating to realize different angles, and hydrogen concentration is higher, and inclination angle is smaller.In addition, hydrogen
Amount needs to reach a certain amount of to reduce inclination angle.For example, Figure 21 A show that dislocation plane 46,56 and 66 has identical inclination
Angle γ.In an alternative embodiment, as illustrated in fig. 21b, dislocation plane 46 has the inclination angle than exterior dislocation plane 56 and 66
(such as β) less inclination angle (such as γ).In other alternative embodiment, as shown in fig. 21 c, dislocation plane 46 have than
The big inclination angle (such as β) in the inclination angle (such as γ) of exterior dislocation plane 56 and 66.According to some embodiments, such as Figure 21 C
Shown, exterior dislocation plane (such as dislocation plane 56 or 66) can contact dislocation plane (such as dislocation plane 46 of inside
Or 56).In other embodiments, although exterior dislocation plane has the inclination angle than internal dislocation plane smaller,
Exterior dislocation plane can not be with internal dislocation plane contact.
The embodiment of the present invention has some favorable characteristics.By forming multiple dislocation planes, the ditch of MOSFET is added
Strain in road area.Since strain coating also serves as the distance piece of the position for limiting dislocation plane, so according to this hair
The manufacture cost of the technique of bright embodiment is low.In addition, by the way that hydrogen is attached in strain coating, dislocation plane is reduced
Inclination angle, so as to cause the further increase of the strain for the channel region for being applied to MOSFET.
According to some embodiments of the present invention, a kind of method includes forming MOSFET.This method includes implementing injection with shape
Into the PAI areas of the gate electrode of neighbouring MOSFET；Strain coating is formed above PAI areas；And to strain coating and PAI areas
Implement annealing to form dislocation plane.Since annealing forms dislocation plane, the inclination angle of dislocation plane is less than about 65 degree.
According to an alternative embodiment of the invention, a kind of method includes implementing injection to form the gate electrode of neighbouring MOSFET
PAI areas and the formation strain coating above PAI areas, wherein in strain coating is formed, are used as process gas by hydrogen.
This method is further included implements annealing to form dislocation plane to strain coating and PAI areas.Since annealing forms dislocation plane.
Other alternative embodiment according to the present invention, MOSFET include semiconductor region including above semiconductor regions
Part gate electrode and neighbouring gate electrode and the dislocation plane in semiconductor region.Dislocation plane, which has, is less than about 65
The inclination angle of degree.
It foregoing has outlined the feature of some embodiments so that each of the present invention may be better understood in those skilled in the art
Aspect.It should be appreciated by those skilled in the art that they can easily be used for using based on the present invention to design or change
Implement the purpose identical with embodiment defined herein and/or realize other techniques and structure of identical advantage.Art technology
Personnel it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from the present invention
In the case of spirit and scope, they can make a variety of changes, replace and change herein.
Claims (18)
1. a kind of method for forming mos field effect transistor, including：
Mos field effect transistor MOSFET is formed, including：
Implement the first injection to form the first pre-amorphous injection PAI areas of the gate electrode of the neighbouring MOSFET；
The first strain coating is formed above the first PAI areas；And
Implement the first annealing to the described first strain coating and the first PAI areas to form the first dislocation plane, wherein, by
The first dislocation plane is formed in the described first annealing, the inclination angle of the first dislocation plane is less than 65 degree；
Adjacent to the MOSFET etching shallow trenches isolation STI area to form the groove of the adjacent MOSFET, wherein, the STI
Area has the recessed top surface below groove, and the pinching line of the first dislocation plane is recessed higher than the STI region
Into top surface.
2. the method according to claim 1 for forming mos field effect transistor, wherein, forming institute
State in the first strain coating, addition hydrogen (H2) it is used as process gas.
3. the method according to claim 1 for forming mos field effect transistor, wherein, described the
In one annealing, the described first strain coating is exposed to ultraviolet light.
4. the method according to claim 1 for forming mos field effect transistor, further includes to form neighbour
Second dislocation plane of the gate electrode of the nearly MOSFET, wherein, the first dislocation plane and the second dislocation plane position
In the same side of the gate electrode, and extend in the source/drain regions of the MOSFET.
5. the method according to claim 4 for forming mos field effect transistor, wherein, forming institute
State the formation that the first dislocation plane implements the second dislocation plane afterwards, and the first dislocation plane and the second
Wrong plane is parallel to each other.
6. the method according to claim 4 for forming mos field effect transistor, wherein, forming institute
State the formation that the first dislocation plane implements the second dislocation plane afterwards, and the first dislocation plane and the second
Wrong plane is not parallel each other.
7. the method according to claim 4 for forming mos field effect transistor, wherein, described in formation
Second dislocation plane includes：
The first strain coating is etched to remove the horizontal component of the first strain coating, wherein, the neighbouring grid
The vertical component of the first strain coating of electrode is not etched to form offset spacer；
After the etching, the second injection is implemented to form the 2nd PAI areas of the neighbouring gate electrode；
The second strain coating is formed above the 2nd PAI areas；And
Second annealing is implemented to the described second strain coating and the 2nd PAI areas, wherein, since the described second annealing is formed
The two dislocations plane.
8. the method according to claim 1 for forming mos field effect transistor, wherein, described first
The inclination angle of dislocation plane is less than 45 degree.
9. the method according to claim 1 for forming mos field effect transistor, further includes：
After the first dislocation plane is formed, implement epitaxial growth with square on the source/drain regions of the MOSFET
Into epitaxial semiconductor layer；And
Implement silication to form silicide area on the source/drain regions, wherein, the extension is consumed in silication and is partly led
The top of body layer, and do not consume the bottom of the epitaxial semiconductor layer in silication.
10. a kind of method for forming mos field effect transistor, including：
Mos field effect transistor MOSFET is formed, including：
Implement the first injection to form the first pre-amorphous injection PAI areas of the gate electrode of the neighbouring MOSFET；
The first strain coating is formed above the first PAI areas, uses hydrogen in the first strain coating is formed
Make process gas；And
Implement the first annealing to the described first strain coating and the first PAI areas to form the first dislocation plane, wherein, by
The first dislocation plane is formed in the described first annealing,
Adjacent to the MOSFET etching shallow trenches isolation STI area to form the groove of the adjacent MOSFET, wherein, the STI
Area has the recessed top surface below the groove, and wherein, the pinching line of the first dislocation plane is higher than described
The recessed top surface of STI region.
11. the method according to claim 10 for forming mos field effect transistor, further includes：
Implement the second injection to form the 2nd PAI areas of the neighbouring gate electrode；
The second strain coating is formed above the 2nd PAI areas；And
Implement the second annealing to the described second strain coating and the 2nd PAI areas to form the second dislocation plane, wherein, by
The second dislocation plane is formed in the described second annealing, and the second dislocation plane is more farther than the first dislocation plane
From the channel region of the MOSFET.
12. the method according to claim 11 for forming mos field effect transistor, wherein, formed
In the second strain coating, hydrogen (H is added2) it is used as process gas.
13. the method according to claim 10 for forming mos field effect transistor, wherein, described the
One dislocation plane has the inclination angle less than 45 degree.
14. the method according to claim 10 for forming mos field effect transistor, wherein, described
In first annealing, the described first strain coating is exposed to ultraviolet light.
15. a kind of MOSFET device, including：
Mos field effect transistor (MOSFET), including：
Semiconductor region；
Gate electrode, including the part above the semiconductor region；And
First dislocation plane, adjacent to the gate electrode and in the semiconductor region, wherein, the first dislocation plane tool
There is the inclination angle less than 65 degree,
Shallow trench isolation STI area, including groove, wherein, the STI region has the recessed top surface below the groove,
And wherein, the pinching line of the first dislocation plane is higher than the recessed top surface of the STI region.
16. MOSFET device according to claim 15, wherein, the inclination angle is small
In 45 degree.
17. MOSFET device according to claim 15, further includes the neighbouring grid
Electrode and the second dislocation plane in the semiconductor region, wherein, the first dislocation plane and second dislocation
Plane is not parallel each other.
18. MOSFET device according to claim 15, further includes the neighbouring grid
Electrode and the second dislocation plane in the semiconductor region, wherein, the first dislocation plane and second dislocation
Plane is connected to each other.
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| US14/455,102 | 2014-08-08 | ||
| US14/455,102 US9299838B2 (en) | 2011-10-24 | 2014-08-08 | MOSFETs with multiple dislocation planes |
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|---|---|---|---|---|
| CN1790734A (en) * | 2004-12-02 | 2006-06-21 | 台湾积体电路制造股份有限公司 | Semiconductor device and methods of producing the same |
| CN102468164A (en) * | 2010-10-29 | 2012-05-23 | 中国科学院微电子研究所 | Transistor and manufacture method thereof |
| CN103066124A (en) * | 2011-10-20 | 2013-04-24 | 台湾积体电路制造股份有限公司 | Semiconductor device with multiple stress structures and method of forming the same |
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| US20030227057A1 (en) * | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
| US8779477B2 (en) * | 2008-08-14 | 2014-07-15 | Intel Corporation | Enhanced dislocation stress transistor |
| US8058134B2 (en) * | 2009-02-19 | 2011-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Junction profile engineering using staged thermal annealing |
| US8809918B2 (en) * | 2011-10-24 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOSFETs with multiple dislocation planes |
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| CN102468164A (en) * | 2010-10-29 | 2012-05-23 | 中国科学院微电子研究所 | Transistor and manufacture method thereof |
| CN103066124A (en) * | 2011-10-20 | 2013-04-24 | 台湾积体电路制造股份有限公司 | Semiconductor device with multiple stress structures and method of forming the same |
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| TW201607026A (en) | 2016-02-16 |
| TWI559527B (en) | 2016-11-21 |
| CN105374873A (en) | 2016-03-02 |
| KR101659176B1 (en) | 2016-09-22 |
| DE102014119643A1 (en) | 2016-02-11 |
| KR20160018317A (en) | 2016-02-17 |
| DE102014119643B4 (en) | 2018-01-25 |
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