CN105374873A - Mosfets with multiple dislocation planes - Google Patents

Mosfets with multiple dislocation planes Download PDF

Info

Publication number
CN105374873A
CN105374873A CN201410770305.0A CN201410770305A CN105374873A CN 105374873 A CN105374873 A CN 105374873A CN 201410770305 A CN201410770305 A CN 201410770305A CN 105374873 A CN105374873 A CN 105374873A
Authority
CN
China
Prior art keywords
dislocation plane
cover layer
dislocation
plane
pai
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410770305.0A
Other languages
Chinese (zh)
Other versions
CN105374873B (en
Inventor
吕伟元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/455,102 external-priority patent/US9299838B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN105374873A publication Critical patent/CN105374873A/en
Application granted granted Critical
Publication of CN105374873B publication Critical patent/CN105374873B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
    • Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.

Description

There is the MOSFET of multiple dislocation plane
The cross reference of related application
The application is the title submitted on October 24th, 2011 is the part continuation application of No. the 13/280th, 094, the U.S. Patent application of " MOSFET with multiple dislocation plane ", and its full content is hereby expressly incorporated by reference.
Technical field
The present invention relates to the MOSFET with multiple dislocation planes.
Background technology
In order to improve the performance of metal-oxide semiconductor (MOS) (MOS) device, can by introduced stress to the channel region of MOS device to improve carrier mobility.Usually, be desirably on source electrode to drain directions and introduce tensile stress in the channel region of N-shaped MOS (" NMOS ") device, and in the channel region of p-type MOS (" PMOS ") device, introduce compression stress on source electrode to drain directions.Therefore the technology for improving the stress in MOS device is developed.
Summary of the invention
In order to solve problems of the prior art, according to an aspect of the present invention, provide a kind of method, comprise: form mos field effect transistor (MOSFET), it comprises: implement the first pre-amorphous injection (PAI) district that first injects the gate electrode to form contiguous described MOSFET; The first strain cover layer is formed above a described PAI district; And the first annealing is implemented to form the first dislocation plane to described first strain cover layer and a described PAI district, wherein, because described first annealing forms described first dislocation plane, the inclination angle of described first dislocation plane is less than about 65 degree.
In the above-mentioned methods, in the described first strain cover layer of formation, hydrogen (H is added 2) as process gas.
In the above-mentioned methods, in described first annealing, described first strain cover layer is exposed to ultraviolet light.
In the above-mentioned methods, also comprise the second dislocation plane of the gate electrode forming contiguous described MOSFET, wherein, described first dislocation plane and described second dislocation plane are positioned at the same side of described gate electrode, and extend in the source/drain regions of described MOSFET.
In the above-mentioned methods, after forming described first dislocation plane, implement the formation of described second dislocation plane, and described first dislocation plane and described second dislocation plane-based are originally upper parallel to each other.
In the above-mentioned methods, forming the formation implementing described second dislocation plane after described first dislocation plane, and described first dislocation plane and described second dislocation plane not parallel each other.
In the above-mentioned methods, form described second dislocation plane to comprise: etch described first strain cover layer to remove the tectal horizontal component of described first strain, wherein, the tectal vertical component of described first strain being close to described gate electrode is not etched with formation offset spacer; After the etching, the second injection is implemented to form the 2nd PAI district of contiguous described gate electrode; The second strain cover layer is formed above described 2nd PAI district; And the second annealing is implemented to described second strain cover layer and described 2nd PAI district, wherein, because described second annealing forms described two dislocation planes.
In the above-mentioned methods, the inclination angle of described first dislocation plane is less than about 45 degree.
In the above-mentioned methods, also comprise: after the described first dislocation plane of formation, implement epitaxial growth to form epitaxial semiconductor layer above the source/drain regions of described MOSFET; And implement silication to form silicide area on described source/drain regions, wherein, in silication, consume the top of described epitaxial semiconductor layer, and in silication, do not consume the bottom of described epitaxial semiconductor layer.
In the above-mentioned methods, also comprise contiguous described MOSFET etching shallow trenches isolation (STI) district to form the groove of adjacent described MOSFET, wherein, described STI region has the recessed end face be positioned at below groove, and the pinching line of described first dislocation plane is higher than the recessed end face of described STI region.
According to a further aspect in the invention, additionally provide a kind of method, comprise: form mos field effect transistor (MOSFET), comprising: implement the first pre-amorphous injection (PAI) district that first injects the gate electrode to form contiguous described MOSFET; Above a described PAI district, form the first strain cover layer, in the described first strain cover layer of formation, hydrogen is used as process gas; And the first annealing is implemented to form the first dislocation plane to described first strain cover layer and a described PAI district, wherein, because described first annealing forms described first dislocation plane.
In the above-mentioned methods, also comprise: implement the second injection to form the 2nd PAI district of contiguous described gate electrode; The second strain cover layer is formed above described 2nd PAI district; And the second annealing is implemented to form the second dislocation plane to described second strain cover layer and described 2nd PAI district, wherein, because described second annealing forms described second dislocation plane, and described second dislocation plane is than the channel region of described first dislocation plane further from described MOSFET.
In the above-mentioned methods, in the described second strain cover layer of formation, hydrogen (H is added 2) as process gas.
In the above-mentioned methods, described first dislocation plane has the inclination angle being less than about 45 degree.
In the above-mentioned methods, in described first annealing, described first strain cover layer is exposed to ultraviolet light.
In the above-mentioned methods, also comprise contiguous described MOSFET etching shallow trenches isolation (STI) district to form the groove of adjacent described MOSFET, wherein, described STI region has the recessed end face be positioned at below described groove, and wherein, the pinching line of described first dislocation plane is higher than the recessed end face of described STI region.
According to another aspect of the invention, additionally provide a kind of device, comprising: mos field effect transistor (MOSFET), comprising: semiconductor region; Gate electrode, comprises the part be positioned at above described semiconductor region; And the first dislocation plane, contiguous described gate electrode and be arranged in described semiconductor region, wherein, described first dislocation plane has the inclination angle being less than about 65 degree.
In the devices set out in the foregoing, described inclination angle is less than about 45 degree.
In the devices set out in the foregoing, also comprise contiguous described gate electrode and be arranged in the second dislocation plane of described semiconductor region, wherein, described first dislocation plane and described second dislocation plane not parallel each other.
In the devices set out in the foregoing, also comprise and be close to described gate electrode and the second dislocation plane being arranged in described semiconductor region, wherein, described first dislocation plane and described second dislocation plane are connected to each other.
Accompanying drawing explanation
When reading in conjunction with the accompanying drawings, various aspects of the present invention can be understood best from following detailed description.It should be noted that according to the standard practices in industry, all parts not drawn on scale.In fact, in order to clearly discuss, the size of various parts can at random increase or reduce.
Fig. 1 shows the top view of mos field effect transistor (MOSFET);
Fig. 2 to Figure 11 is according to the MOSFET of each embodiment sectional view in the interstage manufactured;
Figure 12 is the technological process according to embodiment; And
Figure 13 to Figure 21 C is according to the MOSFET of the embodiment sectional view in the interstage manufactured.
Embodiment
Following discloses content provides many different embodiments for realizing different characteristic of the present invention or example.The instantiation of assembly and layout is described below to simplify the present invention.Certainly, these are only examples, and are not intended to limit the present invention.Such as, in the following description, above second component or on form first component and can comprise the embodiment that first component formed in the mode directly contacted with second component, and also can be included between first component and second component and can form extra parts, thus make the embodiment that first component can not directly contact with second component.In addition, the present invention can repeat reference numerals and/or character in various embodiments.This repeats to be in order to simple and clearly object, and itself does not indicate the relation between each discussed embodiment and/or configuration.
And, this can use such as " in ... below ", " ... below ", " bottom ", " ... on ", the space relative terms such as " top " to be to be easy to describe the relation of an element as shown in the figure or parts and another (or other) element or parts.Except the orientation shown in figure, space relative terms is intended to comprise device different azimuth in use or operation.Device can otherwise directed (90-degree rotation or in other orientation), and space relative descriptors can similarly make corresponding explanation as used herein.
According to each embodiment, provide mos field effect transistor (MOSFET) and forming method thereof.Show the interstage forming MOSFET.Discuss change and the operation of embodiment.Run through each view and illustrative embodiment, identical label is for indicating identical element.
Fig. 1 shows the top view of the N-shaped MOSFET100 according to each embodiment.MOSFET100 is three gate MOS FET (being sometimes referred to as FinFET), and comprises at least one and the multiple semiconductor fin 20 of possibility.Semiconductor fin 20 is spaced apart from each other, and has insulation layer (can be that shallow trench isolation is from (STI) district) 24 between semiconductor fin 20.Semiconductor fin 20 forms gate electrode 22 and gate electrode 22 covers the end face of semiconductor fin 20.Gate electrode 22 is also around the sidewall of semiconductor fin 20.Block active area 26 is positioned on the opposite end of semiconductor fin 20, the wherein part of block active area 26A interconnecting semiconductor fin 20 on the left side of gate electrode 22.The part of block active area 26B interconnecting semiconductor fin 20 on the right side of gate electrode 22.
Fig. 2 to Figure 11 is according to the N-shaped MOSFET100 of some embodiments sectional view in the interstage manufactured.Sectional view intercepts from the level-crossing line 2-2 Fig. 1.With reference to Fig. 2, provide Semiconductor substrate 102, and STI region 24 is formed as extending in Semiconductor substrate 102 from the end face of Semiconductor substrate 102.Semiconductor substrate 102 can be silicon substrate, silicon-Germanium substrate, maybe can comprise other semi-conducting materials of such as Group III-V compound semiconductor material.The sidewall of gate electrode 22 and gate electrode 25 optionally forms master shift distance piece 30.Master shift distance piece 30 can be formed by the dielectric material of such as silica, but also can use other dielectric materials of such as silicon nitride, silicon oxynitride etc.STI region 24 comprises groove 36, forms groove 36 by the part of the adjacent semiconductor substrate 102 making STI region 24 is recessed.Therefore, STI region 24 has end face 24A and recessed end face 24B, and wherein recessed end face 24B is lower than end face 24A.Therefore, the part be positioned at above recessed end face 24B of substrate 102 forms semiconductor fin 20 (please refer to Fig. 1) and bulk semiconductor district 26A and 26B (Fig. 1).In certain embodiments, groove 36 can around semiconductor fin 20 and bulk semiconductor district 26A and 26B.Therefore, form channel region 23 in the semiconductor substrate 102, and channel region 23 is positioned at below gate electrode 22.
As indicated by arrows 32, then the first pre-amorphous injection (PAI, sometimes also referred to as pre-amorphous injection) is implemented.In certain embodiments, silicon or germanium is injected.In other embodiments, the inert gas of such as neon, argon, xenon and radon is injected.Pre-amorphous injection destroys the lattice structure of Semiconductor substrate 102.When injecting germanium, Implantation Energy can at about 25keV with about between 40keV, and implantation dosage can at about 1E14/cm 2about 1E15/cm 2between.In some exemplary embodiments, can implement to inject when time at the temperature that Semiconductor substrate 102 is between-100 DEG C, about-60 DEG C of peace treaties.
After a PAI, the exposed tops of Semiconductor substrate 102 is transformed into amorphous state due to PAI at (exposed tops comprises semiconductor fin 20 and bulk semiconductor district 26A and 26B).Therefore PAI district 40 is formed.In an embodiment, vertically implement to inject.In an alternative embodiment, can implement to inject with inclined angle alpha, inclined angle alpha can be less than about 20 degree.As shown in dotted arrow 32, when implement tilt inject time, can implement two tilt inject and two tilt inject be inclined to contrary direction.
The bottom surface 40A in PAI district 40 can higher than the recessed end face 24B of STI region 24 to guarantee that dislocation pinching line 48 (Fig. 3) is higher than recessed STI end face 24B.When implementing vertical injection and when being formed without offset spacer 30, the inward flange in PAI district 40 can be aimed at substantially with the edge of gate electrode 22 (thus make distance S1 substantially equal zero nanometer).Alternatively, PAI district 40 can open distance S1 to the corresponding hithermost marginating compartment of gate electrode 22, and distance S1 is nonzero value.On the other hand, when implementing to tilt to inject, PAI district 40 or can not extend to and be located immediately at below gate electrode 22.
Fig. 3 shows the formation of the first strain cover layer 42.The material of strain cover layer 42 can comprise silicon nitride, titanium nitride, nitrogen oxide, oxide, SiGe, SiC, SiON and their combination.Strain cover layer 42 can have inherent tensile stress.Adjustment formation process with by stress changes to desired value.In certain embodiments, strain cover layer 42 and comprise individual layer.In other embodiments, strain cover layer 42 and can comprise the laminar structure with multilayer.
According to some embodiments, in the process gas for the formation of strain cover layer 42, do not include hydrogen.Such as, when straining cover layer 42 and comprising silicon nitride, process gas can comprise silane (SiH 4) (or SiCl 4) and ammonia (NH 3), and do not add or substantially do not add hydrogen.In the strain cover layer 42 produced, do not comprise or substantially do not comprise hydrogen.
Such as, rapid thermal annealing (RTA), thermal spike RTA is then used to anneal or other method for annealing enforcement annealing.In an embodiment, such as, spike RTA (wherein annealing temperature is between about 950 DEG C and about 1050 DEG C, continues about 3 milliseconds to 5 seconds) is used to implement annealing.In an alternative embodiment, such as, long-time RTA (wherein annealing temperature is between about 550 DEG C and about 950 DEG C, and the duration is between about 10 seconds and about 5 minutes) can be used to implement annealing.Due to annealing, as Fig. 2 Zhong PAI district 40 passes through the stress recrystallization of the storage obtained from strain cover layer 42.Therefore, Semiconductor substrate 102 can apply tensile stress to the channel region 23 of the MOSFET100 produced, thus improves the drive current of MOSFET100.
Due to annealing, form dislocation plane 46.Although shown in sectional view shown in Figure 3 be line, dislocation plane 46 is in the upper plane extended of the longitudinal direction (being also the Y-direction in Fig. 1) of gate electrode 22.The end point 48 of dislocation plane 46 can higher than the recessed end face 24B of STI region 24.This can make the impact of STI region 24 minimize, and STI region 24 adversely applies compression stress to raceway groove 23.End point 48 forms the line that Y-direction in FIG extends, and therefore hereinafter referred to as pinching line 48.
According to some embodiments, dislocation plane 46 and the horizontal plane parallel with the main top surface of substrate 102 or main bottom surface form angle β.Angle β can in the scope of about 45 degree to about 90 degree, and can between about 50 degree and about 60 degree.According to some exemplary embodiments, angle β is about 55 degree.
Next, with reference to Fig. 4, implement etching step, and remove the horizontal component of strain cover layer 42, and retain some vertical components of strain cover layer 42.The remainder of strain cover layer 42 is hereinafter referred to as offset spacer 49.Offset spacer 49 is positioned on the sidewall of master shift sidewall spacer 30, or is positioned at (if not forming master shift sidewall spacer 30) on the sidewall of gate electrode 22.It should be noted that the remainder of strain cover layer 42 also can comprise the part on the sidewall being positioned at substrate 102 and STI region 24, and these parts are not shown.
Fig. 5 shows the formation in the 2nd PAI district 50 injected by the 2nd PAI, uses arrow 52 to illustrate that PAI injects.Stop that some units of injecting usually implement the 2nd PAI and inject by offset spacer 49.Therefore, the inward flange 50A in PAI district 50 than corresponding PAI district 40 (Fig. 2) further from corresponding gate electrode 22.In other words, the level interval S2 of the spacing between the inward flange in PAI district 50 and the nearest edge of corresponding gate electrode 22 is greater than the level interval S1 in Fig. 2.In addition, at least bottom 46A of each dislocation plane 46 is not positioned at the new PAI district 50 formed.This can realize by making PAI district 50 be shallower than pinching line 48.Alternatively, as shown in Figure 5, this also can by using offset spacer 49 Yi Jiang PAI district 50 and gate electrode 22 realization spaced apart in the 2nd PAI.Because PAI district 50 is amorphous area, so the crystal structure in the part of the dislocation plane 46 overlapping with PAI district 50 is destroyed.The 2nd PAI district can be vertically formed, or utilize the inclination angle being equal to or less than the inclined angle alpha (Fig. 2) that a PAI injects to be formed obliquely the 2nd PAI district.This can guarantee that the dislocation plane 56 (Fig. 6) formed subsequently is not overlapping with dislocation plane 46.The element injected can be selected from the spendable similar available element of a PAI.When injecting germanium, Implantation Energy can at about 15keV with about between 50keV, and implantation dosage can at about 1E14/cm 2about 1E15/cm 2between.Can implement to inject when time at the temperature that Semiconductor substrate 102 is between-100 DEG C, about-60 DEG C of peace treaties.
Fig. 6 shows the formation of the second strain cover layer 54.The candidate material of the second strain cover layer 54 can with substantially identical with formation method for the formation of the candidate material straining cover layer 42 with formation method.After formation second strains cover layer 54, implement the second annealing.Similarly, the second annealing can be annealed substantially identical with first shown in Fig. 3.Due to the second annealing, in PAI district 50, there is recrystallization and produce dislocation plane 56.Meanwhile, because the crystal structure in the bottom 46A of dislocation plane 46 is not destroyed by the 2nd PAI, the crystal structure in the part of the destruction of dislocation plane 46 regrows in PAI district 50, and it changes crystal region into again.In the structure of the such as generation of Fig. 6, two dislocation planes 46 and 56 coexist and parallel to each other, and its Dislocations plane 56 is positioned at the outside of corresponding dislocation plane 46.In addition, the pinching line 48 and 58 of corresponding dislocation plane 46 and 56 is higher than the recessed STI end face 24B of STI region 24.In other words, pinching line 48 and 58 can higher than the bottom of corresponding fin 20, bottom fin with the recessed STI end face 24B of STI region 24 at identical horizontal plane place.
Next, as shown in Figure 7, implement etching step, thus make the horizontal component removing strain cover layer 54, and some vertical components straining cover layer 54 are stayed in offset spacer 49 to form offset spacer 59.In processing step subsequently as shown in Figure 8, implement the 3rd PAI62 to form the 3rd PAI district 60.3rd PAI can be substantially identical with the 2nd PAI in Fig. 5.Equally, each bottom all with Bu Yu PAI district 60 overlap of dislocation plane area 46 and 56, and during the 3rd PAI62, do not destroy the crystal structure in the bottom of dislocation plane 46 and 56.The process detail of the 3rd PAI62 can be substantially identical with the 2nd PAI52 (Fig. 5).Due to the interpolation of offset spacer 49 and 59, PAI district 60 is than PAI district 50 (Fig. 5) further from gate electrode 22, and wherein, interval S 3 is greater than the interval S 1 and interval S 2 distinguished as shown in Figure 2 and Figure 5.
With reference to Fig. 9, form the 3rd strain cover layer 64, implement the 3rd annealing steps subsequently to form dislocation plane 66 in the outside of dislocation plane 46 and 56.In addition, dislocation plane 46,56 and 66 parallel to each other.The pinching line 68 of dislocation plane 66 can higher than the recessed end face 24B of STI region 24.
The formation of dislocation plane 46,56 and 66 can cause the increase of the tensile stress in the channel region 23 of MOSFET100.The formation of multiple dislocation plane can cause tensile stress to increase further.Relation between having carried out simulating with the quantity studying dislocation plane in channel stress and MOS device.Result shows, the channel stress with the MOSFET of two dislocation planes (the every side at gate electrode 22) is 1.5 times of the channel stress of the MOSFET with a dislocation plane, and the channel stress with the MOSFET of three dislocation planes is 1.7 times of the channel stress of the MOSFET with two dislocation planes.Therefore, form multiple dislocation plane and effectively can increase channel stress in corresponding MOSFET.
Fig. 2 to Fig. 9 shows the formation of the MOSFET with three dislocation planes.In an alternative embodiment, MOSFET can have and is positioned at two dislocation planes on every side of gate electrode or the dislocation plane more than three.
With reference to Figure 10, remove strain cover layer 64 and offset spacer 49 and 59.Such as, when straining cover layer 64 and offset spacer 49 and 59 comprises silicon nitride, H can be used 3pO 4implement the removal of offset spacer 49 and 59.Also source/drain regions 110 is formed by injecting.Then epitaxial growth can be implemented with growing epitaxial semiconductor layer 70 on the end face of source/drain regions 110.In an embodiment, epitaxial semiconductor layer 70 comprises silicon, silicon phosphorus, silicon-carbon phosphorus etc.
Next, as shown in figure 11, silication is implemented to form silicide area 72.In an embodiment, in silication, consume the top of epitaxial semiconductor layer 70, and in silication, do not consume the bottom of epitaxial semiconductor layer 70.Therefore, the bottom surface of the silicide area 72 of generation is higher than the end face of the channel region 23 of MOSFET100.Analog result shows, when end face higher than channel region 23 of the bottom surface of silicide area 72, can improve the drive current of MOSFET100, and when the bottom surface of silicide area is higher, this raising increases.
Figure 12 shows the exemplary process flow for the formation of dislocation.First, master shift distance piece (step 120) is formed.Step 120 in Figure 12 can correspond to the step in Fig. 2.Then implement the first dislocation by step 122,124 and 126 to be formed.In step 122, implement pre-amorphous and inject, implement subsequently as the deposition of the stress film for the formation of dislocation in step 124 and 126 and annealing.Step 122,124 and 126 can correspond to the step shown in Fig. 2 to Fig. 4.Next, stress film is etched to expand the size of offset spacer.This step can correspond to the etching step in Fig. 4.Implement the second dislocation by step 130,132,134 and 136 to be formed.In step 130, implement extra pre-amorphous and inject, implement the extra stress film deposition for the formation of dislocation and extra annealing (step 132 and 134) subsequently.In step 136, extra stress film is etched to expand the size of offset spacer.Step 130,132,134 and 136 can correspond to the step shown in Fig. 5 to Fig. 7.Step 130,132,134 and 136 can repeat one or many.Such as, the step shown in Fig. 8 and Fig. 9 show step 130,132, the exemplary repetition of 134 and 136.Step 138 shows the removal of stress film and selectable master shift sidewall spacer.Step 138 can correspond to the illustrative steps shown in Figure 10.
Figure 13 to Figure 21 C shows according to the MOSFET of the embodiment sectional view in the interstage formed.Unless otherwise prescribed, the material of assembly is in these embodiments substantially identical with their same components with formation method, and identical assembly is represented by the identical reference number in the embodiment shown in Fig. 1 to Figure 12.Therefore, can find in the discussion of the embodiment shown in Fig. 1 to Figure 12 about the formation process of assembly shown in Figure 13 to Figure 21 C and the details of material.
Substantially identical with shown in Fig. 2 of the initial configuration of these embodiments and forming step, wherein forms PAI district 40.Next, Figure 13 shows the formation of the first strain cover layer 42.The material of strain cover layer 42 can comprise silicon nitride, titanium nitride, nitrogen oxide, oxide, SiGe, SiC, SiON and their combination.Except other materials, strain cover layer 42 also comprises hydrogen.Such as, strain cover layer 42 can be hydrogeneous silicon nitride, hydrogeneous titanium nitride, containing silicon hydroxide, hydrogeneous silicon oxynitride, hydrogeneous SiGe, hydrogeneous SiC, hydrogeneous SiON, their combination or their multilayer.
In the formation of hydrogeneous strain cover layer 42, except other process gass, process gas comprises hydrogen (H 2).Such as, when straining cover layer 42 and comprising silicon nitride, process gas can comprise silane (SiH 4) (or SiCl 4), ammonia (NH 3) and hydrogen.Depositing temperature can between about 400 DEG C and about 500 DEG C.Process gas has the pressure of about 1 holder to about 15 holders.Therefore, the strain cover layer 42 of generation comprises hydrogen.In some exemplary embodiments, in the deposition of strain cover layer 42, the flow velocity of hydrogen higher than about 100sccm to improve the hydrogen concentration in hydrogeneous strain cover layer 42.In an alternative embodiment, strain cover layer 42 is first formed.Strain cover layer 42 can be without hydrogen or hydrogeneous.After formation strain cover layer 42, implement extra diffusion technology so that (more) hydrogen is attached to strain cover layer 42 and to increase the hydrogen concentration strained in cover layer 42 further.In the hydrogeneous strain cover layer 42 produced, hydrogen concentration can be greater than about 1E19/cm 3, be greater than about 1E20/cm 3or be greater than about 1E19/cm 3.
Such as, RTA, thermal spike RTA is then used to anneal or other method for annealing enforcement annealing.Annealing temperature can between about 400 DEG C and about 500 DEG C.Such as O can adopted 2, N 2, H 2deng process gas environment in implement annealing.Process gas has the pressure of about 1 holder to about 15 holders.In addition, in annealing, hydrogeneous strain cover layer 42 is exposed to ultraviolet (UV)) light.Due to annealing, Fig. 2 Zhong PAI district 40 passes through the stress recrystallization of the storage obtained from strain cover layer 42.Therefore, Semiconductor substrate 102 can apply tensile stress to the channel region 23 of the MOSFET100 produced, thus improves the drive current of MOSFET100.
Due to annealing, form dislocation plane 46.According to some embodiments, due to the formation of hydrogeneous strain cover layer 42, so in annealing, hydrogen degasification from hydrogeneous strain cover layer 42.Such as, UV light contributes to degasification.Growth rate in this embodiment causing the growth rate of the solid phase epitaxy phase regrowth (SPER) in different crystalline plane to be different from Fig. 3.Such as, in the embodiment illustrated in figure 3, growth rate in (100) plane of Semiconductor substrate 102 can be greater than the growth rate in (110) plane of Semiconductor substrate 102, this causes the angle β (Fig. 3) of dislocation plane 46 larger, and angle β can be about 55 degree.In embodiment shown in Figure 13, such as, the growth rate in (100) plane of Semiconductor substrate 102 is decreased to lower than the growth rate in (110) plane of Semiconductor substrate 102,
This causes the angle γ (Figure 13) of dislocation plane 46 smaller (being less than about 65 degree).In certain embodiments, angle γ is less than about 45 degree and in the scope of 0 degree to about 45 degree.Angle γ also can from the scope of about 20 degree to about 40 degree.In some exemplary embodiments, angle γ is about 35 degree.Advantageously, little angle γ causes the stress being applied to channel region 23 higher.Therefore, the angle γ reducing dislocation plane 46 is expected.
The end point 48 of dislocation plane can higher than the recessed end face 24B of STI region 24.This can make the impact of STI region 24 minimize, and it adversely applies compression stress to raceway groove 23.End point 48 forms the line that Y-direction in FIG extends, and therefore hereinafter referred to as pinching line 48.
Next, implement etching step, and remove the horizontal component of strain cover layer 42, and some vertical components of reservation strain cover layer 42 are to be formed as the offset spacer 49 in Figure 14.Equally, offset spacer 49 is positioned on the sidewall of master shift sidewall spacer 30, or is positioned at (if not forming master shift sidewall spacer 30) on the sidewall of gate electrode 22.It should be noted that the remainder of strain cover layer 42 also can comprise (or can not comprise) and be positioned at part on the sidewall of substrate 102 and STI region 24, and these parts are not shown.
Figure 15 shows the formation in the 2nd PAI district 50 injected by the 2nd PAI, uses arrow 52 to illustrate that this PAI injects.Stop that some units of injecting usually implement the 2nd PAI and inject by offset spacer 49.Therefore, the inward flange 50A in PAI district 50 than corresponding PAI district 40 (Fig. 2) further from corresponding gate electrode 22.In other words, the level interval S1 in Fig. 2 is greater than for the level interval S2 (Figure 15) of the spacing between the inward flange in PAI district 50 and the edge of the nearest accordingly of gate electrode 22.In addition, at least bottom 46A of each dislocation plane 46 is not positioned at the new PAI district 50 formed.This can realize by making PAI district 50 be shallower than pinching line 48.Alternatively, as shown in figure 15, this by using offset spacer 49 Yi Jiang PAI district 50 and gate electrode 22 realization spaced apart in the 2nd PAI.Because PAI district 50 is amorphous area, thus in dislocation plane 46 Yu PAI district 50 overlap part in crystal structure be destroyed.Injection technology can be similar to the injection technology discussed with reference to Fig. 5.
Figure 16 A shows the formation of the second strain cover layer 54.The candidate material of strain cover layer 54 can with substantially identical with formation process for the formation of the candidate material straining cover layer 42 with formation process.According to some embodiments, strain cover layer 54 comprises hydrogen, and between strain cover layer 54 Formation period or afterwards hydrogen can be incorporated in strain cover layer 54.In an alternative embodiment, cover layer 54 is strained not hydrogeneous or substantially not hydrogeneous.
After strain cover layer 54 is formed, implement the second annealing.Second annealing can use the process conditions that the process conditions that use of annealing with shown in Figure 13 first are substantially identical, or to anneal the different process conditions of the process conditions that use from first shown in Figure 13.Due to the second annealing, in PAI district 50, there is recrystallization, and produce dislocation plane 56.Meanwhile, because the bottom 46A (Figure 15) of dislocation plane 46 is not destroyed by the 2nd PAI, the part of the destruction of dislocation plane 46 regrows in PAI district 50, and it changes crystal region into again.In the structure of the such as generation of Figure 16 A, dislocation plane 46 and 56 coexists and can be parallel to each other, and its Dislocations plane 56 is positioned at the outside of corresponding dislocation plane 46.In addition, the pinching line 48 and 58 of corresponding dislocation plane 46 and 56 is higher than the recessed STI end face 24B of STI region 24.In other words, pinching line 48 and 58 can higher than the bottom of corresponding fin 20, and the STI end face 24B of the bottom of fin 20 and the recessed of STI region 24 is at identical horizontal plane place.
According to wherein straining some embodiments that cover layer 54 is hydrogeneous layers, the dislocation plane 56 of generation has inclination angle γ, and the angle γ of dislocation plane 56 can be identical or different with the angle γ of dislocation plane 46.Therefore, dislocation plane 46 can or can not be parallel with corresponding dislocation plane 56.In an alternative embodiment, as shown in fig 16b, dislocation plane 56 can have the angle θ being greater than angle γ.In certain embodiments, angle θ equals as the angle β in Fig. 3.Can by making to strain the not hydrogeneous or substantially not hydrogeneous difference realized between angle θ and angle γ of cover layer 54 accordingly.
Figure 16 C shows the sectional view of embodiment, and the inclination angle of its Dislocations plane 56 is less than the inclination angle of dislocation plane 46.According to some exemplary embodiments, the inclination angle of dislocation plane 56 is γ, and the inclination angle of dislocation plane 46 is β.In these embodiments, dislocation plane 56 or can not contact dislocation plane 46.
Next, as shown in figure 17, implement etching step, thus remove the horizontal component of strain cover layer 54, and some vertical components straining cover layer 54 are stayed in offset spacer 49 to form offset spacer 59.As shown in figure 18, in processing step subsequently, implement the 3rd PAI62 to form the 3rd PAI district 60.3rd PAI can be substantially identical with the 2nd PAI in Figure 15.Equally, each dislocation plane area 46 and 56 has the bottom of Bu Yu PAI district 60 overlap, and during the 3rd PAI62, do not destroy the crystal structure of the bottom of dislocation plane area 46 and 56.The process detail of the 3rd PAI62 can be substantially identical with the 2nd PAI52 (Figure 15).
Due to adding of offset spacer 49 and 59, PAI district 60 is than PAI district 50 (Fig. 5) further from gate electrode 22, and wherein, interval S 3 is greater than interval S 1 respectively as shown in Fig. 2 and Figure 15 and interval S 2.
With reference to Figure 19, form the 3rd strain cover layer 64, implement the 3rd annealing steps subsequently to form dislocation plane 66 in the outside of dislocation plane 46 and 56.In addition, dislocation plane 46,56 and 66 can be parallel to each other or can not be parallel to each other.The pinching line 68 of dislocation plane 66 can higher than the recessed end face 24B of STI region 24.According to some embodiments, strain cover layer 64 is hydrogeneous.In an alternative embodiment, it is not hydrogeneous for straining cover layer 64.As a result, the angle straining cover layer 64 can in about 45 degree to the scope of 90 degree or in the scope of 0 degree to about 45 degree.
With reference to Figure 20, remove strain cover layer 64 and offset spacer 49 and 59.Then epitaxial growth can be implemented with growing epitaxial semiconductor layer 70 on the end face of source/drain regions 110.Also source/drain regions 110 can be formed by injecting.Dislocation plane 46,56 and 66 can grow in epitaxial semiconductor layer 70.Epitaxial semiconductor layer 70 can comprise silicon, silicon phosphorus, silicon-carbon phosphorus etc.
Next, as shown in Figure 21 A, Figure 21 B and Figure 21 C, implement silication to form silicide area 72.Silicification technics is substantially identical with details with the silicification technics in the embodiment in Figure 11 with corresponding details, and does not repeat at this.
Figure 21 A, Figure 21 B and Figure 21 C show each embodiment of the present invention.Each dislocation plane can have its oneself inclination angle (such as β, γ and θ), and inclination angle can be identical or different with the inclination angle of other dislocation planes.Can realize different angles by regulating the hydrogen concentration in corresponding strain cover layer, and hydrogen concentration is higher, inclination angle is less.In addition, the amount of hydrogen needs to reach a certain amount of to reduce inclination angle.Such as, Figure 21 A shows dislocation plane 46,56 and 66 and has identical inclination angle γ.In an alternative embodiment, as illustrated in fig. 21b, dislocation plane 46 has the inclination angle (such as γ) less than the inclination angle (such as β) of the dislocation plane 56 and 66 of outside.In other embodiment, as shown in fig. 21 c, dislocation plane 46 has the inclination angle (such as β) larger than the inclination angle (such as γ) of the dislocation plane 56 and 66 of outside.According to some embodiments, as shown in fig. 21 c, outside dislocation plane (such as dislocation plane 56 or 66) can contact inner dislocation plane (such as dislocation plane 46 or 56).In other embodiments, although the dislocation plane of outside has the inclination angle less than the dislocation plane of inside, the dislocation plane of outside can not with the dislocation plane contact of inside.
Embodiments of the invention have some favorable characteristics.By forming multiple dislocation plane, add the strain in the channel region of MOSFET.Because strain cover layer is also used as the distance piece of the position limiting dislocation plane, so the low cost of manufacture of technique according to an embodiment of the invention.In addition, by hydrogen being attached in strain cover layer, reducing the inclination angle of dislocation plane, thus causing the further increase of the strain of the channel region being applied to MOSFET.
According to some embodiments of the present invention, a kind of method comprises formation MOSFET.The method comprises the PAI district implementing the gate electrode injected to form contiguous MOSFET; Strain cover layer is formed above PAI district; And annealing is implemented to form dislocation plane to strain cover layer and PAI district.Because annealing forms dislocation plane, the inclination angle of dislocation plane is less than about 65 degree.
According to an alternative embodiment of the invention, a kind of method comprises enforcement and injects the PAI district of the gate electrode to form contiguous MOSFET and above PAI district, form strain cover layer, wherein strains in cover layer in formation, hydrogen is used as process gas.The method also comprises implements annealing to form dislocation plane to strain cover layer and PAI district.Because annealing forms dislocation plane.
According to other embodiment of the present invention, MOSFET comprises semiconductor region, comprises the gate electrode of the part be arranged in above semiconductor region and is close to gate electrode and is positioned at the dislocation plane of semiconductor region.Dislocation plane has the inclination angle being less than about 65 degree.
Foregoing has outlined the feature of some embodiments, make each side that the present invention may be better understood for those skilled in the art.It should be appreciated by those skilled in the art that they can easily use to design based on the present invention or revise for implement with herein introduce the identical object of embodiment and/or realize other techniques and the structure of identical advantage.Those skilled in the art also it should be appreciated that this equivalent constructions does not deviate from the spirit and scope of the present invention, and when not deviating from the spirit and scope of the present invention, at this, they can make multiple change, replacement and change.

Claims (10)

1. a method, comprising:
Form mos field effect transistor (MOSFET), comprising:
Implement the first pre-amorphous injection (PAI) district that first injects the gate electrode to form contiguous described MOSFET;
The first strain cover layer is formed above a described PAI district; And
Implement the first annealing to form the first dislocation plane to described first strain cover layer and a described PAI district, wherein, because described first annealing forms described first dislocation plane, the inclination angle of described first dislocation plane is less than about 65 degree.
2. method according to claim 1, wherein, in the described first strain cover layer of formation, adds hydrogen (H 2) as process gas.
3. method according to claim 1, wherein, in described first annealing, is exposed to ultraviolet light by described first strain cover layer.
4. method according to claim 1, also comprise the second dislocation plane of the gate electrode forming contiguous described MOSFET, wherein, described first dislocation plane and described second dislocation plane are positioned at the same side of described gate electrode, and extend in the source/drain regions of described MOSFET.
5. method according to claim 4, wherein, implements the formation of described second dislocation plane after forming described first dislocation plane, and described first dislocation plane and described second dislocation plane-based are originally upper parallel to each other.
6. method according to claim 4, wherein, forming the formation implementing described second dislocation plane after described first dislocation plane, and described first dislocation plane and described second dislocation plane not parallel each other.
7. method according to claim 4, wherein, forms described second dislocation plane and comprises:
Etch described first strain cover layer to remove the tectal horizontal component of described first strain, wherein, the tectal vertical component of described first strain of contiguous described gate electrode is not etched with formation offset spacer;
After the etching, the second injection is implemented to form the 2nd PAI district of contiguous described gate electrode;
The second strain cover layer is formed above described 2nd PAI district; And
Second annealing is implemented to described second strain cover layer and described 2nd PAI district, wherein, because described second annealing forms described two dislocation planes.
8. method according to claim 1, wherein, the inclination angle of described first dislocation plane is less than about 45 degree.
9. a method, comprising:
Form mos field effect transistor (MOSFET), comprising:
Implement the first pre-amorphous injection (PAI) district that first injects the gate electrode to form contiguous described MOSFET;
Above a described PAI district, form the first strain cover layer, in the described first strain cover layer of formation, hydrogen is used as process gas; And
First annealing is implemented to form the first dislocation plane to described first strain cover layer and a described PAI district, wherein, because described first annealing forms described first dislocation plane.
10. a device, comprising:
Mos field effect transistor (MOSFET), comprising:
Semiconductor region;
Gate electrode, comprises the part be positioned at above described semiconductor region; And
First dislocation plane, be close to described gate electrode and be arranged in described semiconductor region, wherein, described first dislocation plane has the inclination angle being less than about 65 degree.
CN201410770305.0A 2014-08-08 2014-12-15 MOSFET with multiple dislocation planes Active CN105374873B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/455,102 US9299838B2 (en) 2011-10-24 2014-08-08 MOSFETs with multiple dislocation planes
US14/455,102 2014-08-08

Publications (2)

Publication Number Publication Date
CN105374873A true CN105374873A (en) 2016-03-02
CN105374873B CN105374873B (en) 2018-05-15

Family

ID=55134670

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410770305.0A Active CN105374873B (en) 2014-08-08 2014-12-15 MOSFET with multiple dislocation planes

Country Status (4)

Country Link
KR (1) KR101659176B1 (en)
CN (1) CN105374873B (en)
DE (1) DE102014119643B4 (en)
TW (1) TWI559527B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109920846A (en) * 2019-03-11 2019-06-21 长江存储科技有限责任公司 Transistor and forming method thereof, memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
CN1790734A (en) * 2004-12-02 2006-06-21 台湾积体电路制造股份有限公司 Semiconductor device and methods of producing the same
CN102468164A (en) * 2010-10-29 2012-05-23 中国科学院微电子研究所 Transistor and manufacture method thereof
CN103066124A (en) * 2011-10-20 2013-04-24 台湾积体电路制造股份有限公司 Semiconductor device with multiple stress structures and method of forming the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8779477B2 (en) * 2008-08-14 2014-07-15 Intel Corporation Enhanced dislocation stress transistor
US8058134B2 (en) * 2009-02-19 2011-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Junction profile engineering using staged thermal annealing
US8809918B2 (en) * 2011-10-24 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. MOSFETs with multiple dislocation planes

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
CN1790734A (en) * 2004-12-02 2006-06-21 台湾积体电路制造股份有限公司 Semiconductor device and methods of producing the same
CN102468164A (en) * 2010-10-29 2012-05-23 中国科学院微电子研究所 Transistor and manufacture method thereof
CN103066124A (en) * 2011-10-20 2013-04-24 台湾积体电路制造股份有限公司 Semiconductor device with multiple stress structures and method of forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109920846A (en) * 2019-03-11 2019-06-21 长江存储科技有限责任公司 Transistor and forming method thereof, memory
CN109920846B (en) * 2019-03-11 2023-11-03 长江存储科技有限责任公司 Transistor, forming method thereof and memory

Also Published As

Publication number Publication date
KR101659176B1 (en) 2016-09-22
CN105374873B (en) 2018-05-15
DE102014119643B4 (en) 2018-01-25
TWI559527B (en) 2016-11-21
TW201607026A (en) 2016-02-16
DE102014119643A1 (en) 2016-02-11
KR20160018317A (en) 2016-02-17

Similar Documents

Publication Publication Date Title
US10269967B2 (en) MOSFETs with multiple dislocation planes
US8809918B2 (en) MOSFETs with multiple dislocation planes
US9698249B2 (en) Epitaxy in semiconductor structure and manufacturing method of the same
US10720529B2 (en) Source/drain junction formation
US8802533B1 (en) Semiconductor device and method of manufacturing the same
US20170365528A1 (en) Semiconductor device and method of manufacturing the semiconductor device
CN108461394B (en) Method for manufacturing semiconductor device using stress memorization technology and semiconductor device
US20130015443A1 (en) Semiconductor device and manufacturing method thereof
US7952122B2 (en) Strained semiconductor device and method of making same
CN103811313A (en) Reducing pattern loading effect in epitaxy
US10361305B2 (en) Semiconductor structure and fabrication method thereof
US9406797B2 (en) Semiconductor integrated circuit with dislocations
CN105374873A (en) Mosfets with multiple dislocation planes
US20080206965A1 (en) STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY
CN109087859A (en) A kind of manufacturing method of semiconductor devices
US8633078B2 (en) Method for manufacturing semiconductor device
US20160056268A1 (en) Method for fabricating semiconductor device improving the process speed
US10340385B2 (en) Method to improve FinFET device performance
CN111403339B (en) Semiconductor structure and forming method thereof
JP2011091291A (en) Semiconductor device and method of manufacturing the same
US20130183801A1 (en) Method for manufacturing semiconductor devices
KR20060039610A (en) Method for manufacturing transistor in semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant