TWI559527B - Semiconductor device and methods for forming the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device technology, and more particularly to a semiconductor device having a metal oxide semiconductor field effect transistor and a method of fabricating the same.

In order to improve the performance of a metal oxide semiconductor (MOS) device, stress can be introduced in the channel region to cause the metal oxide semiconductor to increase the carrier mobility. In general, it is desirable to generate tensile stress from the source to the drain in the channel of the N-type metal oxide semiconductor (NMOS), and from the source to the drain between the channels of the P-type metal oxide semiconductor (PMOS). The direction of the stress is generated. Therefore, it began to explore techniques for increasing the stress of metal oxide semiconductors.

Embodiments of the present invention provide a method of fabricating a semiconductor device, including forming a metal oxide semiconductor field effect transistor, including performing a first implant to form a first pre-amorphization implant region adjacent to metal oxide a gate electrode of the semiconductor field effect transistor; forming a first strain cap layer on the first pre-amorphization implant region; and performing a first strain cap layer and the first pre-amorphization implant region The first annealing forms a first difference surface, wherein the first difference surface is formed by the first annealing, and the first difference mask has an inclination angle of less than 65 degrees.

Embodiments of the present invention provide another method of fabricating a semiconductor device, comprising performing a first implant to form a first pre-amorphization implant region adjacent to a gate electrode of a metal oxide semiconductor field effect transistor Forming a first strained cap layer on the first pre-amorphization implanted region, and using the hydrogen as the process gas when forming the first strained cap layer; and first pre-amorphizing the first strained cap layer The implant region performs a first annealing to form a first difference surface, wherein the first difference surface is formed by the first annealing.

Embodiments of the present invention provide a semiconductor device including a metal oxide semiconductor field effect transistor including a semiconductor region; a gate electrode including a portion on the semiconductor region; and a first difference surface adjacent to The gate electrode is located in the semiconductor region, wherein the first row mask has an angle of inclination of less than 65 degrees.

20‧‧‧Semiconductor fin structure

22, 25‧‧‧ gate electrode

23‧‧‧Channel area

24‧‧‧Isolation area (shallow trench isolation area)

24A‧‧‧Upper surface

24B‧‧‧ concave upper surface

26A, 26B‧‧‧ Block Active Area

30‧‧‧Main offset spacer

49, 59‧‧‧ offset gap

32‧‧‧First pre-amorphization implant

36‧‧‧ Notch

40‧‧‧First pre-amorphization implanted area

40A‧‧‧ lower surface

42‧‧‧First strain cover

46, 56, 66‧ ‧ ‧ poor face

48, 58, 68‧‧‧ pinch line (bottom point)

50‧‧‧Second pre-amorphization implanted area

50A‧‧‧ inside edge

52‧‧‧Second pre-amorphization implant

54‧‧‧Second strain cover

60‧‧‧ third pre-amorphization implanted area

62‧‧‧ Third pre-amorphization implant

64‧‧‧ third strain cover

70‧‧‧Semiconductor epitaxial layer

72‧‧‧Metal bismuth compound area

100‧‧‧N type metal oxide semiconductor field effect transistor

102‧‧‧Semiconductor substrate

110‧‧‧Source/Bungee Area

120, 122, 124, 126, 128, 130, 132, 134, 136, 138 ‧ ‧ steps

S1, S2, S3‧‧‧ spacing

α, β, γ, θ‧‧‧ angle

Figure 1 is a schematic plan view of a metal oxide semiconductor field effect transistor (MOSFET).

Figures 2 through 11 are schematic cross-sectional views showing various stages of fabrication of metal oxide semiconductor field effect transistors of various embodiments.

Figure 12 is a flow chart showing a manufacturing method of various embodiments.

13-15, 16A-16C, 17-20, 21A-21C are schematic cross-sectional views showing various stages of fabrication of a metal oxide semiconductor field effect transistor of another embodiment.

It is to be understood that the following disclosures of this specification provide many The same embodiments or examples are used to implement different features of the invention. The disclosure of the present specification is a specific example of the various components and their arrangement in order to simplify the description of the invention. Of course, these specific examples are not intended to limit the invention. For example, if the disclosure of the present specification describes forming a first feature on or above a second feature, that is, it includes an embodiment in which the formed first feature is in direct contact with the second feature. Also included is an embodiment in which additional features are formed between the first feature and the second feature described above, such that the first feature and the second feature may not be in direct contact. In addition, different examples in the description of the invention may use repeated reference symbols and/or words. These repeated symbols or words are not intended to limit the relationship between the various embodiments and/or the appearance structures for the purpose of simplicity and clarity.

Furthermore, for convenience of describing the relationship of one element or feature in the drawings to another (plural) element or (complex) feature, space-related terms such as "below", "below", "lower", "above", "upper" and similar terms. Spatially related terms encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, elements that are described as "below" or "below" other elements or features in the <RTIgt; Therefore, the term "below" of the example may encompass the orientation above and below. The device may also be additionally positioned (eg, rotated 90 degrees or at other orientations) and the description of the spatially relevant terms used may be interpreted accordingly.

According to various embodiments, a metal oxide semiconductor field effect transistor (MOSFET) and a method for fabricating the same are provided, and various stages of manufacturing are represented by the drawings, and each Differences and operations of the embodiments. The same reference numbers are used in the different views and the embodiments to refer to the same or similar parts.

1 is a schematic plan view of an N-type metal oxide semiconductor field effect transistor (MOSFET) 100 according to various embodiments. The metal oxide semiconductor field effect transistor 100 is a three-gate metal oxide semiconductor field effect. a transistor (also referred to as a fin field effect transistor (FinFET)) and comprising at least one semiconductor structure 20, the semiconductor fin structure 20 being comprised of isolation regions 24 (which may be shallow trench isolation regions, STI regions) isolate each other. A gate electrode 22 is formed over the semiconductor fin structure 20 and covers the upper surface of the semiconductor fin structure 20. Gate electrode 22 also encapsulates the sidewalls of semiconductor fin structure 20. A bulk active region 26 is located at an opposite end of the semiconductor fin structure 20, wherein the bulk active region 26A is connected to a portion of the semiconductor fin structure 20 located on the left side of the gate electrode 22, and the bulk active region 26B is partially located The semiconductor fin structure 20 on the right side of the gate electrode 22 is connected inside.

2 through 11 are cross-sectional views showing the intermediate stages of fabricating an N-type metal oxide semiconductor field effect transistor 100 in accordance with some embodiments, which is a cross-sectional view taken along line 2-2 of Fig. 1. Referring to FIG. 2, a semiconductor substrate 102 is provided to form a shallow trench isolation region 24 that extends from the upper surface of 102 into the semiconductor substrate 102. The semiconductor substrate 102 can be a germanium substrate, a germanium substrate, or other semiconductor material such as a tri-five compound semiconductor. On the sidewalls of the gate electrode 22 and the gate electrode 25, a main offset spacer 30 can be selectively formed. The primary offset spacers 30 may be formed of a dielectric material such as hafnium oxide, and other dielectric materials such as tantalum nitride, hafnium oxynitride or the like may also be used. The shallow trench isolation region 24 includes a recess 36, and the recess 36 is formed by a recess The shallow trench isolation regions 24 are formed adjacent to the semiconductor substrate 102. Thus, the shallow trench isolation region 24 has an upper surface 24A and a recessed upper surface 24B, wherein the recessed upper surface 24B is positioned lower than the upper surface 24A. The semiconductor fin structure 20 (please refer to FIG. 1) and the bulk active regions 26A and 26B are formed partially above the recessed upper surface 24B (see FIG. 1). In some embodiments, the recess 36 can surround the semiconductor fin structure 20 and the bulk active regions 26A and 26B. The channel region 23 is thus formed within the semiconductor substrate 102 and below the gate electrode 22.

Next, a first pre-amorphization/preamorphous implantation (PAI) is performed, as indicated by arrow symbol 32. In some embodiments, helium or neon is implanted, and in other embodiments, an inert gas such as helium, argon, neon, or xenon is implanted. The pre-amorphization implant destroys the lattice structure of the semiconductor substrate 102. When implanted, the implant energy can be between about 25 keV and 40 keV, and the implant dose can be between about 10 ¹⁴ /cm ² and 10 ¹⁵ /cm ² . In some exemplary embodiments, implantation is performed when the semiconductor substrate 102 is at a temperature between -60 degrees Celsius and -100 degrees Celsius.

After the first pre-amorphization implantation, a portion of the exposed upper portion of the semiconductor substrate 102 includes the semiconductor fin structure 20 and the bulk active regions 26A and 26B and is transformed into an amorphous state by pre-amorphization implantation. Forming a pre-amorphized implant region 40. Vertical implants are performed in one embodiment, and in other embodiments, implants are performed at an oblique angle a or less than 20 degrees. As indicated by the dashed arrow symbol 32, when the oblique angle is implanted, two oblique angles can be performed which are inclined in opposite directions.

To ensure that the difference pinch line 48 (see FIG. 3) is higher than the recessed upper surface 24B of the shallow trench isolation region 24, the lower surface 40A of the pre-amorphization implant region 40 may be higher than the recess upper surface 24B. When vertical planting is performed and there is no offset gap 30 shape At the time of the formation, the inner edge of the pre-amorphization implant region 40 can be substantially aligned with the edge of the gate electrode 22 (so that the pitch S1 is substantially equal to 0 nm). Alternatively, the pre-amorphization implant region 40 and the edge of the closest gate electrode 22 may be separated by a non-zero spacing S1. On the other hand, the pre-amorphization implant region 40 may or may not extend directly below the gate electrode 22 when performing oblique implants.

Figure 3 depicts the formation of a first strained cap layer 42. The material of the strained cap layer 42 includes tantalum nitride, titanium nitride, nitrogen oxides, oxides, antimony, antimony carbide, antimony oxynitride, and combinations thereof. The strained cap layer 42 can have an inherent tensile stress. The stress is changed to the desired value by adjusting the manufacturing process. In some embodiments, the strained cap layer 42 includes a single layer, and in other embodiments, the strained cap layer 42 can be a multi-layered layered structure.

According to some embodiments, hydrogen is not included in the process gas forming the strained cap layer 42. For example, when the strained cap layer 42 is composed of tantalum nitride, the process gas may include decane (SiH ₄ ) (or SiCl ₄ ) and ammonia (NH ₃ ), but no hydrogen is added or substantially no hydrogen is added. Hydrogen or substantially no hydrogen is included in the final strained cap layer 42.

Next, annealing is performed, such as rapid thermal anneal (RTA), rapid thermal annealing (spike RTA), or other annealing methods. In one embodiment, an instant rapid thermal anneal is used with an annealing temperature between 950 ° C and 1050 ° C for a time of about 3 milliseconds to 5 seconds. In other embodiments, for example, a prolonged rapid thermal anneal can be performed with an annealing temperature between 550 ° C and 950 ° C for a duration of about 10 seconds to 5 minutes. Due to the annealing, the pre-amorphization implanted region 40 shown in Fig. 2 is recrystallized by the memory stress obtained from the strained cap layer 42. Therefore, the semiconductor substrate 102 can provide a stress to the final metal oxide The channel region 23 of the semiconductor field effect transistor 100 is used to improve the driving current of the metal oxide semiconductor field effect transistor 100.

Due to the annealing, a differential face 46 is formed. Although the cross-sectional view of FIG. 3 shows the difference row 46 as a line, the difference surface 46 is actually a plane extending from the longitudinal direction of the gate electrode 22 or the Y direction of FIG. The bottom point 48 of the differential face 46 may be higher than the recessed upper surface 24B of the shallow trench isolation region 24, while minimizing the effect of the shallow trench isolation region 24 providing unfavorable compressive stress to the channel region 23. The bottom point 48 extends from the Y direction of Fig. 1 to form a line, and is hereinafter referred to as a pinch line 48.

According to some embodiments, the differential face 46 forms an angle β with a horizontal plane parallel to a major upper/lower surface of the substrate 102, and the angle β may be between 45 degrees and 90 degrees, and may also be between 50 degrees and 60 degrees. between. According to some exemplary embodiments, the angle β is approximately 55 degrees.

Next, referring to FIG. 4, an etching step is performed to remove the horizontal portion of the strained cap layer 42 while leaving the vertical portion of the strained cap layer 42. The remaining portion of the strained cap layer 42 is hereinafter referred to as an offset gap wall 49 that is located on the sidewall of the primary offset spacer wall 30. If the main offset spacers 30 are not formed, the offset spacers 49 are located on the sidewalls of the gate electrodes 22. It may be noted that the remaining portion of the strained cap layer 42 may also include portions that are partially on the sidewalls of the substrate 102 and the shallow trench isolation regions 24, and these portions are not shown in the figures.

Figure 5 depicts a second pre-amorphization implant region 50 formed via a second pre-amorphization implant and depicts the pre-amorphization implant at arrow 52. The second pre-amorphization implant is performed with the offset spacers 49 blocking some of the implant elements. Therefore, the gate electrode 22 is farther from the inner edge 50A of the pre-amorphization implant region 50 than to the pre-amorphization implant region 40 (see FIG. 2). Alternatively, the horizontal spacing S2, that is, the spacing between the inner edge of the pre-amorphization implant region 50 and the edge of the closest gate electrode 22 is greater than the horizontal pitch S1 of FIG. Furthermore, by having the pre-amorphization implant region 50 shallower than the pinch line 48, it is achieved that at least one bottom portion 46A of each of the difference rows 46 is not located inside the newly formed pre-amorphization implant region 50, Alternatively, as depicted in FIG. 5, the pre-amorphization implant region 50 can be moved away from the gate electrode 22 by using the offset spacers 49 formed by the second pre-amorphization implant. Since the pre-amorphous phased implant region 50 is an amorphous region, the crystal structure of the partial difference surface 46 overlapping the pre-amorphization implant region 50 is destroyed. The second pre-amorphization implanted region may be formed vertically or obliquely at an inclination angle α equal to or smaller than the first pre-amorphous phased implant (see FIG. 2). It is ensured that the subsequently formed difference surface 56 (refer to FIG. 6) does not overlap the difference surface 46. An implantable element that is similar to that of the first pre-amorphization implant can be selected. When implantation is performed, the implantation energy is between 15 keV and 50 keV, and the implantation amount can be between about 1×10 ¹⁴ /cm ² and 1×10 ¹⁵ /cm ² when the semiconductor substrate 102 is between -60 ° C and Embedding was performed at a temperature of -100 °C.

FIG. 6 depicts the formation of a second strained cap layer 54 that is substantially identical to the strained cap layer 42 in that the candidate material of the strained cap layer 54 is formed. After the strained cap layer 54 is formed, a second annealing is performed. Similarly, as shown in Figure 3, the second anneal is essentially the same as the first anneal. Due to the second annealing, recrystallization occurs in the pre-amorphization implant region 50, and a poor discharge surface 56 is formed. During this period, since the second pre-amorphization implant does not destroy the crystal structure of the bottom portion 46A of the difference drain surface 46, the crystal structure of the broken portion located in the difference discharge surface 46 is re-established in the pre-amorphization implant region 50. Upon growth, the pre-amorphization implant region 50 is again converted into a crystalline structure. As shown in Figure 6, the final structure, the two differential faces 46 and 56 coexist and In parallel, the differential face 56 is located outside of the corresponding differential face 46. Moreover, the pinch lines 48 and 58 of the corresponding differential faces 46 and 56 are higher than the upper surface 24B of the shallow trench isolation regions of the shallow trench isolation region. Alternatively, the pinch lines 48 and 58 may be higher than the bottom of the corresponding fin structure 20, and the bottom of the fin structure is at the same level as the shallow trench isolation region recess upper surface 24B of the shallow trench isolation region 24.

Next, as shown in FIG. 7, an etching step is performed to remove the horizontal portion of the strained cap layer 54, however, the vertical portions of some of the strained cap layers 54 remain on the offset spacers 49 to form the offset spacers 59. Subsequent process steps, as shown in FIG. 8, a third pre-amorphization implant 62 is formed to form a third pre-amorphization implant region 60, and the third pre-amorphization implant is substantially the same as the fifth The second pre-amorphization implant of the figure is the same. Again, both of the differential faces 46 and 56 have a bottom portion of the non-overlapping pre-amorphization implant region 60, and the third pre-amorphization implant 62 does not break the bottom portions of the differential faces 46 and 56. Crystal structure. The process details of the third pre-amorphization implant 62 can be substantially the same as the second pre-amorphization implant 52 (see Figure 5). Due to the addition of the offset spacers 49 and 59, the pre-amorphization implant region 60 is further away from the gate electrode 22 than the pre-amorphization implant region 50 (see FIG. 5), and the pitch S3 is greater than that of the second and fifth, respectively. The spacings S1 and S2 shown in the figure.

Referring to FIG. 9, a third strained cap layer 64 is formed, and then a difference discharge surface 66 is formed on the outer sides of the difference rows 46 and 56 by a third annealing step. Moreover, the differential rows 46, 56 and 66 are parallel to each other, and the pinch line 68 of the differential face 66 can be higher than the recessed upper surface 24B of the shallow trench isolation region 24.

The formation of the differential faces 46, 56, and 66 can cause an increase in tensile stress in the channel region 23 of the MOSFET 100. Simulation to investigate the channel stress and the number of differential rows in a metal oxide semiconductor device Therefore, the results show that the channel stress of the MOSFET having the two-difference row (on each side of the gate electrode 22) is 1.5 times that of the MOSFET having a difference between the MOSFETs The channel stress of the metal-oxide-semiconductor field-effect transistor having a three-difference surface is 1.7 times that of the metal-oxide-semiconductor field-effect transistor having a two-difference surface. Therefore, the more differential planes formed can effectively increase the channel stress of the corresponding metal oxide semiconductor field effect transistor.

Figures 2 through 9 illustrate the formation of a metal oxide semiconductor field effect transistor having a three-difference row. In other embodiments, a metal oxide semiconductor field effect transistor can have two different rows or more than three different rows on each side of the gate electrode.

Referring to FIG. 10, the strain cap layer 64 and the offset spacers 49 and 59 are removed. For example, when the strained cap layer 64 and the offset spacers 49 and 59 contain tantalum nitride, the offset spacers 49 and 59 are removed using phosphoric acid (H ₃ PO ₄ ), and the source/germination is also formed by implantation. The polar region 110 is epitaxially grown over the upper surface of the source/drain region 110 to form a semiconductor epitaxial layer 70. In one embodiment, the semiconductor epitaxial layer 70 comprises tantalum, tantalum phosphide, silicon carbon phosphorus, or the like.

Next, as shown in Fig. 11, a metal deuteration process is performed to form a metal antimony compound region 72. In one embodiment, the upper portion of the semiconductor epitaxial layer 70 is consumed in the metal deuteration process, while the underlying portion of the semiconductor epitaxial layer 70 is not consumed in the metal deuteration process. Therefore, the bottom surface of the final metal tantalum compound region 72 is higher than the upper surface of the channel region 23 of the metal oxide semiconductor field effect transistor 100. The simulation results show that when the bottom surface of the metal germanium compound region 72 is higher than the upper surface of the channel region 23, the metal oxide semiconductor field effect transistor 100 can be lifted. The current is driven, and when the bottom surface of the metal ruthenium compound region is higher, the degree of lift increases.

Figure 12 is a diagram showing an exemplary flow chart for forming a difference row. First, a main offset spacer is formed (step 120), and step 120 in FIG. 12 may correspond to the step shown in FIG. 2, and then the formation of the differential layout is performed according to steps 122, 124, and 126. In step 122, a pre-amorphization implant is performed, followed by stress film deposition and annealing to form the drains as in steps 124 and 126. Steps 122, 124, and 126 may correspond to the steps shown in FIGS. 2 through 4. Next, the stress film is etched to enlarge the size of the offset spacer. This step may correspond to the etching step of FIG. A second difference row is produced by steps 130, 132, 134, and 136. In step 130, an additional pre-amorphization implant is performed, followed by additional stress film deposition and annealing to form the drain ( Steps 132 and 134). In step 136, an additional stress film is etched to enlarge the size of the offset spacer. Steps 130, 132, 134, and 136 may correspond to the steps shown in FIGS. 5-7, and step 130 may be repeated or repeated a plurality of times. 132, 134 and 136. For example, the exemplary steps illustrated in Figures 8 and 9 are repeated steps 130, 132, 134, and 136. Step 138 depicts the offset spacers that remove film stress and selectivity. Step 138 corresponds to the illustrative steps shown in FIG.

13 through 21C are schematic cross-sectional views showing an intermediate stage of forming a metal oxide semiconductor field effect transistor according to another embodiment. Unless otherwise indicated, the materials and forming methods of the components in these embodiments are essentially the same as those shown in Figures 1 through 12 and are labeled with the same reference numerals. Details of the materials for forming the process and components shown in Figures 13 through 21C can be found in the examples discussed in Figures 1 through 12.

The initial structure and formation steps of these embodiments are essentially the same as shown in FIG. 2, forming a pre-amorphization implant region 40. Next, FIG. 13 depicts the formation of the first strained cap layer 42. The material of the strained cap layer 42 may include tantalum nitride, titanium nitride, nitrogen oxides, oxides, antimony, antimony carbide, antimony oxynitride, and combinations thereof. The strained cap layer 42 also includes hydrogen in addition to other materials. For example, the strained cap layer 42 can be a hydrogen-containing tantalum nitride, a hydrogen-containing titanium nitride, a hydrogen-containing nitrogen oxide, a hydrogen-containing oxide, a hydrogen-containing ruthenium, and a A tantalum carbide of hydrogen, a hydrogen-containing bismuth oxynitride, and combinations thereof or a multilayer composed thereof.

In the fabrication of the hydrogen-containing strained cap layer 42, hydrogen is included as a process gas in addition to other process gases. For example, when the strained cap layer 42 includes tantalum nitride, the process gas may include decane (SiH ₄ ) (or SiCl ₄ ), ammonia (NH ₃ ), and hydrogen, and the deposition temperature may be between about 400 ° C and 500 ° C. The process gas has a pressure of about 1 torr to 15 torr, and the final strained cap layer 42 thus includes hydrogen therein. In some exemplary embodiments, to increase the concentration of hydrogen in the hydrogen-containing strained cap layer 42, the hydrogen flow rate in the strained cap layer 42 is greater than about 100 sccm. In other embodiments, a strained cap layer 42 is formed first, and the strained cap layer 42 can be hydrogen free or hydrogen containing. After the strained cap layer 42 is formed, an additional diffusion process is performed to incorporate (more) hydrogen into the strained cap layer 42 to further increase the hydrogen concentration in the strained cap layer 42. In the final hydrogen-containing strain cap layer 42, the concentration of hydrogen gas may be greater than 1 × 10 ¹⁹ /cm ³ , greater than 1 × 10 ²⁰ /cm ³ or greater than 5 × 10 ²⁰ /cm ³ .

An annealing process is then performed, for example, using rapid thermal annealing, rapid thermal annealing, or other annealing methods, and the annealing temperature can be between about 400 ° C and 500 ° C. Annealing can be carried out in a process environment such as introduction of oxygen, nitrogen, hydrogen or the like, and the process gas pressure is from about 1 torr to 15 torr. again In the annealing, the hydrogen-containing strain cap layer 42 is exposed to ultraviolet light (UV). Due to the annealing, the pre-amorphization implanted region 40 shown in Fig. 2 is recrystallized by the memory stress obtained from the strained cap layer 42. Therefore, the semiconductor substrate 102 can provide a stress region to the channel region 23 of the final metal oxide semiconductor field effect transistor 100 to improve the driving current of the metal oxide semiconductor field effect transistor 100.

Due to the annealing, a differential face 46 is formed. According to some embodiments, hydrogen is outgassed from the hydrogen-containing strain cap layer 42 during the annealing process due to the formation of the hydrogen-containing strain cap layer 42. For example, ultraviolet light helps with outgassing. This causes the solid phase epitaxial-Phase Regrowth (SPER) to grow at different crystal planes differently than the growth rate of the embodiment of FIG. 3, for example, as shown in the embodiment of FIG. The growth rate of the (100) plane of the substrate 102 can be greater than the growth rate of the (110) plane of the semiconductor substrate 102, resulting in a relatively large angle β of the differential face 46, which can be about 55 degrees. In the embodiment shown in Fig. 13, the growth rate of the (100) plane of the semiconductor substrate 102 is lowered. For example, less than the growth rate of the (110) plane of the semiconductor substrate 102, the angle γ (see FIG. 13) of the differential face 46 is relatively small (less than about 65 degrees). In some embodiments, the angle γ is less than about 45 degrees and ranges from about 0 to 45 degrees, and the angle γ can also range from about 20 to 40 degrees. In some exemplary embodiments, the angle γ is approximately 35 degrees. Advantageously, a small angle γ results in a greater stress being provided to the channel region 23. Therefore, it is desirable to reduce the angle γ of the differential face 46.

The bottom point 48 of the differential face 46 may be higher than the recessed upper surface 24B of the shallow trench isolation region 24, minimizing the effect of the shallow trench isolation region 24 providing unfavorable compressive stress to the channel region 23. The bottom point 48 extends from the Y direction of Fig. 1 to form a line, and is hereinafter referred to as a pinch line 48.

Next, as shown in Fig. 14, an etching step is performed to remove the horizontal portion of the strained cap layer 42, however, some of the vertical portions of the strained cap layer 42 remain offset to form the offset spacers 49. Again, if the primary offset spacer 30 is not formed, the offset spacer 49 is located on the sidewall of the gate electrode 22. It may be noted that the remaining portion of the strained cap layer 42 may also include (or not include) portions on the sidewalls of the substrate 102 and the shallow trench isolation regions 24, and these portions are not shown in the figures.

Figure 15 depicts a second pre-amorphization implant region 50 formed via a second pre-amorphization implant and depicts the pre-amorphization implant at arrow 52. The second pre-amorphization implant is performed with the offset spacers 49 blocking some of the implant elements. Therefore, the gate electrode 22 is far from the inner edge 50A of the pre-amorphization implant region 50 with respect to the pre-amorphization implant region 40 (please refer to FIG. 2). Alternatively, the horizontal pitch S2 (refer to Fig. 15), that is, the distance between the inner edge of the pre-amorphization implant region 50 and the edge of the closest gate electrode 22 is larger than the horizontal pitch S1 of Fig. 2. Furthermore, by having the pre-amorphization implant region 50 shallower than the pinch line 48, it is achieved that at least one bottom portion 46A of each of the difference rows 46 is not located inside the newly formed pre-amorphization implant region 50, Alternatively, as depicted in FIG. 5, the pre-amorphization implant region 50 can be moved away from the gate electrode 22 by using the offset spacers 49 formed by the second pre-amorphization implant. Since the pre-amorphous phased implant region 50 is an amorphous region, the crystal structure of the partial difference surface 46 overlapping the pre-amorphization implant region 50 is destroyed. Referring to Figure 5, the implant process can be similar to the implant process discussed.

FIG. 16A depicts the fabrication of a second strained cap layer 54 that is substantially identical to the strained cap layer 42 in that the candidate material of the strained cap layer 54 is formed. According to some embodiments, the strained cap layer 54 includes hydrogen gas that can be formed in the strained cap layer 54 when Joined in / or after. In other embodiments, the strained cap layer 54 is free of hydrogen or substantially free of hydrogen.

After the strained cap layer 54 is formed, a second annealing is performed. Likewise, the second anneal may use process conditions that are essentially the same as the first anneal in FIG. 13 or use process conditions different from the first anneal. Due to the second annealing, recrystallization occurs in the pre-amorphization implant region 50 to form a differential face 56. During this period, since the second pre-amorphous phase implantation does not break the bottom portion 46A of the differential surface 46, the damaged portion of the differential surface 46 re-grows in the pre-amorphous phased implant region 50, and is again transformed. Formed into a crystalline zone. As with the final configuration shown in FIG. 16A, the two differential rows 46 and 56 coexist and are parallel to each other, and the differential face 56 is located outside the corresponding differential face 46. Moreover, the pinch lines 48 and 58 of the corresponding differential faces 46 and 56 are higher than the recessed shallow trench isolation region upper surface 24B of the shallow trench isolation region 24. Alternatively, the pinch lines 48 and 58 may be higher than the bottom of the corresponding fin structure 20, and the bottom of the fin structure is at the same level as the shallow trench isolation region recess upper surface 24B of the shallow trench isolation region 24.

In accordance with some embodiments in which the strained cap layer 54 is a hydrogen-containing film layer, the resulting differential face 56 has an angle of inclination γ that may be the same or different than the angle γ of the facet 46. Thus, the differential face 46 can be parallel or non-parallel to the corresponding difference face 56. In other embodiments, as shown in FIG. 16B, the difference face 56 may have an angle θ that is greater than the angle γ. In some embodiments, the angle θ is equal to the angle β shown in FIG. The difference between the angle θ and the angle γ can be obtained by making the corresponding strained cap layer 54 not include hydrogen or substantially not including hydrogen.

FIG. 16C is a schematic cross-sectional view showing another embodiment in which the inclination angle of the difference discharge surface 56 is smaller than the inclination angle of the difference discharge surface 46. According to some exemplary In the embodiment, the inclination angle of the difference discharge surface 56 is γ, and the inclination angle of the difference discharge surface 46 is β. In these embodiments, the differential face 56 may or may not contact the differential face 46.

Next, as shown in Fig. 17, an etching step is performed, thereby removing the horizontal portion of the strained cap layer 54, and some vertical portions of the strained cap layer 54 remain on the offset spacers 49 to form the offset spacers 59. A third pre-amorphization implant 62 is formed to form a third pre-amorphization implant region 60, as shown in Fig. 18, and the third pre-amorphization implant is substantially the same as the fifteenth The second pre-amorphization implant of the figure is the same. Again, both of the differential faces 46 and 56 have a bottom portion of the non-overlapping pre-amorphization implant region 60, and the third pre-amorphization implant 62 does not break the bottom portions of the differential faces 46 and 56. Crystal structure. The process details of the third pre-amorphization implant 62 may be substantially the same as the second pre-amorphization implant 52 (see Figure 15).

Due to the addition of the offset spacers 49 and 59, the pre-amorphization implant region 60 is further away from the gate electrode 22 than the pre-amorphization implant region 50 (refer to FIG. 5), and the pitch S3 is greater than the pitches S1 and S2, respectively As shown in Figures 2 and 15.

Referring to Figure 19, a third strained cap layer 64 is formed, followed by a third annealing step to form a differential face 66 on the outside of the differential faces 46 and 56. Furthermore, the differential faces 46, 56 and 66 may be parallel or non-parallel to one another. The pinch line 68 of the differential face 66 may be higher than the recessed upper surface 24B of the shallow trench isolation region 24. According to some embodiments, the strained cap layer 64 is hydrogen-containing, and in other embodiments, the strained cap layer 64 is hydrogen free. As such, the angle of the strained cap layer 64 can range from about 45 to 90 degrees or from 0 to 45 degrees.

Referring to FIG. 20, the strain cap layer 64 and the offset spacers 49 and 59 are removed, and then epitaxial growth is performed over the upper surface of the source/drain region 110 to form the semiconductor epitaxial layer 70. The source/drain region 110 can also be formed by implantation. Difference The faces 46, 56, and 66 may be grown in the semiconductor epitaxial layer 70, and the semiconductor epitaxial layer 70 may include tantalum, tantalum phosphide, silicon carbon phosphorus, or the like.

Next, as shown in FIGS. 21A, 21B, and 21C, a metal deuteration process is performed to form the metal germanium compound region 72, and the metal germanium process and individual details are essentially the same as those of the embodiment of FIG. 11 and are not repeated here.

21A, 21B, and 21C are diagrams depicting various embodiments, each of which may have its own angle of inclination (such as β, γ, and θ), and the angles of inclination of the difference planes may be the same or different from each other by adjusting The hydrogen concentration of the individual strain cap layers can be obtained at different angles, and the higher the hydrogen concentration, the smaller the tilt angle. Furthermore, in order to reduce the tilt angle, it is necessary to achieve a specific hydrogen content. For example, Figure 21A shows that the differential faces 46, 56 and 66 have the same angle of inclination γ. In other embodiments, as shown in FIG. 21B, the difference face 46 has a smaller angle of inclination (such as y) than the angle of inclination of the outer facets 56 and 66 (such as β). In still another embodiment, as shown in Fig. 21C, the difference face 46 has a larger inclination angle (e.g., β) than the inclination angle (e.g., γ) of the outer difference faces 56 and 66. According to some embodiments, as shown in FIG. 21C, the outer differential face (such as the difference face 56 or 66) may contact the inner face (such as the face 46 or 56). In other embodiments, although the outer differential face angle is smaller than the inner difference face, the outer difference face does not contact the inner face.

Embodiments herein have some advantageous features in that the strain in the channel region of the MOSFET is increased by the formation of a plurality of differential rows. Since the strained cap layer also serves as a spacer to define the position of the differential face, the manufacturing according to the above embodiment is inexpensive. In addition, hydrogen can be incorporated into the strained cap layer. Reducing the tilt angle of the differential facets results in more strain in the channel region of the MOSFET.

A method of fabricating a semiconductor device according to some embodiments of the present invention includes forming a metal oxide semiconductor field effect transistor, comprising performing a first implant to form a first pre-amorphization implant region adjacent to the metal oxide a gate electrode of the semiconductor field effect transistor; forming a first strain cap layer on the first pre-amorphization implant region; and performing a first strain cap layer and the first pre-amorphization implant region An annealing is performed to form a first difference surface, wherein the first difference surface is formed by the first annealing, and the first difference mask has an inclination angle of less than 65 degrees.

A method of fabricating a semiconductor device according to another embodiment of the present invention includes performing a first implant to form a first pre-amorphization implant region adjacent to a gate electrode of a metal oxide semiconductor field effect transistor; Forming a first strained cap layer on the first pre-amorphization implant region, and forming hydrogen as the process gas when forming the first strained cap layer; and topping the first pre-amorphized implant on the first strained cap layer The first region is subjected to a first annealing to form a first difference surface, wherein the first difference surface is formed by the first annealing.

A semiconductor device according to still another embodiment of the present invention includes a metal oxide semiconductor field effect transistor including a semiconductor region; a gate electrode including a portion on the semiconductor region; and a first difference surface adjacent to The gate electrode is located in the semiconductor region, wherein the first row mask has an angle of inclination of less than 65 degrees.

The features of many embodiments are described above to enable those skilled in the art to clearly understand the following description. Those of ordinary skill in the art will understand that they can utilize the disclosure of the present invention as a basis for Designing or modifying other processes and structures accomplishes the same objectives as above and/or achieves the same advantages as the above-described embodiments. It is also to be understood by those skilled in the art that <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

120, 122, 124, 126, 128, 130, 132, 134, 136, 138 ‧ ‧ steps

Claims (10)

A method of fabricating a semiconductor device, comprising: forming a metal oxide semiconductor field effect transistor, comprising: performing a first implant to form a first pre-amorphization implant region adjacent to the metal oxide semiconductor field effect a gate electrode of the transistor; forming a first strain cap layer on the first pre-amorphization implant region; and performing a first step on the first strain cap layer and the first pre-amorphization implant region An annealing to form a first difference surface, wherein the first difference surface is formed by the first annealing, and the first difference mask has an inclination angle of less than 65 degrees. The method of manufacturing a semiconductor device according to claim 1, wherein when the first strained cap layer is formed, hydrogen is added as a process gas. The method of fabricating a semiconductor device according to claim 1, further comprising forming a gate electrode adjacent to the metal oxide semiconductor field effect transistor, wherein the first and the first The second difference row is located on the same side of the gate electrode and extends into the source/drain region of the MOSFET, and wherein the second difference is formed after the first difference surface is formed And the first and second difference rows are parallel or non-parallel to each other. The method of fabricating a semiconductor device according to claim 3, wherein the forming the second difference surface comprises: etching the first strained cap layer to remove a horizontal portion of the first strained cap layer, wherein adjacent to the A vertical portion of the first strained cap layer of the gate electrode is maintained unetched to form an offset spacer; after the etching is performed, a second implant is performed to form a second pre-amorphized implanted phase Adjacent to the gate electrode; Forming a second strained cap layer covering the second pre-amorphization implanted region; and performing a second annealing on the second strained cap layer and the second pre-amorphized implanted region, wherein the second differential row The surface is formed by the second annealing. The method for fabricating a semiconductor device according to claim 1, further comprising: performing an epitaxial growth to form a semiconductor epitaxial layer on the metal oxide semiconductor field after the first difference surface is formed; a source/drain region of the crystal; performing a deuteration process to form a germanium compound region over the source/drain region, wherein an upper portion of the semiconductor epitaxial layer is consumed in the deuteration process, and Not consuming a bottom portion of the epitaxial layer of the semiconductor; and etching a shallow trench isolation region adjacent to the MOSFET to form a recess adjacent to the MOSFET, The shallow trench isolation region has a recessed upper surface under the recess, and a pinch line of the first difference row is higher than the recessed upper surface of the shallow trench isolation region. A method of fabricating a semiconductor device, comprising: forming a metal oxide semiconductor field effect transistor, comprising: performing a first implant to form a first pre-amorphization implant region adjacent to the metal oxide semiconductor field effect a gate electrode of the transistor; forming a first strain cap layer on the first pre-amorphization implant region, and forming the first strain cap layer, using hydrogen as a process gas; and the first strain Performing a first annealing on the first pre-amorphization implant region over the cap layer to form a first difference surface, wherein the first difference surface is due to the first retreat Formed by fire. The method of manufacturing a semiconductor device according to claim 6, further comprising: performing a second implant to form a second pre-amorphization implant region adjacent to the gate electrode; forming a second strain a capping layer on the second pre-amorphization implant region, wherein hydrogen is added as a process gas when forming the second strain cap layer; and the second pre-amorphization implant is over the second strain cap layer Forming a second annealing to form a second difference surface, wherein the second difference surface is formed by the second annealing, and the second difference surface is further away from the metal oxidation than the first difference surface A channel region of a semiconductor field effect transistor. The method of fabricating a semiconductor device according to claim 6, further comprising etching a shallow trench isolation (STI) region adjacent to the metal oxide semiconductor field effect transistor to form a recess adjacent to the metal oxide The semiconductor field effect transistor, wherein the shallow trench isolation region has a recessed upper surface under the recess, and a pinch line of the first difference surface is higher than the recess upper surface of the shallow trench isolation region. A semiconductor device comprising: a metal oxide semiconductor field effect transistor comprising: a semiconductor region; a gate electrode including a portion on the semiconductor region; and a first difference surface adjacent to the gate electrode And located in the semiconductor region, wherein the first difference mask has an inclination angle of less than 65 degrees. The semiconductor device according to claim 9 of the patent application, further comprising a second difference The row is adjacent to the gate electrode and is located in the semiconductor region, wherein the first and second difference faces are not parallel or in contact with each other.