CN104517846B - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
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- CN104517846B CN104517846B CN201310459557.7A CN201310459557A CN104517846B CN 104517846 B CN104517846 B CN 104517846B CN 201310459557 A CN201310459557 A CN 201310459557A CN 104517846 B CN104517846 B CN 104517846B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 150000002500 ions Chemical class 0.000 claims abstract description 47
- 238000000137 annealing Methods 0.000 claims abstract description 33
- 239000011248 coating agent Substances 0.000 claims abstract description 25
- 238000000576 coating method Methods 0.000 claims abstract description 25
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 35
- 238000002347 injection Methods 0.000 claims description 19
- 239000007924 injection Substances 0.000 claims description 19
- 238000002513 implantation Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- 238000005224 laser annealing Methods 0.000 claims description 6
- 229910001432 tin ion Inorganic materials 0.000 claims description 4
- -1 germanium ion Chemical class 0.000 claims description 2
- 230000009471 action Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 239000000470 constituent Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, including：Semiconductor substrate is provided, gate structure is formed on a semiconductor substrate, source/drain region is formed in the Semiconductor substrate of gate structure both sides；The first ion implanting and the first annealing are performed successively, to form dislocation in source/drain region；The second ion implanting is performed, so that source/drain region is in amorphous state；Form covering gate structure and the stress coating of Semiconductor substrate；The second annealing is performed, the tensile stress that stress coating has is transferred to the channel region of Semiconductor substrate；De-stress coating is removed, and self-aligned silicide is formed on source/drain region；Being formed has adjustable heavily stressed contact etch stop layer.According to the present invention, dislocation is formed in source/drain region by the first ion implanting and is formed with adjustable heavily stressed contact etch stop layer come the stability of the tensile stress of channel region of the castering action in NMOS, so as to significantly increase the channel region carrier mobility of NMOS.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of channel region carrier mobility for improving NMOS
Method.
Background technology
When the node of semiconductor fabrication process reach 90nm and it is following when, stress technique（Stress Engineering）Quilt
It is widely used to improve the carrier mobility in semiconductor device channel area.
For CMOS, after implementing source/drain region injection, dual stressed layers are formed usually on its substrate to improve its ditch
Carrier mobility in road area, wherein, tensile stress layer is used to improve the electron mobility in NMOS channel regions, and compressive stress layer is used
In improving the hole mobility in PMOS channel regions.However, when forming the dual stressed layers, the drawing of the dual stressed layers is formed
There are overlapped parts in the intersection of the two for stressor layers and compressive stress layer.The overlapped part will generate one
Boundary Nearest effect, the effect are remarkably decreased the carrier mobility caused in channel region.It is meanwhile described overlapped
Part will also cause a degree of puzzlement to the implementation of subsequent contact etch technique.If form single tensile stress
Layer while then promoting the electron mobility in NMOS channel regions, reduces the hole mobility in PMOS channel regions.
After implementing to anneal and removing above-mentioned stressor layers, self-aligned silicide is formed on source/drain region, then, in substrate
It is upper to form the contact etch stop layer with different stress characteristics.Due to the presence of self-aligned silicide, it is impossible to implement high temperature
Annealing is with by stress transfer possessed by contact etch stop layer to channel region, and then the effect of influence stress memory.
It is, therefore, desirable to provide a kind of method, to solve the problems, such as that above-mentioned stress memory process exists.
Invention content
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, including：Semiconductor is provided
Substrate is formed with gate structure on the semiconductor substrate, is formed in the Semiconductor substrate of the gate structure both sides
Source/drain region；The first ion implanting and the first annealing are performed successively, to form dislocation in the source/drain region；Perform the second ion
Injection, so that the source/drain region is in amorphous state；Form the stress covering for covering the gate structure and the Semiconductor substrate
Layer；The second annealing is performed, the tensile stress that the stress coating has is transferred to the channel region of the Semiconductor substrate.
Further, the injection ion of first ion implanting is tin ion, is performed in two steps：The first step, it is described from
For the incident direction of son injection perpendicular to the surface of the Semiconductor substrate, implantation dosage is 3.0 × e14-1.0×e15Ion/flat
Square centimetre, Implantation Energy 40-100keV；Second step, the incident direction of the ion implanting is relative to the Semiconductor substrate
Surface the angle of cut for 7-35 degree, implantation dosage is 5.0 × e14-1.5×e15Ion/square centimeter, Implantation Energy 60-
200keV。
Further, the order for performing the first step and the second step exchanges.
Further, described first peak value annealing or laser annealing are annealed into.
Further, the temperature of the peak value annealing is 900-1100 DEG C, duration 10-60s；The laser annealing
Temperature is 1200-1350 DEG C, duration 20-80ms.
Further, the injection ion of second ion implanting is germanium ion, and one step of ion implanting is completed, incident
Direction is 0-15 degree relative to the angle of cut on the surface of the Semiconductor substrate, and implantation dosage is 5.0 × e14-1.0×e15Ion/
Square centimeter, Implantation Energy 20-40keV.
Further, the thickness of the stress coating is 10-100nm.
Further, described second peak value annealing or instantaneous annealing are annealed into.
Further, the temperature of the peak value annealing is 950-1100 DEG C, duration 20-60s；The instantaneous annealing
Temperature is 1000-1350 DEG C, duration 10-300ms.
Further, after the described second annealing, following step is further included：The stress coating is removed, and described
Self-aligned silicide is formed on source/drain region；It is formed and covers the gate structure, the self-aligned silicide and semiconductor lining
Bottom has adjustable heavily stressed contact etch stop layer.
Further, the material of the contact etch stop layer is TaCxNyOr TiCxNy, wherein, the numberical range of x is
The numberical range of 0.01-0.2, y are 0.05-0.3.
Further, the semiconductor devices is NMOS.
Further, the gate structure includes the gate dielectric being laminated from bottom to top and gate material layers.
According to the present invention, institute's rheme is formed in the source/drain region of the Semiconductor substrate by first ion implanting
Wrong and formation is described to carry out castering action in the raceway groove of the NMOS with adjustable heavily stressed contact etch stop layer
The stability of the tensile stress in area, so as to significantly increase the channel region carrier mobility of the NMOS.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
The device that the step of Figure 1A-Fig. 1 G is implement according to the method for exemplary embodiment of the present successively obtains respectively
Schematic cross sectional view；
Fig. 2 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Raising NMOS channel region carrier mobility method.Obviously, execution of the invention is not limited to semiconductor applications
The specific details that technical staff is familiar with.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiment.
It should be understood that it when the term " comprising " and/or " including " is used in this specification, indicates described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combination thereof.
[exemplary embodiment]
In the following, the ditch that method according to an exemplary embodiment of the present invention improves NMOS is described with reference to Figure 1A-Fig. 1 G and Fig. 2
The detailed step of road area carrier mobility.
With reference to Figure 1A-Fig. 1 G, method according to an exemplary embodiment of the present invention is shown and implements the step of institute successively
The schematic cross sectional view of the device obtained respectively.
First, as shown in Figure 1A, Semiconductor substrate 100 is provided, the constituent material of Semiconductor substrate 100, which may be used, not to be mixed
Miscellaneous monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator（SOI）, silicon is laminated on insulator（SSOI）, insulator upper strata
Folded SiGe（S-SiGeOI）, germanium on insulator SiClx（SiGeOI）And germanium on insulator（GeOI）Deng.As an example, at this
In embodiment, the constituent material of Semiconductor substrate 100 selects monocrystalline silicon.Isolation structure is formed in Semiconductor substrate 100
101, as an example, isolation structure 101 is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.
In the present embodiment, isolation structure 101 divides Semiconductor substrate 100 for NMOS area and PMOS areas, only shows NMOS area in the example shown.
Various traps (well) structure is also formed in Semiconductor substrate 100, to put it more simply, being omitted in diagram.
It is formed with gate structure 102 on a semiconductor substrate 100, as an example, gate structure is included from bottom to top successively
The gate dielectric 102a of stacking and gate material layers 102b.Gate dielectric 102a includes oxide skin(coating), such as silica
（SiO2）Layer.Gate material layers 102b includes polysilicon layer, metal layer, conductive metal nitride layer, conductive metal oxidation
It is one or more in nitride layer and metal silicide layer, wherein, the constituent material of metal layer can be tungsten（W）, nickel（Ni）Or titanium
（Ti）；Conductive metal nitride layer includes titanium nitride（TiN）Layer；Conductive metal oxide layer includes yttrium oxide（IrO2）
Layer；Metal silicide layer includes titanium silicide（TiSi）Layer.The forming method of gate dielectric 102a and gate material layers 102b can
With any prior art being familiar with using those skilled in the art, preferably chemical vapour deposition technique (CVD), such as cryochemistry gas
Mutually deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhancing
Learn vapor deposition (PECVD).
In addition, as an example, the offset side wall 103 against gate structure 102 is formed in the both sides of gate structure 102.
Offset side wall 103 is made of oxide, nitride or combination, in the present embodiment, the composition material of offset side wall 103
Expect for oxide.The technical process for forming offset side wall 103 is familiar with by those skilled in the art, is not repeated here herein.
Side wall 104 is formed in the both sides of offset side wall 103.The processing step for forming side wall 104 includes：It is served as a contrast in semiconductor
The spacer material layer that gate structure 102 and offset side wall 103 is completely covered, the preferred silicon nitride of constituent material are formed on bottom 100；
It is etched using side wall（blanket etch）The technique etched side walling bed of material, to form side wall 104.
Next, it performs source/drain region injection 105 and anneals, to form source/drain region in Semiconductor substrate 100, for letter
Change, it is illustrated that in omitted.The technique for forming source/drain region 105 is familiar with by those skilled in the art, is no longer gone to live in the household of one's in-laws on getting married herein
It states.In order to reduce heat budget, the annealing performs when can move to subsequent implementation stress memory.Implementing source/drain region injection 105
Before or while, optionally, implement pre-amorphous injection, to reduce short-channel effect.The injection ion of pre-amorphous injection
Including III race such as germanium, carbon and V race's ion.
Then, as shown in Figure 1B, side wall 105 is removed, and performs the first ion implanting 106.In the present embodiment, first from
The injection ion of son injection 106 is tin（Sn）Ion performs in two steps：The first step, the incident direction of the ion implanting are hung down
Directly in the surface of Semiconductor substrate 100, implantation dosage is 3.0 × e14-1.0×e15Ion/square centimeter, Implantation Energy 40-
100keV；Second step, the incident direction of the ion implanting have the angle of cut, the friendship relative to the surface of Semiconductor substrate 100
The preferred 7-35 degree in angle, implantation dosage are 5.0 × e14-1.5×e15Ion/square centimeter, Implantation Energy 60-200keV.It needs
Illustrate, the order for performing the first step and the second step can be interchanged.
Then, as shown in Figure 1 C, the first annealing is performed, to form dislocation 107 in the source/drain region of Semiconductor substrate 100.
By the injection ion of the first ion implanting 106 for for tin ion, dislocation 107 is by tin ion injection region and Semiconductor substrate
What the lattice mismatch defect that the interface between the silicon in 100 generates was formed, it can significantly increase and act on Semiconductor substrate
The stress of 100 channel region.After performing the first ion implanting 106, in amorphous state, cell volume increases the silicon in ion implanted region
Greatly（Amplitude is about 6-8%）；After performing the first annealing, the silicon in ion implanted region is again crystallization, and cell volume restores
State to before the first ion implanting 106 of execution, the variation of above-mentioned silicon crystal lattice volume lead to the production of the lattice mismatch defect
It is raw.In the present embodiment, described first peak value annealing or laser annealing are annealed into.The temperature of the peak value annealing is 900-1100
DEG C, duration 10-60s；The temperature of the laser annealing is 1200-1350 DEG C, duration 20-80ms.
Then, as shown in figure iD, the second ion implanting 108 is performed, so that the source/drain region is in amorphous state.In this implementation
In example, the injection ion of the second ion implanting 108 is germanium（Ge）Ion, one step of ion implanting are completed, incident direction phase
The angle of cut for the surface of Semiconductor substrate 100 is 0-15 degree, and implantation dosage is 5.0 × e14-1.0×e15Ion/square li
Rice, Implantation Energy 20-40keV.After performing the second ion implanting 108, the silicon in ion implanted region is brilliant again in amorphous state
Tensile stress caused by the increase of lattice volume is locked by dislocation 107, this process is equivalent to primary stress Memory Process.
Then, as referring to figure 1E, covering gate structure 102 and the stress coating 109 of Semiconductor substrate 100 are formed.
In the present embodiment, stress coating 109 is formed using conformal deposition process, so that the stress coating 109 formed has well
Step coverage characteristics.The size for the stress that stress coating 109 has used by forming stress coating 109 with depositing work
The process conditions of skill are related, are not specifically limited herein, the preferred silicon nitride of constituent material, thickness 10-100nm.It needs
Illustrate, before stress coating 109 is formed, a thin layer oxide skin(coating) can be initially formed, to prevent from subsequently going de-stress
Semiconductor substrate 100 is caused to damage during coating 109, to put it more simply, the oxide thin layer nitride layer is not shown in diagram.
Then, the second annealing is performed, the tensile stress that stress coating 109 has is transferred in Semiconductor substrate 100
Channel region.The transfer of above-mentioned stress realizes that after performing the second annealing, the silicon in ion implanted region is again by dislocation 107
It is crystallization, the tensile stress of the reduction generation of cell volume（Cell volume reduces the tensile stress that 6% induction generates 4GPa）By dislocation
107 lockings.Due to the presence of stress coating 109, the cell volume of the silicon in ion implanted region will not be completely recovered to perform
State before second ion implanting 108.In the present embodiment, described second peak value annealing or instantaneous annealing are annealed into.It is described
The temperature of peak value annealing is 950-1100 DEG C, duration 20-60s；The temperature of the instantaneous annealing is 1000-1350 DEG C,
Duration is 10-300ms.
Then, as shown in fig. 1F, de-stress coating 109 is removed, and is formed on the source/drain region in Semiconductor substrate 100
Self-aligned silicide 110.In the present embodiment, de-stress coating 109 is gone using wet etching process.Form autoregistration silication
The technique of object 110 is known to those skilled in the art, is not repeated here herein.
Then, as shown in Figure 1 G, covering gate structure 102, self-aligned silicide 110 is formed and in Semiconductor substrate 100
Have adjustable heavily stressed contact etch stop layer 111.In the present embodiment, it is connect using conformal deposition process formation
Contact hole etching stopping layer 111, so that the contact etch stop layer 111 formed has good step coverage characteristics.Contact hole
The preferred TaC of material of etching stopping layer 111xNyOr TiCxNy, to enhance the channel region carrier mobility of NMOS and saturation electricity
Stream, wherein, the numberical range of x is 0.01-0.2, and the numberical range of y is 0.05-0.3.
So far, the processing step that method according to an exemplary embodiment of the present invention is implemented is completed, next, can pass through
Subsequent technique completes the making of entire semiconductor devices, including：Interlayer dielectric layer is formed on contact etch stop layer 111,
The contact hole of connection self-aligned silicide 110 is formed in interlayer dielectric layer, filling in the contact hole forms the metal of contact plug
Material etc..According to the present invention, formed in the source/drain region of Semiconductor substrate 100 by the first ion implanting 106 dislocation 107 with
And form the tensile stress for carrying out channel region of the castering action in NMOS with adjustable heavily stressed contact etch stop layer 111
Stability, so as to significantly increase the channel region carrier mobility of NMOS.
With reference to Fig. 2, the channel region carrier that method according to an exemplary embodiment of the present invention improves NMOS is shown
The flow chart of mobility, for schematically illustrating the flow of entire manufacturing process.
In step 201, Semiconductor substrate is provided, is formed with gate structure on a semiconductor substrate, in gate structure two
Source/drain region is formed in the Semiconductor substrate of side；
In step 202, the first ion implanting and the first annealing are performed successively, to form dislocation in source/drain region；
In step 203, the second ion implanting is performed, so that source/drain region is in amorphous state；
In step 204, covering gate structure and the stress coating of Semiconductor substrate are formed；
In step 205, the second annealing is performed, the tensile stress that stress coating has is transferred to Semiconductor substrate
Channel region；
In step 206, stress material layer is removed, and self-aligned silicide is formed on source/drain region；
In step 207, it is adjustable high to form having for covering gate structure, self-aligned silicide and Semiconductor substrate
The contact etch stop layer of stress.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of manufacturing method of semiconductor devices, including：
Semiconductor substrate is provided, gate structure is formed on the semiconductor substrate, in partly leading for the gate structure both sides
Source/drain region is formed in body substrate；
Perform successively the first ion implanting and first annealing, to form dislocation in the source/drain region, wherein, described first from
The injection of son injection performs in two steps：The first step, the incident direction of the ion implanting is perpendicular to the table of the Semiconductor substrate
Face, second step, the incident direction of the ion implanting are 7-35 degree relative to the angle of cut on the surface of the Semiconductor substrate；
The second ion implanting is performed, so that the source/drain region is in amorphous state；
Form the stress coating for covering the gate structure and the Semiconductor substrate；
The second annealing is performed, the tensile stress that the stress coating has is transferred to the channel region of the Semiconductor substrate；
The stress coating is removed, and self-aligned silicide is formed on the source/drain region；
Form the covering gate structure, the self-aligned silicide and the Semiconductor substrate has adjustable high stress
Contact etch stop layer, the material of the contact etch stop layer is TaCxNyOr TiCxNy, wherein, the numerical value model of x
It encloses for 0.01-0.2, the numberical range of y is 0.05-0.3.
2. according to the method described in claim 1, it is characterized in that, the injection ion of first ion implanting be tin ion,
The implantation dosage of the first step is 3.0 × e14-1.0×e15Ion/square centimeter, Implantation Energy 40-100keV；It is described
The implantation dosage of second step is 5.0 × e14-1.5×e15Ion/square centimeter, Implantation Energy 60-200keV.
3. according to the method described in claim 2, it is characterized in that, the order for performing the first step and the second step is mutual
It changes.
4. according to the method described in claim 1, it is characterized in that, described first is annealed into peak value annealing or laser annealing.
5. according to the method described in claim 4, it is characterized in that, the temperature of peak value annealing is 900-1100 DEG C, persistently
Time is 10-60s；The temperature of the laser annealing is 1200-1350 DEG C, duration 20-80ms.
6. according to the method described in claim 1, it is characterized in that, the injection ion of second ion implanting be germanium ion,
Second ion implanting, one step is completed, and incident direction is 0-15 degree relative to the angle of cut on the surface of the Semiconductor substrate,
Implantation dosage is 5.0 × e14-1.0×e15Ion/square centimeter, Implantation Energy 20-40keV.
7. according to the method described in claim 1, it is characterized in that, the thickness of the stress coating is 10-100nm.
8. according to the method described in claim 1, it is characterized in that, described second is annealed into peak value annealing or instantaneous annealing.
9. according to the method described in claim 8, it is characterized in that, the temperature of peak value annealing is 950-1100 DEG C, persistently
Time is 20-60s；The temperature of the instantaneous annealing is 1000-1350 DEG C, duration 10-300ms.
10. according to the method described in claim 1, it is characterized in that, the semiconductor devices is NMOS.
11. according to the method described in claim 1, it is characterized in that, the gate structure includes the grid being laminated from bottom to top
Dielectric layer and gate material layers.
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| CN102403226A (en) * | 2010-09-15 | 2012-04-04 | 中国科学院微电子研究所 | Transistor and method of manufacturing the same |
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