CN105372889A - Display device, COA baseplate and manufacture method for same - Google Patents

Display device, COA baseplate and manufacture method for same Download PDF

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Publication number
CN105372889A
CN105372889A CN201510697888.3A CN201510697888A CN105372889A CN 105372889 A CN105372889 A CN 105372889A CN 201510697888 A CN201510697888 A CN 201510697888A CN 105372889 A CN105372889 A CN 105372889A
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China
Prior art keywords
layer
ito film
film layer
photoresist layer
insulation course
Prior art date
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CN201510697888.3A
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Chinese (zh)
Inventor
武岳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201510697888.3A priority Critical patent/CN105372889A/en
Priority to US14/908,080 priority patent/US9726956B2/en
Priority to PCT/CN2015/099148 priority patent/WO2017067067A1/en
Publication of CN105372889A publication Critical patent/CN105372889A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136222—Colour filters incorporated in the active matrix substrate
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Abstract

The invention discloses a manufacture method of a COA baseplate. The method comprises the steps that a thin film transistor is formed on a substrate baseplate; a second insulating layer is formed on the thin film transistor; a color resistance layer is formed on the second insulating layer; a third insulating layer is formed on the color resistance layer; at least one through hole exposed from a drain electrode of the thin film transistor is formed; an ITO film layer is formed on the third insulating layer; a light resistance layer is formed on the ITO film layer; the light resistance layer on the ITO film layer in a through hole area is treated by light shielding; the light resistance layer on the ITO film layer in a non-through hole area is treated by exposure; and the light resistance layer on the ITO film layer in the through hole area and the light resistance layer on the ITO film layer in the non-through hole area are treated by developing, so that a light resistance layer plug which covers the ITO film layer in the through hole area is obtained. The invention also discloses a display device and the COA baseplate. In this way, according to the method disclosed by the invention, the opening of the through hole can be filled through light resistance; and quality of a panel in a display device can be improved.

Description

Display device, COA substrate and manufacture method thereof
Technical field
The present invention relates to liquid crystal technology field, particularly relate to a kind of display device, COA substrate and manufacture method thereof.
Background technology
The technology that COA (ColorFilteronArray) substrate adopts is by a kind of technology be integrated in by colored filter on array base palte.Compare traditional CF (colored filter) substrate and TFT (thin film transistor (TFT)) substrate to group technique, COA technology provides a kind of mentality of designing reduced to the difficulty of box processing procedure in display panel preparation process.Specifically, in the conventional technology, in order to eliminate grouping error as far as possible, adopt wider black matrix" (BM) shading in the design, and in COA substrate, black matrix" can be designed as narrow linewidth, aperture opening ratio promotes thereupon.In addition, COA substrate adds the distance between pixel electrode and metal routing by color blocking layer, and reduce the capacitance coupling effect between the two, the signal lag effect on metal wire is improved, and panel quality gets a promotion.
But COA substrate, while increasing the distance between metal routing and pixel electrode, also makes pixel electrode and metal routing overlap the increase of difficulty.Specifically, interval dielectric layers and one deck colored filter between pixel electrode and metal routing, need by a very dark via hole overlap joint.In order to prevent pixel electrode break or and metal routing between loose contact, the perforated area of this via hole is larger.In follow-up making, when under liquid crystal drop, liquid crystal is easily assembled at via hole place, causes liquid crystal deflection near via hole not by Control of Voltage, causes display abnormal, affect the quality of the panel of display device.
In sum, be necessary to provide a kind of display device, COA substrate and manufacture method thereof to solve the problem.
Summary of the invention
The technical matters that the present invention mainly solves is to provide a kind of display device, COA substrate and manufacture method thereof, can improve the quality of the panel of display device.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: the manufacture method providing a kind of COA substrate, comprise: on underlay substrate, form thin film transistor (TFT), wherein thin film transistor (TFT) comprises the first metal layer be arranged on underlay substrate, setting the first insulation course on the first metal layer, is arranged on the semiconductor active layer on the first insulation course and is arranged on the second metal level on semiconductor active layer, and the second metal level forms the drain electrode of thin film transistor (TFT); Thin film transistor (TFT) is formed the second insulation course; Form color blocking layer over the second dielectric; Color blocking layer forms the 3rd insulation course; Form at least one via hole exposing the drain electrode of thin film transistor (TFT); The method also comprises: on the 3rd insulation course, form ito film layer, and wherein ito film layer comprises the via area ito film layer be arranged on via hole and the non-via area ito film layer be arranged on outside via hole; Ito film layer forms photoresist layer; Shading treatment is carried out to the photoresist layer on via area ito film layer, and exposure-processed is carried out to the photoresist layer on non-via area ito film layer; Development treatment is carried out to the photoresist layer on the photoresist layer on via area ito film layer and non-via area ito film layer, to obtain covering the photoresist layer stopper on via area ito film layer.
Wherein, non-via area ito film layer comprises routing region ito film layer and non-routing region ito film layer; Carry out exposure-processed to the photoresist layer on non-via area ito film layer to comprise: enter the photoresist layer on the ito film layer of routing region row portiondivide exposure-processed, peel off the photoresist layer on the ito film layer of routing region with part, and complete exposure-processed is carried out to the photoresist layer on the ito film layer of non-routing region, all to peel off the photoresist layer on the ito film layer of non-routing region.
Wherein, the photoresist layer on the ito film layer of routing region is entered row portionpoint exposure-processed comprises: utilize semi-transparent light shield to carry out half exposure-processed to the photoresist layer on the ito film layer of routing region.
Wherein, after carrying out the step of development treatment to the described photoresist layer on described via area ito film layer, the method also comprises: utilize etch process to peel off non-routing region ito film layer.
Wherein, utilize after etch process peels off the step of non-routing region ito film layer, the method also comprises: utilize dry carving technology to process the photoresist layer on the photoresist layer on the ito film layer of routing region and via area ito film layer, all to peel off the photoresist layer on the ito film layer of routing region, part peels off the photoresist layer on via area ito film layer, and photoresist layer stopper is covered on via hole.
Wherein, the lateral vertical underlay substrate of exposed photoresist layer stopper outside via hole.
For solving the problems of the technologies described above, the present invention adopts another technical scheme to be: provide a kind of COA substrate, comprising: underlay substrate; Be arranged on the thin film transistor (TFT) on underlay substrate, wherein thin film transistor (TFT) comprises the first metal layer be arranged on underlay substrate, setting the first insulation course on the first metal layer, is arranged on the semiconductor active layer on the first insulation course and is arranged on the second metal level on semiconductor active layer, and the second metal level forms the drain electrode of thin film transistor (TFT); Be arranged on the second insulation course on thin film transistor (TFT), color blocking layer is over the second dielectric set; Be arranged on the 3rd insulation course on color blocking layer and expose at least one via hole of drain electrode of thin film transistor (TFT); This COA substrate also comprises: be arranged on the ito film layer on the 3rd insulation course, and wherein ito film layer comprises the via area ito film layer be arranged on via hole; Cover the photoresist layer stopper on via area ito film layer.
Wherein, photoresist layer stopper comprises teat and stopper, and stopper is filled in via hole, and teat protrudes from via hole.
Wherein, teat comprises the side of the surface level parallel with underlay substrate and vertical substrates substrate.
For solving the problems of the technologies described above, the present invention adopts another technical scheme to be: provide a kind of display device, this display device comprises the COA substrate of above-mentioned any one.
The invention has the beneficial effects as follows: the situation being different from prior art, the manufacture method of COA substrate of the present invention comprises: on underlay substrate, form thin film transistor (TFT); Thin film transistor (TFT) is formed the second insulation course; Form color blocking layer over the second dielectric; Color blocking layer forms the 3rd insulation course; Form at least one via hole exposing the drain electrode of thin film transistor (TFT); 3rd insulation course forms ito film layer; Ito film layer forms photoresist layer; Shading treatment is carried out to the photoresist layer on via area ito film layer, and exposure-processed is carried out to the photoresist layer on non-via area ito film layer; Development treatment is carried out to the photoresist layer on the photoresist layer on via area ito film layer and non-via area ito film layer, to obtain covering the photoresist layer stopper on via area ito film layer.By the way, the present invention, when not increasing light shield, just carries out the local amendment of ITO light shield, and adopt half exposure technology to make the pixel electrode of COA substrate, and utilize photoresistance to be filled up at the hole of via hole, panel manufacture craft can be optimized, effectively improve panel quality.
Accompanying drawing explanation
fig. 1it is the flow process signal of the manufacture method of COA substrate of the present invention figure;
fig. 2it is the structural representation of COA substrate of the present invention figure;
fig. 3be fig. 2the structure for amplifying signal of first embodiment of middle region A figure;
fig. 4be fig. 2the structure for amplifying signal of second embodiment of middle region A figure.
Embodiment
Below in conjunction with accompanying drawingthe present invention is described in detail with embodiment.
as Fig. 1shown in, fig. 1it is the flow process signal of the manufacture method of COA substrate of the present invention figure.The method comprises the following steps:
Step S101: form thin film transistor (TFT) on underlay substrate.
Wherein, thin film transistor (TFT) comprises the first metal layer be arranged on underlay substrate, setting the first insulation course on the first metal layer, is arranged on the semiconductor active layer on the first insulation course and is arranged on the second metal level on semiconductor active layer.The first metal layer forms the grid of thin film transistor (TFT), and the second metal level forms drain electrode and the source electrode of thin film transistor (TFT).
Step S102: form the second insulation course on thin film transistor (TFT).
Step S103: form color blocking layer over the second dielectric.
Step S104: form the 3rd insulation course on color blocking layer.
Step S105: form at least one via hole exposing the drain electrode of thin film transistor (TFT).
Step S106: form ito film layer on the 3rd insulation course.
Wherein, the ito film layer at via hole place through the 3rd insulation course, color blocking layer is with the second insulation course and be connected with the second metal level signal.Ito film layer comprises the via area ito film layer be arranged on via hole and the non-via area ito film layer be arranged on outside via hole.In the present embodiment, the ito film laminating thickness be attached on the 3rd insulation course is all identical, and the via area ito film layer namely on attaching via hole is of uniform thickness with the non-via area ito film layer be attached to outside via hole.
Step S107: form photoresist layer on ito film layer.
Wherein, photoresist layer is filled on via hole.Should be understood that the present invention is not limited on ito film layer and form photoresist layer, other materials layer can also formed on ito film layer, as long as all material that can be filled on ito film layer can.But, ito film layer is formed other materials layer, namely needs the processing procedure again making many other materials layers, the manufacturing process making COA substrate can be increased, strengthen design cost.On the contrary, the processing procedure forming photoresist layer is ripe in liquid crystal technology field, and the present invention directly can adopt the processing procedure making photoresist layer, can reduce the manufacturing process making COA substrate, reduces design cost.
Step S108: shading treatment is carried out to the photoresist layer on via area ito film layer, and exposure-processed is carried out to the photoresist layer on non-via area ito film layer.
In step S108, non-via area ito film layer comprises routing region ito film layer and non-routing region ito film layer, enters the photoresist layer on the ito film layer of routing region row portiondivide exposure-processed, and complete exposure-processed is carried out to the photoresist layer on the ito film layer of non-routing region.
Particularly, light tight light shield is utilized to carry out shading treatment to the photoresist layer on via area ito film layer, to keep the thickness of the photoresist layer on via area ito film layer constant.Utilize semi-transparent light shield to carry out half exposure-processed to the photoresist layer on the ito film layer of routing region, peel off the photoresist layer on the ito film layer of routing region with part, namely reduce the thickness of the photoresist layer on the ito film layer of routing region.Complete printing opacity light shield is utilized to carry out complete exposure-processed to the photoresist layer on the ito film layer of non-routing region, all to peel off the described photoresist layer on the ito film layer of non-routing region.
That is, after execution of step S108, the thickness of the photoresist layer on via area ito film layer remains unchanged, the photoresist layer on the ito film layer of routing region thinning, and the photoresist layer on the ito film layer of non-routing region is all peeled off.
Should understand, when utilizing semi-transparent light shield to process the photoresist layer on the ito film layer of routing region, by controlling the penetrating light intensity of light shield, can change the thickness of the photoresist layer on the ito film layer of routing region, be preferably the half of original thickness by the thickness decrease of the photoresist layer on the ito film layer of routing region.Certainly, can according to actual needs, control the penetrating light intensity of light shield, by the thickness decrease of the photoresist layer on the ito film layer of routing region be original thickness 1/3rd, 1/4th or three/second-class.
Step S109: development treatment is carried out to the photoresist layer on the photoresist layer on via area ito film layer and non-via area ito film layer.
In step S109, utilize developer solution to carry out development treatment to the photoresist layer carried out on via area ito film layer that shading treatment crosses, also utilize developer solution to develop to the photoresist layer carried out on non-via area ito film layer that exposure-processed crosses simultaneously.
In certain embodiments, from step S101, after the development treatment of step S109, can directly by carrying out shading treatment to the photoresist layer on via area ito film layer, retaining all photoresist layers on via area ito film layer is filled on via hole, and by carrying out exposure-processed to the photoresist layer on non-via area ito film layer, remove photoresist layers all on non-via area ito film layer, finally can obtain covering the photoresist layer stopper on via area ito film layer.
Step S110: utilize etch process to peel off non-routing region ito film layer.
That is, all non-routing region ito film layer on the 3rd insulation course is removed.
Step S111: utilize dry carving technology to process the photoresist layer on the photoresist layer on the ito film layer of routing region and via area ito film layer, all to peel off the photoresist layer on the ito film layer of routing region, part peels off the photoresist layer on via area ito film layer, and photoresist layer stopper is covered on via hole.
In step S111, after carrying out dry carving technology process to the photoresist layer on the ito film layer of routing region, now on routing region ito film layer, thinner photoresist layer is all removed, and exposes figurethe routing region ito film layer of shape; Meanwhile, the remaining part of photoresist layer thicker on via area ito film layer, forms photoresist layer stopper, blocks via hole.Wherein, the thickness peeling off the photoresist layer on the ito film layer of routing region is identical with the thickness of the photoresist layer peeled off on via area ito film layer.
In the present embodiment, owing to utilizing dry carving technology to process to the photoresist layer on the photoresist layer on the ito film layer of routing region and via area ito film layer, then the side of exposed photoresist layer stopper outside via hole forms the shape of vertical substrates substrate.Due to the lateral vertical underlay substrate of photoresist layer stopper, the liquid crystal near the side of therefore photoresist layer stopper also can vertical substrates substrate, can not change toppling direction because of the impact of photoresist layer stopper.When the side out of plumb of photoresist layer stopper is hung down underlay substrate, as its side and underlay substrate form larger angle of inclination, neighbouring liquid crystal can, due to residing topographic change toppling direction, cause local repressentation abnormal.
The present embodiment is not by when increasing light shield, half masking process (i.e. half exposure) flow process is adopted to make the ITO electrode on COA substrate top layer, and utilize photoresistance to be filled up at the hole of darker via hole, namely first ITO electrode is formed, photoresistance is formed again to deposit in via hole in ITO electrode, panel manufacture craft can be optimized, effectively improve panel quality.
Further, the present invention discloses a kind of display device, and this display device comprises COA substrate. as Fig. 3shown in, COA substrate comprises underlay substrate 10, thin film transistor (TFT), the second insulation course 15, color blocking layer 16, the 3rd insulation course 17, at least one via hole 20 exposing the drain electrode of thin film transistor (TFT), ito film layer 18 and photoresist layer stopper 19.
Thin film transistor (TFT) is arranged on underlay substrate 10.Second insulation course 15 is arranged on thin film transistor (TFT).Color blocking layer 16 is arranged on the second insulation course 15.3rd insulation course 17 is arranged on color blocking layer 16.Ito film layer 18 is arranged on the 3rd insulation course 17, and ito film layer 18 is attached on via hole 20, and namely ito film layer 18 is connected with the drain signal of thin film transistor (TFT) with the 3rd insulation course 17 through the second insulation course 15, color blocking layer 16.Photoresist layer stopper 19 is arranged on via hole 20.Wherein, ito film layer 18 comprises and is arranged on via area ito film layer on via hole 20 and routing region ito film layer, and routing region ito film laminating is attached on the 3rd insulation course 17, and via area ito film laminating is attached in via hole 20.Photoresist layer stopper 19 cover be provided with via area ito film layer via hole 20 in.
In the present embodiment, thin film transistor (TFT) comprises the first metal layer 11, first insulation course 12, semiconductor active layer 13 and the second metal level 14.The first metal layer 11 is arranged on underlay substrate 10.First insulation course 12 is arranged on the first metal layer 11.Semiconductor active layer 13 is arranged on the first insulation course 12.Second metal level 14 is arranged on semiconductor active layer 13.Wherein, the first metal layer 11 forms the grid of thin film transistor (TFT), and the second metal level 14 forms drain electrode and the source electrode of thin film transistor (TFT).
as Fig. 3shown in 4, photoresist layer stopper 19 comprises stopper 191 and teat 192, and stopper 191 is filled in via hole 20, and teat 192 protrudes from via hole 20.In the present embodiment, teat 192 preferably includes the surface level 194 parallel with underlay substrate 10 and the side 193 of vertical substrates substrate 10.Due to side 193 vertical substrates substrate 10, the liquid crystal therefore near side 193 also can vertical substrates substrate 10, can not change toppling direction because of the impact of side 193; Meanwhile, the technique forming the side 193 of vertical substrates substrate 10 also facilitates, and directly adopts dry carving technology can form the side 193 of vertical substrates substrate 10.When side 193 out of plumb is hung down underlay substrate 10, as side 193 and underlay substrate 10 form larger angle of inclination, neighbouring liquid crystal can, due to residing topographic change toppling direction, cause local repressentation abnormal.In like manner, surface level 194 is due to parallel underlay substrate 10, and the liquid crystal on surface level 194 also can vertical substrates substrate 10, can not change the direction that liquid crystal is toppled over.
In other embodiments, as Fig. 4shown in, fig. 4in teat 292 can comprise the surface level 294 parallel with underlay substrate 10 and form the side 293 at pitch angle with underlay substrate 10.Consider that side 293 can affect the vergence direction of liquid crystal, therefore arrange in the present embodiment side 293 and underlay substrate 10 forms pitch angle and is less than 30 degree, preferably, arrange side 293 and underlay substrate 10 to form pitch angle be 20 degree or 15 degree.
In summary, the side 193 of teat 192 can have influence on the deflection of liquid crystal, in order to not affect the deflection of liquid crystal, therefore in other embodiments, be arranged to only comprise stopper 191 by photoresist layer stopper 19, stopper 191 is directly filled in via hole 20, and stopper 191 is provided with the surface level parallel with routing region ito film layer, namely the volume of stopper 191 is equal with the volume of via hole 20, and make stopper 191 be filled on via hole 20, its surface level is relative with the height of routing region ito film layer.
The present embodiment by arranging photoresist layer stopper in the via hole of COA substrate, can prevent from assembling liquid crystal in via hole by photoresist layer stopper, promote the display effect of panel, and the processing procedure of the photoresist layer stopper of this COA substrate is simple, panel manufacture craft can be optimized, improve panel quality, effectively reduce design cost.
The foregoing is only embodiments of the present invention, not thereby limit the scope of the claims of the present invention, every utilize instructions of the present invention and in accompanying drawingthe equivalent structure of Rong Suozuo or the conversion of equivalent flow process, or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.

Claims (10)

1. the manufacture method of a COA substrate, comprise: on underlay substrate, form thin film transistor (TFT), wherein said thin film transistor (TFT) comprises the first metal layer be arranged on described underlay substrate, the first insulation course be arranged on described the first metal layer, the second metal level of being arranged on the semiconductor active layer on described first insulation course and being arranged on described semiconductor active layer, and described second metal level forms the drain electrode of described thin film transistor (TFT); Described thin film transistor (TFT) is formed the second insulation course; Described second insulation course forms color blocking layer; Described color blocking layer forms the 3rd insulation course; Form at least one via hole exposing the drain electrode of described thin film transistor (TFT); It is characterized in that, described method also comprises:
Described 3rd insulation course forms ito film layer, and wherein said ito film layer comprises the via area ito film layer be arranged on described via hole and the non-via area ito film layer be arranged on outside described via hole;
Described ito film layer forms photoresist layer;
Shading treatment is carried out to the described photoresist layer on described via area ito film layer, and exposure-processed is carried out to the described photoresist layer on described non-via area ito film layer;
Development treatment is carried out to the described photoresist layer on the described photoresist layer on described via area ito film layer and described non-via area ito film layer, to obtain covering the photoresist layer stopper on described via area ito film layer.
2. method according to claim 1, is characterized in that, described non-via area ito film layer comprises routing region ito film layer and non-routing region ito film layer;
Describedly exposure-processed carried out to the described photoresist layer on described non-via area ito film layer comprise:
Partial exposure process is carried out to the described photoresist layer on the ito film layer of described routing region, the described photoresist layer on the ito film layer of described routing region is peeled off with part, and complete exposure-processed is carried out to the described photoresist layer on the ito film layer of described non-routing region, all to peel off the described photoresist layer on the ito film layer of described non-routing region.
3. method according to claim 2, is characterized in that, describedly carries out Partial exposure process to the described photoresist layer on the ito film layer of described routing region and comprises:
Semi-transparent light shield is utilized to carry out half exposure-processed to the described photoresist layer on the ito film layer of described routing region.
4. method according to claim 2, is characterized in that, described the step of development treatment is carried out to the described photoresist layer on described via area ito film layer after, described method also comprises:
Etch process is utilized to peel off described non-routing region ito film layer.
5. method according to claim 4, is characterized in that, describedly utilizes after etch process peels off the step of described non-routing region ito film layer, and described method also comprises:
Dry carving technology is utilized to process the described photoresist layer on the described photoresist layer on the ito film layer of described routing region and described via area ito film layer, all to peel off the described photoresist layer on the ito film layer of described routing region, part peels off the described photoresist layer on described via area ito film layer, and described photoresist layer stopper is covered on described via hole.
6. method according to claim 1, is characterized in that, underlay substrate described in the lateral vertical of exposed described photoresist layer stopper outside described via hole.
7. a COA substrate, comprising: underlay substrate; Be arranged on the thin film transistor (TFT) on described underlay substrate, wherein said thin film transistor (TFT) comprises the first metal layer be arranged on described underlay substrate, the first insulation course be arranged on described the first metal layer, the second metal level of being arranged on the semiconductor active layer on described first insulation course and being arranged on described semiconductor active layer, and described second metal level forms the drain electrode of described thin film transistor (TFT); Be arranged on the second insulation course on described thin film transistor (TFT), be arranged on the color blocking layer on described second insulation course; Be arranged on the 3rd insulation course on described color blocking layer and expose at least one via hole of drain electrode of described thin film transistor (TFT); It is characterized in that, described COA substrate also comprises:
Be arranged on the ito film layer on described 3rd insulation course, wherein said ito film layer comprises the via area ito film layer be arranged on described via hole;
Cover the photoresist layer stopper on described via area ito film layer.
8. COA substrate according to claim 7, is characterized in that, described photoresist layer stopper comprises teat and stopper, and described stopper is filled in described via hole, and described teat protrudes from described via hole.
9. COA substrate according to claim 8, is characterized in that, described teat comprises the side of the surface level parallel with described underlay substrate and vertical described underlay substrate.
10. a display device, is characterized in that, described display device comprises the COA substrate as described in any one of claim 7-9.
CN201510697888.3A 2015-10-23 2015-10-23 Display device, COA baseplate and manufacture method for same Pending CN105372889A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018094805A1 (en) * 2016-11-22 2018-05-31 深圳市华星光电技术有限公司 Manufacturing method for coa type liquid crystal panel, and coa type liquid crystal panel
CN108333845A (en) * 2018-02-26 2018-07-27 武汉华星光电技术有限公司 The production method of array substrate, display panel and array substrate
WO2021088138A1 (en) * 2019-11-07 2021-05-14 深圳市华星光电半导体显示技术有限公司 Coa-type array substrate and manufacturing method therefor

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105353567B (en) * 2015-12-02 2019-01-15 深圳市华星光电技术有限公司 Using the VA type liquid crystal display panel and preparation method thereof of no black matrix" technology
CN110061058A (en) * 2018-04-17 2019-07-26 京东方科技集团股份有限公司 Array substrate and preparation method thereof, display device
JP2022084146A (en) * 2020-11-26 2022-06-07 株式会社ジャパンディスプレイ Display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130169901A1 (en) * 2012-01-04 2013-07-04 Samsung Display Co., Ltd. Display substrate, method of manufacturing the same and display apparatus having the same
CN104076559A (en) * 2013-03-25 2014-10-01 三星显示有限公司 Display device
CN104460147A (en) * 2014-11-20 2015-03-25 深圳市华星光电技术有限公司 Thin film transistor array substrate, manufacturing method and display device
CN104576655A (en) * 2014-12-01 2015-04-29 深圳市华星光电技术有限公司 COA substrate and manufacturing method thereof
US9104060B2 (en) * 2013-03-07 2015-08-11 Innolux Corporation Liquid crystal display panel and liquid crystal display device containing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100720093B1 (en) * 2000-10-04 2007-05-18 삼성전자주식회사 liquid crystal display
KR20080001110A (en) * 2006-06-29 2008-01-03 엘지.필립스 엘시디 주식회사 Liquid crystal display device and method of manufacturing the same
KR20090126767A (en) * 2008-06-05 2009-12-09 삼성전자주식회사 Liquid crystal display and method for manufacturing the same
KR102254619B1 (en) * 2013-11-15 2021-05-24 삼성디스플레이 주식회사 Display substrate and a method of the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130169901A1 (en) * 2012-01-04 2013-07-04 Samsung Display Co., Ltd. Display substrate, method of manufacturing the same and display apparatus having the same
US9104060B2 (en) * 2013-03-07 2015-08-11 Innolux Corporation Liquid crystal display panel and liquid crystal display device containing the same
CN104076559A (en) * 2013-03-25 2014-10-01 三星显示有限公司 Display device
CN104460147A (en) * 2014-11-20 2015-03-25 深圳市华星光电技术有限公司 Thin film transistor array substrate, manufacturing method and display device
CN104576655A (en) * 2014-12-01 2015-04-29 深圳市华星光电技术有限公司 COA substrate and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018094805A1 (en) * 2016-11-22 2018-05-31 深圳市华星光电技术有限公司 Manufacturing method for coa type liquid crystal panel, and coa type liquid crystal panel
CN108333845A (en) * 2018-02-26 2018-07-27 武汉华星光电技术有限公司 The production method of array substrate, display panel and array substrate
WO2021088138A1 (en) * 2019-11-07 2021-05-14 深圳市华星光电半导体显示技术有限公司 Coa-type array substrate and manufacturing method therefor

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Application publication date: 20160302