CN105355668A - In(0.3)Ga(0.7)As cell with amorphous buffer layer structure and preparation method thereof - Google Patents

In(0.3)Ga(0.7)As cell with amorphous buffer layer structure and preparation method thereof Download PDF

Info

Publication number
CN105355668A
CN105355668A CN201510736815.0A CN201510736815A CN105355668A CN 105355668 A CN105355668 A CN 105355668A CN 201510736815 A CN201510736815 A CN 201510736815A CN 105355668 A CN105355668 A CN 105355668A
Authority
CN
China
Prior art keywords
layer
buffer layer
amorphous buffer
type
battery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510736815.0A
Other languages
Chinese (zh)
Inventor
李国强
高芳亮
温雷
张曙光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
South China University of Technology SCUT
Original Assignee
South China University of Technology SCUT
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by South China University of Technology SCUT filed Critical South China University of Technology SCUT
Priority to CN201510736815.0A priority Critical patent/CN105355668A/en
Publication of CN105355668A publication Critical patent/CN105355668A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0725—Multiple junction or tandem solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0735—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H01L31/1844—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses an In(0.3)Ga(0.7)As cell with an amorphous buffer layer structure, sequentially comprising an amorphous buffer layer and a solar cell layer from bottom to top. The amorphous buffer layer is composed of In(x)Ga(1-x)As, wherein 0.4<=x<=0.8. The thickness of the amorphous buffer layer is 1-5nm. The invention further discloses a preparation method of the In(0.3)Ga(0.7)As cell with an amorphous buffer layer structure. According to the invention, the buffer layer structure is simplified, the epitaxial growth process is simplified, the thickness, composition and doping concentration of the epitaxial layer can be strictly controlled, and therefore, an In(0.3)Ga(0.7)As material with good surface morphology, low defect density and high crystal quality and a single-junction or multi-junction solar cell are obtained.

Description

A kind of In with amorphous buffer layer structure 0.3ga 0.7as battery and preparation method
Technical field
The present invention relates to solar cell field, particularly a kind of In with amorphous buffer layer structure 0.3ga 0.7as battery and preparation method thereof.
Background technology
Solar energy, as a kind of regenerative resource, has clean, cheap, inexhaustible, nexhaustible feature, is effective replacer of the conventional fossil fuel energy.Along with developing rapidly of solar energy power generating industry and market, and under the traction of spacecraft energy resource system demand, photovoltaic technology constantly obtains important breakthrough; Meanwhile, corresponding photoelectric conversion efficiency improves constantly, and photovoltaic technology is obtained in space and ground and applies more and more widely.The most noticeable, landmark breakthrough based on the iii-v binary of GaAs, ternary and developing rapidly of quaternary compound semiconductor battery technology; And GaAs base system efficiency of solar cell is high, anti-radiation performance good, high temperature resistant, good reliability, meets the requirement of space environment to solar cell.Can be with as 1.42eV due to GaAs material, unijunction GaAs solar cell can only absorb the sunlight of a certain specific wavelength, and therefore its photoelectric conversion efficiency is restricted.In order to improve the utilance of solar cell to sunlight, needing to adopt many knot lamination solar cell structures, solar spectrum is carried out " segmentation ".
Current conventional iii-v three ties GaAs system solar cell aspect, mainly GaInP/InGaAs/Ge (1.84/1.4/0.67eV) structure solar cell, this system take Lattice Matching as overriding concern principle, and then limit the selection of material system, therefore the conversion efficiency room for promotion of battery is very limited.Seriously restrict the problem of three knot laminated cell performances to solve band gap mismatch, researchers, using band-gap as overriding concern principle, adopt GaAs to be the developing direction that the lattice mismatch system of substrate becomes efficient multi-node stacked solar cell, cascade solar cell.Such as bandgap structure is that the ideal three of 1.84/1.4/1.0eV ties laminated cell, and the ideal bandgap coupling of four knot stacked solar cell, cascade solar cells is 1.8/1.4/1.0/0.7eV.Can find out, in the efficient multi-node solar battery structure of above-mentioned band-gap, the sub-battery of ~ 1.0eV band gap material is a sub-junction battery the most key in efficient iii-v multijunction solar cell.Pass through theory calculate, 1eVGaInNAs material is as comparatively suitable with the band gap and lattice size of solar cell, but the minority carrier life time of GaInNAs epitaxial material is low, seriously limits the current density of many knot stacked solar cell, cascade solar cells, become the key factor that restriction efficiency improves.Therefore, according to the development of current growth technology, epitaxial device and the performance of material, can be ternary semiconductor Compound I n with the optimal material for 1eV 0.3ga 0.7as.
Now existing researcher prepares In on GaAs (substrate) material 0.3ga 0.7the unijunction of As (1.0eV) or multijunction cell, but, GaAs material carries out lattice mismatch In 0.3ga 0.7when the epitaxial growth of As battery material and element manufacturing, what usually adopt is all the buffer layer structure such as content gradually variational, component saltus step, component inversion of multilayer.Fig. 1 is the In adopting multilayer component resilient coating to prepare 0.3ga 0.7as single junction cell, comprises substrate 101, and the resilient coating set gradually on the substrate 101, undoped an In 0.3ga 0.72nd In of As layer 107, doping 0.3ga 0.7as layer 108, back surface field layer 109, In 0.3ga 0.7as base layer 110, In 0.3ga 0.7as emission layer 111, Window layer 112, contact layer 113, bottom electrode 100 and top electrode 114, resilient coating is made up of the sub-resilient coating 102,103,104,105,106 of multiple crystalline state, the resilient coating of these sandwich constructions needs the resilient coating that epitaxial growth multilayer is thicker in solar battery structure, growth step is loaded down with trivial details, and the composition of the every layer of material of very difficult accurately control, thickness and crystal mass, thus finally affect In 0.3ga 0.7the performance of As battery.
Summary of the invention
In order to overcome the above-mentioned shortcoming of prior art with not enough, the object of the present invention is to provide a kind of In with amorphous buffer layer structure 0.3ga 0.7as battery, simplifies buffer layer structure, simplifies epitaxial growth technology simultaneously.
Another object of the present invention is to provide the above-mentioned In with amorphous buffer layer structure 0.3ga 0.7the preparation method of As battery.
Object of the present invention is achieved through the following technical solutions:
A kind of In with amorphous buffer layer structure 0.3ga 0.7as battery, comprises amorphous buffer layer, solar cell layer from the bottom to top successively; Described amorphous buffer layer component is In xga 1-xas, 0.4≤x≤0.8.
The thickness of described amorphous buffer layer is 1-5nm.
Described solar cell layer comprises In from the bottom to top successively 0.3ga 0.7as non-doping intrinsic layer, In 0.3ga 0.7as doped layer, AlGaInAs back surface field layer, In 0.3ga 0.7as battery active layer, Ga 0.22in 0.78p Window layer.
The described In with amorphous buffer layer structure 0.3ga 0.7as battery is single-junction structure or multijunction structure.
The described In with amorphous buffer layer structure 0.3ga 0.7as battery, comprises lower contact electrode, GaAs (001) substrate of N-type, In from the bottom to top successively 0.6ga 0.4as amorphous buffer layer, In 0.3ga 0.7as non-doping intrinsic layer, N-type In 0.3ga 0.7as layer, N-type AlGaInAs back surface field layer, N-type In 0.3ga 0.7as base layer, P type In 0.3ga 0.7as emission layer, P type Ga 0.22in 0.78window layer, P type In 0.3ga 0.7as contact layer, upper contact electrode.
A kind of In with amorphous buffer layer structure 0.3ga 0.7the preparation method of As battery, comprises the following steps:
(1) adopt MOCVD technology or MBE technology to prepare amorphous buffer layer, preparation temperature is 300 ~ 380 DEG C, and vacuum degree is 5.0 × 10 -10torr, V/III line ratio is 20 ~ 25; Described amorphous buffer layer component is In xga 1-xas, 0.4≤x≤0.8;
(2) on the surface that amorphous buffer layer is exposed, solar cell layer is prepared.
The thickness of described amorphous buffer layer is 1-5nm.
Step (2) is described on the surface that amorphous buffer layer is exposed, prepares solar cell layer, is specially:
On the surface that amorphous buffer layer is exposed, MOCVD technology or MBE technology is adopted to prepare In successively 0.3ga 0.7as non-doping intrinsic layer, In 0.3ga 0.7as doped layer, AlGaInAs back surface field layer, by In 0.3ga 0.7battery active layer, the Ga of As base layer and emission layer composition 0.22in 0.78p Window layer; Described AlGaInAs back surface field layer and In 0.3ga 0.7the conductiving doping type of As base layer is identical.
The described In with amorphous buffer layer structure 0.3ga 0.7as battery is single-junction structure or multijunction structure.
The described In with amorphous buffer layer structure 0.3ga 0.7as battery comprises lower contact electrode, GaAs (001) substrate of N-type, In from the bottom to top successively 0.6ga 0.4as amorphous buffer layer, In 0.3ga 0.7as non-doping intrinsic layer, N-type In 0.3ga 0.7as layer, N-type AlGaInAs back surface field layer, N-type In 0.3ga 0.7as base layer, P type In 0.3ga 0.7as emission layer, P type Ga 0.22in 0.78window layer, P type In 0.3ga 0.7as contact layer, upper contact electrode.
Compared with prior art, the present invention has the following advantages and beneficial effect:
1. solar cell band gap of the present invention is ~ 1.0eV, can form more reasonably band gap and combine, can utilize solar spectrum more fully with the GaInP/GaAs of technology maturation, preparation high efficiency many knots stacked solar cell, cascade solar cell;
2. solar cell of the present invention adopts the In of individual layer xga 1-xas large mismatch amorphous buffer layer structure, compared with the resilient coating of sandwich construction, simplify buffer layer structure, simplify epitaxial growth technology simultaneously, strictly can control thickness, component, the doping content of epitaxial loayer, thus obtain the In that surface topography is good, defect concentration is low, crystal mass is high 0.3ga 0.7as material.
3. solar cell of the present invention employs low temperature In xga 1-xprepared by As amorphous buffer layer technology, can effectively filtering substrate and In 0.3ga 0.7due to the dislocation that lattice mismatch causes between As material, discharge stress well, can enough thick In be obtained like this 0.3ga 0.7as layer and the defect do not produced because misfit strain causes, improve In 0.3ga 0.7the crystal mass of As material, thus the efficiency improving battery.
Accompanying drawing explanation
Fig. 1 is the In of prior art 0.3ga 0.7as battery structure schematic diagram.
Fig. 2 is the unijunction In with amorphous buffer layer structure of embodiments of the invention 1 0.3ga 0.7the structural representation of As battery.
Fig. 3 is the unijunction In with amorphous buffer layer structure of embodiments of the invention 1 0.3ga 0.7the I-V curve chart of As battery.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment 1
The unijunction In with amorphous buffer layer structure of the present embodiment 0.3ga 0.7the preparation process of As battery is as follows:
(1) choose GaAs (001) substrate of N-type, and substrate is cleaned, the GaAs substrate of No clean also can be selected directly to enter next step reaction.GaAs substrate is placed in the reaction chamber of MBE, adopt cooled with liquid nitrogen, reaction chamber vacuum degree reaches 5.0 × 10 -10torr, by silicon to 600 ~ 680 DEG C under the environment of As line protection, to remove substrate surface oxide layer, plays surface reconstruction simultaneously, obtains smooth GaAs (001) substrate surface.
(2) on GaAs substrate surface, adopt MBE to grow In 0.6ga 0.4as amorphous buffer layer, adopt lower temperature growth process, growth temperature is 300 DEG C, and V/III line ratio is 20, by controlling growth temperature, prepares amorphous In 0.6ga 0.4as amorphous buffer layer, meanwhile, control In 0.6ga 0.4the thickness of As amorphous buffer layer is ~ 1nm.
(3) at In 0.6ga 0.4as amorphous buffer layer adopts MBE method to grow In successively on the surface 0.3ga 0.7as non-doping intrinsic layer, temperature is 550 DEG C, and V/III line ratio is 20, and thickness is 500nm.
(4) In 0.3ga 0.7as non-doping intrinsic layer grows the N-type In of Si doping 0.3ga 0.7as layer, doping content is 2 × 10 18cm -3, growth temperature is 550 DEG C, and V/III line ratio is 20, and thickness is 500nm.
(5) then at N-type In 0.3ga 0.7the N-type AlGaInAs back surface field layer that As layer surface-borne Si adulterates, to reduce the compound of light induced electron, doping content is 3 × 10 18cm -3, temperature is 550 DEG C, and V/III line ratio is 20, and thickness is 100nm.
(6) on AlGaInAs back surface field layer, grow the Si doped N-type In of carrier concentration lower than back surface field layer carrier concentration 0.3ga 0.7as base layer, doping content is 1 × 10 17cm -3, growth temperature is 550 DEG C, and V/III line ratio is 20, and thickness is 2.5 μm.Then the P type In of Zn doping is grown 0.3ga 0.7as emission layer, doping content is 2 × 10 18cm -3, growth temperature is 550 DEG C, and V/III line ratio is 20, and thickness is 100nm.
(7) the P type Ga of Zn doping is then grown 0.22in 0.78p, as Window layer, prevents light induced electron from upwards spreading, and Zn is dopant, and doping content is 3 × 10 18cm -3, growth temperature is 550 DEG C, and V/III line ratio is 20, and thickness is 100nm.
(8) at Ga 0.22in 0.78p Window layer surface adopts MBE to grow the P type In of high-dopant concentration 0.3ga 0.7as contact layer, Zn is dopant, and doping content is 1 × 10 19cm -3, growth temperature is 550 DEG C, and V/III line ratio is 20, and thickness is 500nm, so that battery and top electrode form good ohmic contact, reduces battery impedance, improves battery performance.Finally obtain based on In 0.6ga 0.4in in As amorphous buffer layer 0.3ga 0.7as unijunction solar cell epitaxial wafer.
(9) by obtain based on In 0.6ga 0.4in in As amorphous buffer layer 0.3ga 0.7as unijunction solar cell epitaxial wafer is transferred to electron beam evaporation system, carries out electrode fabrication: at In 0.3ga 0.7contact electrode under contact electrode and N-type is prepared in P type respectively on the surface of As contact layer and on the surface of GaAs substrate.Finally obtain based on In 0.6ga 0.4in in As amorphous buffer layer 0.3ga 0.7as unijunction solar cell.
As shown in Figure 2, the In with amorphous buffer layer structure that the present embodiment prepares 0.3ga 0.7as battery, comprises lower contact electrode 200, GaAs (001) substrate 201 of N-type, In from the bottom to top successively 0.6ga 0.4as amorphous buffer layer 202, In 0.3ga 0.7the N-type In of As non-doping intrinsic layer 203, Si doping 0.3ga 0.7n-type AlGaInAs back surface field layer 205, the Si doped N-type In of As layer 204, Si doping 0.3ga 0.7the P type In of As base layer 206, Zn doping 0.3ga 0.7the P type Ga of As emission layer 207, Zn doping 0.22in 0.78the P type In of Window layer 208, Zn doping 0.3ga 0.7as contact layer 209, upper contact electrode 210.
GaAs (001) substrate prepared by the present embodiment has the In of amorphous buffer layer structure 0.3ga 0.7as shown in Figure 3, display open circuit voltage is 0.629V to the I-V curve of As solar cell, reaches desirable level.
Embodiment 2
The binode In with amorphous buffer layer structure of the present embodiment 0.3ga 0.7the preparation process of As battery is as follows: (1) chooses GaAs (001) substrate of N-type, and cleans substrate, and the GaAs substrate of No clean also can be selected directly to enter next step reaction.GaAs substrate is placed in the reaction chamber of MBE, adopt cooled with liquid nitrogen, reaction chamber vacuum degree reaches 5.0 × 10 -10torr, by silicon to 680 DEG C under the environment of As line protection, to remove substrate surface oxide layer, plays surface reconstruction simultaneously, obtains smooth GaAs (001) substrate surface.
(2) on GaAs substrate surface, MBE is adopted to grow the N-type GaAs resilient coating of Si doping, to obtain the GaAs surface of surfacing.Growth temperature is 580 DEG C, and V/III line ratio is 25, and thickness is ~ 200nm.
(3) the sub-junction battery of growth top battery GaAs on GaAs resilient coating: first grow Si heavily doped N-type GaInP back surface field layer, doping content is 2 × 10 18cm -3, growth temperature is 580 DEG C, and V/III line ratio is 25, and thickness is 100nm.
(4) then grow the N-type GaAs base layer of Si doping, doping content is 1 × 10 17cm -3, growth temperature is 580 DEG C, and V/III line ratio is 25, and thickness is 2.5 μm.Then grow the P type GaAs emission layer of Zn doping, doping content is 2 × 10 18cm -3, growth temperature is 580 DEG C, and V/III line ratio is 25, and thickness is 100nm.
(5) on P type GaAs emission layer, grow the P type GaInP Window layer of Zn doping, prevent light induced electron from upwards spreading, Zn is dopant, and doping content is 3 × 10 18cm -3, growth temperature is 580 DEG C, and V/III line ratio is 25, and thickness is 100nm.
(6) in the P type GaInP Window layer of Zn doping, grow GaAs tunnel junctions, be followed successively by the N-GaAs tunnel junctions of the P-GaAs/Si doping of Zn doping, doping content is 1 × 10 19cm -3, growth temperature is 580 DEG C, and V/III line ratio is 25, and thickness is 200nm.
(7) on N-type tunnel junctions GaAs, In is grown 0.6ga 0.4as amorphous buffer layer, adopt lower temperature growth process, growth temperature is 380 DEG C, and V/III line ratio is 25, by controlling growth temperature, prepares amorphous In 0.6ga 0.4as amorphous buffer layer, meanwhile, control In 0.6ga 0.4the thickness of As amorphous buffer layer is ~ 5nm.
(8) at In 0.6ga 0.4as amorphous buffer layer grows the N-type In of Si doping 0.3ga 0.7as layer, doping content is 2 × 10 18cm -3, growth temperature is 580 DEG C, and V/III line ratio is 25, and thickness is 500nm.
(9) then at N-type In 0.3ga 0.7the N-type AlGaInAs back surface field layer that As layer surface-borne Si adulterates, to reduce the compound of light induced electron, doping content is 3 × 10 18cm -3, temperature is 580 DEG C, and V/III line ratio is 25, and thickness is 100nm.
(10) on AlGaInAs back surface field layer, grow the Si doped N-type In of carrier concentration lower than back surface field layer carrier concentration 0.3ga 0.7as base layer, doping content is 1 × 10 17cm -3, growth temperature is 580 DEG C, and V/III line ratio is 25, and thickness is 2.5 μm.Then the P type In of Zn doping is grown 0.3ga 0.7as emission layer, doping content is 2 × 10 18cm -3, growth temperature is 550 ~ 580 DEG C, and V/III line ratio is 25, and thickness is 100nm.
(11) then growing P-type Ga 0.22in 0.78p is as Ga 0.22in 0.78p Window layer, prevents light induced electron from upwards spreading, and Zn is dopant, and doping content is 3 × 10 18cm -3, growth temperature is 580 DEG C, and V/III line ratio is 25, and thickness is 100nm.
(12) at Ga 0.22in 0.78the P type In of P Window layer superficial growth high-dopant concentration 0.3ga 0.7as contact layer, Zn is dopant, and doping content is 1 × 10 19cm -3, growth temperature is 580 DEG C, and V/III line ratio is 25, and thickness is 500nm, so that battery and top electrode form good ohmic contact, reduces battery impedance, improves battery performance.Finally obtain based on In 0.6ga 0.4gaAs/In in As amorphous buffer layer 0.3ga 0.7as Double Junction Tandem Solar Cells epitaxial wafer.
(13) by obtain based on In 0.6ga 0.4in in As amorphous buffer layer 0.3ga 0.7as unijunction solar cell epitaxial wafer is transferred to electron beam evaporation system, carries out electrode fabrication: at In 0.3ga 0.7contact electrode on contact electrode and N-type is prepared under P type respectively on the surface of As contact layer and on the surface of GaAs substrate.Finally obtain using the sub-junction battery of GaAs top battery.In 0.3ga 0.7as battery is the GaAs/In of end battery 0.3ga 0.7as Double Junction Tandem Solar Cells.
GaAs (001) prepared by the present embodiment has the In of amorphous buffer layer structure 0.3ga 0.7the I-V curve display of As solar cell, display open circuit voltage is 1.67V, reaches desirable level.
Above-described embodiment is the present invention's preferably execution mode; but embodiments of the present invention are not limited by the examples; change, the modification done under other any does not deviate from Spirit Essence of the present invention and principle, substitute, combine, simplify; all should be the substitute mode of equivalence, be included within protection scope of the present invention.

Claims (10)

1. one kind has the In of amorphous buffer layer structure 0.3ga 0.7as battery, is characterized in that, comprises amorphous buffer layer, solar cell layer from the bottom to top successively; Described amorphous buffer layer component is In xga 1-xas, 0.4≤x≤0.8.
2. the In with amorphous buffer layer structure according to claim 1 0.3ga 0.7as battery, is characterized in that, the thickness of described amorphous buffer layer is 1-5nm.
3. the In with amorphous buffer layer structure according to claim 1 0.3ga 0.7as battery, is characterized in that, described solar cell layer comprises In from the bottom to top successively 0.3ga 0.7as non-doping intrinsic layer, In 0.3ga 0.7as doped layer, AlGaInAs back surface field layer, In 0.3ga 0.7as battery active layer, Ga 0.22in 0.78p Window layer.
4. the In with amorphous buffer layer structure according to claim 3 0.3ga 0.7as battery, is characterized in that, described in there is the In of amorphous buffer layer structure 0.3ga 0.7as battery is single-junction structure or multijunction structure.
5. the In with amorphous buffer layer structure according to claim 1 0.3ga 0.7as battery, is characterized in that, comprises lower contact electrode, GaAs (001) substrate of N-type, In from the bottom to top successively 0.6ga 0.4as amorphous buffer layer, In 0.3ga 0.7as non-doping intrinsic layer, N-type In 0.3ga 0.7as layer, N-type AlGaInAs back surface field layer, N-type In 0.3ga 0.7as base layer, P type In 0.3ga 0.7as emission layer, P type Ga 0.22in 0.78window layer, P type In 0.3ga 0.7as contact layer, upper contact electrode.
6. one kind has the In of amorphous buffer layer structure 0.3ga 0.7the preparation method of As battery, is characterized in that, comprises the following steps:
(1) adopt MOCVD technology or MBE technology to prepare amorphous buffer layer, preparation temperature is 300 ~ 380 DEG C, and vacuum degree is 5.0x10 -10torr, V/III line ratio is 20 ~ 25; Described amorphous buffer layer component is In xga 1-xas, 0.4≤x≤0.8;
(2) on the surface that amorphous buffer layer is exposed, solar cell layer is prepared.
7. the In with amorphous buffer layer structure according to claim 6 0.3ga 0.7the preparation method of As battery, is characterized in that, the thickness of described amorphous buffer layer is 1-5nm.
8. the In with amorphous buffer layer structure according to claim 6 0.3ga 0.7the preparation method of As battery, is characterized in that, step (2) is described on the surface that amorphous buffer layer is exposed, prepares solar cell layer, is specially:
On the surface that amorphous buffer layer is exposed, MOCVD technology or MBE technology is adopted to prepare In successively 0.3ga 0.7as non-doping intrinsic layer, In 0.3ga 0.7as doped layer, AlGaInAs back surface field layer, by In 0.3ga 0.7battery active layer, the Ga of As base layer and emission layer composition 0.22in 0.78p Window layer; Described AlGaInAs back surface field layer and In 0.3ga 0.7the conductiving doping type of As base layer is identical.
9. the described In with amorphous buffer layer structure according to claim 8 0.3ga 0.7the preparation method of As battery, described in there is the In of amorphous buffer layer structure 0.3ga 0.7as battery is single-junction structure or multijunction structure.
10. the In with amorphous buffer layer structure according to claim 6 0.3ga 0.7the preparation method of As battery, is characterized in that, the described In with amorphous buffer layer structure 0.3ga 0.7as battery comprises lower contact electrode, GaAs (001) substrate of N-type, In from the bottom to top successively 0.6ga 0.4as amorphous buffer layer, In 0.3ga 0.7as non-doping intrinsic layer, N-type In 0.3ga 0.7as layer, N-type AlGaInAs back surface field layer, N-type In 0.3ga 0.7as base layer, P type In 0.3ga 0.7as emission layer, P type Ga 0.22in 0.78window layer, P type In 0.3ga 0.7as contact layer, upper contact electrode.
CN201510736815.0A 2015-10-30 2015-10-30 In(0.3)Ga(0.7)As cell with amorphous buffer layer structure and preparation method thereof Pending CN105355668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510736815.0A CN105355668A (en) 2015-10-30 2015-10-30 In(0.3)Ga(0.7)As cell with amorphous buffer layer structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510736815.0A CN105355668A (en) 2015-10-30 2015-10-30 In(0.3)Ga(0.7)As cell with amorphous buffer layer structure and preparation method thereof

Publications (1)

Publication Number Publication Date
CN105355668A true CN105355668A (en) 2016-02-24

Family

ID=55331600

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510736815.0A Pending CN105355668A (en) 2015-10-30 2015-10-30 In(0.3)Ga(0.7)As cell with amorphous buffer layer structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN105355668A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449811A (en) * 2016-10-28 2017-02-22 华南理工大学 GaAs substratum grown n-InGaAs film and preparation method
CN106653926A (en) * 2017-01-23 2017-05-10 华南理工大学 Plasmon enhanced GaAs-based multi-junction solar cell and preparation method thereof
CN111276550A (en) * 2019-11-11 2020-06-12 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 Flexible solar cell with graphene transparent electrode and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738267A (en) * 2012-06-20 2012-10-17 中国科学院苏州纳米技术与纳米仿生研究所 Solar battery with superlattices and manufacturing method thereof
CN103199142A (en) * 2013-04-03 2013-07-10 中国科学院苏州纳米技术与纳米仿生研究所 GaInP/GaAs/InGaAs/Ge quadruple-junction solar battery and preparation method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738267A (en) * 2012-06-20 2012-10-17 中国科学院苏州纳米技术与纳米仿生研究所 Solar battery with superlattices and manufacturing method thereof
CN103199142A (en) * 2013-04-03 2013-07-10 中国科学院苏州纳米技术与纳米仿生研究所 GaInP/GaAs/InGaAs/Ge quadruple-junction solar battery and preparation method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
FANGLIANG GAO 等: "Quality-enhanced In0.3Ga0.7As film grown on GaAs substrate with an ultrathin amorphous In0.6Ga0.4As buffer layer", 《APPLIED PHYSICS LETTERS》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449811A (en) * 2016-10-28 2017-02-22 华南理工大学 GaAs substratum grown n-InGaAs film and preparation method
CN106653926A (en) * 2017-01-23 2017-05-10 华南理工大学 Plasmon enhanced GaAs-based multi-junction solar cell and preparation method thereof
CN106653926B (en) * 2017-01-23 2018-04-13 华南理工大学 A kind of phasmon enhancing GaAs Quito connection solar cell and preparation method thereof
CN111276550A (en) * 2019-11-11 2020-06-12 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 Flexible solar cell with graphene transparent electrode and manufacturing method thereof

Similar Documents

Publication Publication Date Title
US10066318B2 (en) Isoelectronic surfactant induced sublattice disordering in optoelectronic devices
US10050166B2 (en) Silicon heterojunction photovoltaic device with wide band gap emitter
US7626116B2 (en) Isoelectronic surfactant suppression of threading dislocations in metamorphic epitaxial layers
US9437769B2 (en) Four-junction quaternary compound solar cell and method thereof
CN101859813B (en) Method for manufacturing quadri-junction GaInP/GaAs/InGaAs/Ge solar cells
JP2015073130A (en) Four junction inverted metamorphic multi-junction solar cell with two metamorphic layers
CN102790120B (en) GaInP/GaAs/Ge three-junction solar battery and manufacturing method thereof
CN102412337A (en) High-efficient four solar cell and manufacturing method thereof
CN106024924A (en) Lattice mismatch solar cell containing novel tunneling junction and preparation method thereof
CN105355668A (en) In(0.3)Ga(0.7)As cell with amorphous buffer layer structure and preparation method thereof
CN103077983A (en) Multi-junction solar battery and preparation method thereof
CN105810760A (en) Lattice-matched five-junction solar cell and fabrication method thereof
CN102738267B (en) Solar battery with superlattices and manufacturing method thereof
CN103000740A (en) GaAs/GaInP double knot solar battery and manufacturing method thereof
CN114171615B (en) Silicon-based multi-junction solar cell and gradual change buffer layer thereof
CN109755340A (en) Positive lattice mismatch three-junction solar cell
CN104241416A (en) Three-junction solar cell with quantum well structure
CN102738266B (en) Solar cell with doping superlattice and method for manufacturing solar cell
CN106252448A (en) A kind of multijunction solar cell containing GaInNAs material and preparation method thereof
CN107403850B (en) Multi-junction solar cell containing embedded back surface field structure and preparation method thereof
CN205752204U (en) A kind of two-sided growth four-junction solar cell with reflecting layer
CN110137298B (en) Preparation method of Ge/Si heterojunction bottom cell of GaAs-based multi-junction solar cell
WO2013004188A1 (en) Solar cell, system, and manufacturing method thereof
CN111129196B (en) Germanium-based laminated solar cell and preparation method thereof
Yamaguchi et al. Super-high-efficiency III-V tandem and multi-junction cells

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20160224