CN105353288A - Transistor process fluctuation detection system and detection method - Google Patents
Transistor process fluctuation detection system and detection method Download PDFInfo
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- CN105353288A CN105353288A CN201410409294.3A CN201410409294A CN105353288A CN 105353288 A CN105353288 A CN 105353288A CN 201410409294 A CN201410409294 A CN 201410409294A CN 105353288 A CN105353288 A CN 105353288A
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Abstract
The invention provides a transistor process fluctuation detection system and a detection method. The detection system includes a cell array to be detected, a rank code translator, a rank selector, and an oscillator; wherein the cell array to be detected includes at least two cells to be detected; the rank code translator is connected to each cell to be detected respectively and is used to select each cell to be detected; the rank selector is connected to the oscillator and a transistor to be detected of each cell to be detected respectively and is used to connect the selected transistor to be detected and the oscillator; and the oscillator converts an output signal of the transistor to be detected into a pulse signal, the frequency of the pulse signal is corresponding to the threshold voltage of the transistor to be detected, and the fluctuation of the threshold voltage of the transistor to be detected can be determined through the fluctuation of the frequency of the pulse signal. The transistor process fluctuation detection system and the detection method can solve the problem in the prior art that semiconductor transistor process fluctuation detection method is more complicated, and can achieve fast and simple detection of transistor process fluctuation.
Description
Technical field
The present invention relates to semiconductor transistor detection technique, particularly relate to a kind of transistor technology surge detection system and detection method.
Background technology
The technological fluctuation of semiconductor transistor refers in the manufacture process of semi-conductor chip, because dopant concentration is uneven, photoetching process not thoroughly or planarization process imperfect, the parameters (such as its channel length, width and gate oxide thickness etc.) that result in semiconductor transistor is not identical with desirable numerical value, but there is certain deviation.Technological fluctuation can affect the electrical parameters such as the threshold voltage of semiconductor transistor self, and the conducting of transistor mistake or mistake then can be caused time serious to turn off.Between the multiple transistors in semi-conductor chip, technological fluctuation then can cause the performance between each transistor there are differences, and then have impact on the serviceability of whole semi-conductor chip.Therefore, extremely important to the detection of semiconductor transistor technology fluctuation.
At present, to the detection mode of semiconductor transistor technology fluctuation, one adopts physico-chemical process, directly measures the physical quantitys such as channel length, width and gate oxide thickness, then carries out the situation that comprehensive analysis obtains technological fluctuation.But this method can produce to semi-conductor chip the destructiveness damage being difficult to repair, and cost is very high, and measuring process is very complicated.Another kind of mode is that such as threshold voltage, by measuring threshold voltage, obtains the situation of technological fluctuation indirectly by measuring the electrical parameter being subject to technological fluctuation impact, is use a kind of detection mode comparatively widely at present.
In prior art, by obtaining the anti-mode pushing away threshold voltage of current-voltage characteristic curve of transistor to the measurement of the threshold voltage of semiconductor transistor, comparatively accurate numerical value can be obtained, but because the method obtaining current-voltage characteristic curve is more complicated, and then making the testing process of transistor technology fluctuation also very complicated, efficiency is lower.
Summary of the invention
The invention provides a kind of transistor technology surge detection system and detection method, the problem that the detection method for solving existing semiconductor transistor technological fluctuation is more complicated, to realize carrying out detecting fast, easily to transistor technology fluctuation.
The embodiment of the present invention provides a kind of transistor technology surge detection system, comprises to-be-measured cell array, ranks code translator, ranks selector switch and oscillator;
Described to-be-measured cell array is the array be made up of at least two to-be-measured cells;
Described ranks code translator is connected with each described to-be-measured cell respectively, for selected to-be-measured cell;
Described ranks selector switch is connected with the test transistor in described oscillator and each described to-be-measured cell respectively, for selected test transistor is connected to described oscillator; The output signal of described test transistor is converted to pulse signal by described oscillator, the frequency of described pulse signal is corresponding with the threshold voltage of described test transistor, to be determined the fluctuation of the threshold voltage of described test transistor by the fluctuation of described pulse signal frequency.
Transistor technology surge detection system as above, described to-be-measured cell also comprises auxiliary detection transistor, and described in described auxiliary detection transistor AND gate, the structure of test transistor is identical;
The data terminal of described auxiliary detection transistor is connected with the data terminal of described test transistor, the control end of described auxiliary detection transistor and the control end of described test transistor receive enable signal anti-phase each other respectively, with when described test transistor turns off, described auxiliary detection transistor turns and suppress described oscillator operation.
Transistor technology surge detection system as above, described test transistor and auxiliary detection transistor are p channel field-effect pipe;
The source electrode of described auxiliary detection transistor receives high level signal, and drain electrode is connected with the source electrode of described test transistor, the grounded drain of described test transistor;
The source electrode of described test transistor, also as the output terminal of described test transistor, is connected with described oscillator.
Transistor technology surge detection system as above, described oscillator comprises the odd level phase inverter being in turn connected into ring-type, and wherein the output terminal of one-level phase inverter is as the output terminal of described oscillator;
First link of phase inverter at different levels receives high level signal, and the second link is all connected with the output terminal of described to-be-measured cell.
Transistor technology surge detection system as above, every one-level phase inverter in described odd level phase inverter comprises the first field effect transistor and the second field effect transistor, described first field effect transistor is p channel field-effect pipe, and described second field effect transistor is n channel field-effect pipe;
The source electrode of described first field effect transistor receives high level signal, and drain electrode is connected with the drain electrode of described second field effect transistor; The source electrode of described second field effect transistor, as the input end of described oscillator, is connected with the output terminal of described auxiliary transistor;
The grid of described first field effect transistor is connected with the grid of described second field effect transistor, and is connected with the output terminal of previous stage phase inverter as the input end of described phase inverter, and the drain electrode of described first field effect transistor is as the output terminal of described phase inverter.
Transistor technology surge detection system as above, described test transistor and auxiliary detection transistor are n channel field-effect pipe;
The source ground of described auxiliary detection transistor, drain electrode is connected with the source electrode of described test transistor, and the drain electrode of described test transistor receives high level signal;
The source electrode of described test transistor, also as the output terminal of described test transistor, is connected with described oscillator.
Transistor technology surge detection system as above, described oscillator comprises the odd level phase inverter being in turn connected into ring-type, and wherein the output terminal of one-level phase inverter is as the output terminal of described oscillator;
First link ground connection of phase inverter at different levels, the second link is all connected with the output terminal of described to-be-measured cell.
Transistor technology surge detection system as above, every one-level phase inverter in described odd level phase inverter comprises the 3rd field effect transistor and the 4th field effect transistor, described 3rd field effect transistor is n channel field-effect pipe, and described 4th field effect transistor is p channel field-effect pipe;
The source ground of described 3rd field effect transistor, drain electrode is connected with the drain electrode of described 4th field effect transistor; The source electrode of described 4th field effect transistor, as the input end of described oscillator, is connected with the output terminal of described auxiliary transistor;
The grid of described 3rd field effect transistor is connected with the grid of described 4th field effect transistor, and is connected with the output terminal of previous stage phase inverter as the input end of described phase inverter, and the drain electrode of described 3rd field effect transistor is as the output terminal of described phase inverter.
Transistor technology surge detection system as above, also comprises frequency divider; Described frequency divider is connected with described oscillator, carries out frequency division for the pulse signal exported described oscillator.
This aspect embodiment also provides a kind of transistor technology surge detection method, comprising:
To-be-measured cell in the to-be-measured cell array be made up of at least two to-be-measured cells is selected;
The output signal of the test transistor in selected described to-be-measured cell is converted to pulse signal, the frequency of described pulse signal is corresponding with the threshold voltage of described test transistor, to be determined the fluctuation of the threshold voltage of described test transistor by the fluctuation of described pulse signal frequency.
Transistor technology surge detection method as above, also comprises:
Frequency division is carried out to described pulse signal, to be determined the frequency jitter of described pulse signal by the frequency jitter of the pulse signal after frequency division.
The technical scheme that the present embodiment provides adopts ranks code translator selected to-be-measured cell in to-be-measured cell array, test transistor in selected to-be-measured cell and oscillator couple together by ranks selector switch, to make oscillator, the signal that test transistor exports is converted to pulse signal, detected by the frequency of the pulse signal exported each to-be-measured cell correspondence, the fluctuation situation of each test transistor threshold voltage can be determined according to the fluctuation of frequency, also namely embodied the situation of transistor technology fluctuation.Compared with prior art, the technology that the present embodiment provides is comparatively simple, can realize technological fluctuation in the sheet to semiconductor transistor and carry out detecting fast, easily.
Accompanying drawing explanation
The structural representation of the transistor technology surge detection system that Fig. 1 provides for the embodiment of the present invention one;
The structural representation of the to-be-measured cell that Fig. 2 provides for the embodiment of the present invention one and oscillator;
Fig. 3 is the structural representation of p channel field-effect pipe transmission of electric signals;
Fig. 4 is the structural representation of n channel field-effect pipe transmission of electric signals;
The structural representation of the to-be-measured cell that Fig. 5 provides for the embodiment of the present invention two and oscillator;
The structural representation of the to-be-measured cell that Fig. 6 provides for the embodiment of the present invention three and oscillator;
The structural representation of first kind to-be-measured cell in the transistor technology surge detection system that Fig. 7 provides for the embodiment of the present invention four;
The structural representation of Equations of The Second Kind to-be-measured cell in the transistor technology surge detection system that Fig. 8 provides for the embodiment of the present invention four;
The process flow diagram of the transistor technology surge detection method that Fig. 9 provides for the embodiment of the present invention five.
Embodiment
Embodiment one
The structural representation of the transistor technology surge detection system that Fig. 1 provides for the embodiment of the present invention one.As shown in Figure 1, the transistor technology surge detection system that the present embodiment provides can comprise: to-be-measured cell array, ranks code translator, ranks selector switch 4 and oscillator 2, wherein, to-be-measured cell array is the array be made up of at least two to-be-measured cells 1, and at least two to-be-measured cells 1 can form two-dimensional array.Each to-be-measured cell 1 comprises a test transistor, and the technical scheme that the present embodiment provides is exactly detect the threshold voltage fluctuation situation of the test transistor in each to-be-measured cell 1, to determine the technological fluctuation situation of test transistor.
Ranks code translator is connected with each to-be-measured cell 1 respectively, the to-be-measured cell address date that ranks code translator is sent for receiving external circuit, and in to-be-measured cell array, chooses corresponding to-be-measured cell 1 according to this address date.Ranks code translator specifically can comprise line decoder 31 and column decoder 32, line decoder 31 comes identifying rows address for the address date sent according to external circuit, row address and column address, for identifying column address, combine by column decoder 32, can select unique to-be-measured cell 1.The concrete structure of ranks code translator can adopt implementation conventional in prior art, and the present embodiment is not construed as limiting this.
Ranks selector switch 4 is connected with the test transistor in oscillator 2 and each to-be-measured cell 1 respectively, for selected test transistor is connected to oscillator 2.Concrete, ranks selector switch 4 can have multiple input end, an input end is connected with the output terminal of a test transistor, and the output terminal of ranks selector switch 4 is connected with the input end of oscillator 2, the output terminal of chosen test transistor can be connected with oscillator 2.The specific implementation of ranks selector switch 4 can refer to mode conventional in prior art and realizes.
Oscillator 2 is for being converted to pulse signal by the output signal of test transistor, and the frequency of this pulse signal and the threshold voltage of test transistor have corresponding relation, to be determined the fluctuation of the threshold voltage of test transistor by the fluctuation of pulse signal frequency.
The signal that each test transistor in to-be-measured cell array exports is converted to pulse signal, by the detection of pulse signals frequency with compare, can determine whether to exist in each test transistor the threshold voltage of some transistor and the larger situation of other transistor gap.Because manufacturing process affects the maximum factor of the threshold voltage of transistor, therefore, the fluctuation situation determining transistor threshold voltage is also equivalent to the fluctuation situation determining transistor fabrication.
The technical scheme measured is carried out for each to-be-measured cell 1 in to-be-measured cell array, can refer to shown in Fig. 2, the structural representation of the to-be-measured cell that Fig. 2 provides for the embodiment of the present invention one and oscillator.In fig. 2, to-be-measured cell 1 comprises test transistor 11, and the output terminal of test transistor 11 is connected with oscillator 2.
The technical scheme that the present embodiment provides make use of the phenomenon that semiconductor transistor exists threshold voltage loss in the process of transmission of electric signals, for field effect transistor, as shown in Figure 3 and Figure 4, Fig. 3 is the structural representation of p channel field-effect pipe transmission of electric signals, and Fig. 4 is the structural representation of n channel field-effect pipe transmission of electric signals.Such as: p channel field-effect pipe is when transmitting low level signal GND, and the actual signal exported not is GND, but GND+V
tH_p, wherein V
tH_pfor the threshold voltage of p channel field-effect pipe; N channel field-effect pipe is when transmitting high level signal VDD, and the actual signal exported not is VDD, but VDD-V
tH_n, wherein V
tH_nfor the threshold voltage of n channel field-effect pipe.
According to the Principle of Signal Transmission of above-mentioned field effect transistor, namely its threshold voltage can be obtained according to the input signal of field effect transistor and output signal.But for including the semi-conductor chip of multiple transistor, being exported by the threshold voltage of multiple transistor and measuring is a comparatively complicated problem, on the one hand, because the pin of semi-conductor chip is limited, if exported by the pin of the output signal of multiple transistor by semi-conductor chip, then can improve the reuse plan difficulty of chip pin; On the other hand, according to analog to digital converter, the output signal of transistor is converted to digital signal and exports, but the method needs to increase analog to digital conversion partial circuit in semi-conductor chip inside, the area of chip design difficulty and chip can be increased, also improve the Design and manufacture cost of semi-conductor chip.
Therefore, the present embodiment adopts oscillator 2, and the output signal of test transistor 11 is converted to pulse signal, and the frequency of this pulse signal and the threshold voltage of test transistor 11 can be one-to-one relationship.Concrete, above-mentioned oscillator 2 can adopt oscillator conventional in prior art, the voltage signal of analog quantity can be converted to digital pulse signal, especially periodic pulse signal, such as can adopt the oscillatory circuit be made up of odd level phase inverter, its input end is connected with the output terminal of test transistor 11.
The effect of above-mentioned to-be-measured cell 1 is exactly receive the enable signal and input signal that external circuit provides, and to make test transistor 11 conducting of its inside, and exports an electric signal according to this input signal and is supplied to oscillator 2.Those skilled in the art can design multiple circuit to realize the function of to-be-measured cell 1.
The technical scheme that the present embodiment provides adopts ranks code translator selected to-be-measured cell in to-be-measured cell array, test transistor in selected to-be-measured cell and oscillator couple together by ranks selector switch, to make oscillator, the signal that test transistor exports is converted to pulse signal, detected by the frequency of the pulse signal exported each to-be-measured cell correspondence, the fluctuation situation of each test transistor threshold voltage can be determined according to the fluctuation of frequency, also namely embodied the situation of transistor technology fluctuation.Compared with prior art, the technology that the present embodiment provides is comparatively simple, can realize carrying out detecting fast, easily to the technological fluctuation in semiconductor transistor sheet.
On the basis of technique scheme, to-be-measured cell 1, except comprising test transistor 11, can also comprise auxiliary detection transistor 12, and its structure is identical with test transistor 11, as shown in Figure 2.The data terminal of auxiliary detection transistor 12 is connected with the data terminal of test transistor 11, the control end of auxiliary detection transistor 12 and the control end of test transistor 11 receive enable signal anti-phase each other, during to make test transistor 11 conducting, auxiliary detection transistor 12 turns off, and when test transistor 11 turns off, auxiliary detection transistor 12 conducting, and send the signal for suppressing oscillator operation to oscillator 2, quit work to make oscillator.
Embodiments of the invention, all for field effect transistor, are described in detail the technological fluctuation detection system of semiconductor transistor.Field effect transistor is divided into n channel field-effect pipe and p channel field-effect pipe usually, and in the present embodiment, the source electrode of field effect transistor and drain electrode are called data terminal, and grid is called control end.
Above-mentioned test transistor 11 can be n channel field-effect pipe, and also can be p channel field-effect pipe, then to-be-measured cell array can have three kinds of forms, one, and the test transistor 11 in whole to-be-measured cell 1 is n channel field-effect pipe; Its two, the test transistor 11 in whole to-be-measured cell 1 is p channel field-effect pipe; Its three, wherein in part to-be-measured cell 1, test transistor 11 is n channel field-effect pipe, and the test transistor 11 in remaining to-be-measured cell 1 is p channel field-effect pipe.
For the situation that test transistor 11 is n channel field-effect pipe or p channel field-effect pipe, art technology people can design corresponding circuit structure to realize the function of above-mentioned to-be-measured cell 1.Embodiment two and embodiment three, with regard to the field effect transistor of two types, provide concrete implementation respectively.Wherein, embodiment two, when being p channel field-effect pipe for test transistor 11, providing a kind of implementation of to-be-measured cell 1 and oscillator 2, the to-be-measured cell 1 in embodiment two is called first kind to-be-measured cell; Embodiment three, when being n channel field-effect pipe for test transistor 11, providing the another kind of implementation of to-be-measured cell 1 and oscillator 2, the to-be-measured cell 1 in embodiment three is called Equations of The Second Kind to-be-measured cell.
When the test transistor 11 in whole to-be-measured cell 1 is p channel field-effect pipe, to-be-measured cell 1 can refer to the implementation that embodiment two provides; When the test transistor 11 in whole to-be-measured cell 1 is n channel field-effect pipe, to-be-measured cell 1 can refer to the implementation that embodiment three provides; When the test transistor 11 in part to-be-measured cell 1 is n channel field-effect pipe, test transistor 11 in remainder to-be-measured cell 1 is p channel field-effect pipe, also when namely two kinds of field effect transistor are present in to-be-measured cell array simultaneously, the implementation of embodiment two and embodiment three can be combined, the quantity of first kind to-be-measured cell and Equations of The Second Kind to-be-measured cell can match with ranks code translator.
Embodiment two
The structural representation of the to-be-measured cell that Fig. 5 provides for the embodiment of the present invention two and oscillator.As shown in Figure 5, the test transistor 11 that p channel field-effect pipe is formed is called the first test transistor MP0.To-be-measured cell 1 is except comprising the first test transistor MP0, and can also comprise the first auxiliary detection transistor MP1, its structure is identical with MP0, and namely MP0 and MP1 is p channel field-effect pipe.
The data terminal series connection of MP1 and MP0, concrete, the source electrode of MP1 receives high level signal (input signal namely in embodiment one), drain electrode is connected with the source electrode of MP0, the grounded drain of MP0, the source electrode of MP0, also as the output terminal of to-be-measured cell 1, is connected with oscillator 2.
The grid of MP0 and MP1 receives enable signal anti-phase each other, and turn off to realize the MP1 when MP0 conducting, MP1 can not affect the output signal of MP0.Can connect a phase inverter at the grid of MP1, the input end of this phase inverter and the grid of MP0 receive same enable signal.
Corresponding with p channel field-effect pipe, oscillator 2 can comprise the odd level phase inverter being in turn connected into ring-type, and wherein the output terminal of one-level phase inverter is as the output terminal of oscillator 2.First link of phase inverter at different levels receives high level signal, and the second link is all connected with the output terminal of to-be-measured cell 1.
The multiple implementation that can form the phase inverter of oscillator 2 is there is in prior art, the present embodiment proposes a kind of implementation of phase inverter for to-be-measured cell 1, concrete, every one-level phase inverter in odd level phase inverter can comprise the first field effect transistor T1 and the second field effect transistor T2, wherein, first field effect transistor T1 can be p channel field-effect pipe, and the second field effect transistor T2 can be n channel field-effect pipe.The source electrode of the first field effect transistor T1 receives high level signal as the first link of phase inverter, drain electrode is connected with the drain electrode of the second field effect transistor T2, the source electrode of the second field effect transistor T2, as the second link of phase inverter, also as the input end of oscillator 2, is connected with the output terminal of MP0.
The grid of the first field effect transistor T1 is connected with the grid of the second field effect transistor T2, and is connected with the output terminal of previous stage phase inverter as the input end of this grade of phase inverter, and the drain electrode of the first field effect transistor T1 is as the output terminal of this grade of phase inverter.
The course of work of above-mentioned to-be-measured cell 1 and oscillator 2 is: provide an enable signal by external circuit, and when this enable signal is high level signal 1, the signal that the grid of MP0 receives is that 1, MP0 turns off; Phase inverter in to-be-measured cell 1 is by after anti-phase for enable signal 1, and the signal that MP1 receives is 0, MP1 conducting, then the output terminal of to-be-measured cell 1 is charged to high level signal 1 by MP1 and is supplied to oscillator 2.The voltage difference that in oscillator 2, phase inverter two ends at different levels receive is approximately 0, then oscillator 2 can not export periodic pulse signal, and namely oscillator 2 does not work.
When this enable signal is low level signal 0, the phase inverter in to-be-measured cell 1 is by after anti-phase for enable signal 0, and the signal that MP1 receives is that 1, MP1 turns off; And the signal that the grid of MP0 receives is 0, MP0 conducting, because MP0 exists threshold voltage loss, the output terminal of to-be-measured cell 1 is discharged to GND+V by MP0
tH_p, this voltage signal, as the new earth potential of oscillator 2, allows oscillator 2 start vibration and output pulse signal, the frequency of this pulse signal and the threshold voltage V of MP0
tH_pcorresponding.
The technical scheme that the present embodiment provides is p channel field-effect pipe for test transistor, adopt oscillator that the electric signal that test transistor exports is converted to pulse signal, detect by the pulse signal frequency exported each test transistor correspondence and compare, namely the situation of the threshold voltage fluctuation of each test transistor can be obtained, and then the technological fluctuation situation of this to-be-measured cell array can be obtained, compared with prior art, the technology that the present embodiment provides is comparatively simple, can realize carrying out detecting fast, easily to the technological fluctuation in semiconductor transistor sheet.
In addition, in the present embodiment, in odd level phase inverter, the source electrode of the first field effect transistor T1 of every one-level phase inverter receives high level signal, and the source electrode of the second field effect transistor T2 is connected with the output terminal of to-be-measured cell, and the first test transistor MP0 outputs signal GND+V
tH_pto oscillator 2, as the new earth potential of oscillator 2, oscillator 2 is allowed to start vibration and output pulse signal.And when the first test transistor MP0 turns off, if the source electrode of each second field effect transistor T2 receives earth potential in oscillator 2, then also can vibrate, the present embodiment adopts the first auxiliary detection transistor MP1 when the first test transistor MP0 turns off, in oscillator 2, the source electrode of each second field effect transistor T2 provides a noble potential, then inhibit the work of oscillator 2, unnecessary energy consumption can be reduced on the one hand.On the other hand, it also avoid and when the first test transistor MP0 conducting, the device of its hot side and low potential side is protected, avoid occurring the situation of the direct short circuit of equipment of its hot side and low potential side to occur.
Embodiment three
The structural representation of the to-be-measured cell that Fig. 6 provides for the embodiment of the present invention three and oscillator.As shown in Figure 6, the test transistor 11 that n channel field-effect pipe is formed is called the second test transistor MN0.To-be-measured cell 1 is except comprising the second test transistor MN0, and can also comprise the second auxiliary detection transistor MN1, its structure is identical with MN0, and namely MN0 and MN1 is n channel field-effect pipe.
The data terminal series connection of MN0 and MN1, concrete, the source ground of MN1, the drain electrode of MN1 is connected with the source electrode of MN0, and the drain electrode of MN0 receives high level signal.The source electrode of MN0, also as the output terminal of to-be-measured cell 1, is connected with oscillator 2.
The grid of MN0 and MN1 receives enable signal anti-phase each other, and turn off to realize the MN1 when MN0 conducting, MN1 can not affect the output signal of MN0.Can connect a phase inverter at the grid of MN1, the input end of this phase inverter and the grid of MN0 receive same enable signal.
Corresponding with n channel field-effect pipe, oscillator 2 can comprise the odd level phase inverter being in turn connected into ring-type, and wherein the output terminal of one-level phase inverter is as the output terminal of oscillator 2.First link ground connection of phase inverter at different levels, the second link is all connected with the output terminal of to-be-measured cell 1.
The multiple implementation that can form the phase inverter of oscillator 2 is there is in prior art, the present embodiment proposes a kind of implementation for to-be-measured cell 1, concrete, every one-level phase inverter in odd level phase inverter can comprise the 3rd field effect transistor T3 and the 4th field effect transistor T4, wherein, 3rd field effect transistor T3 can be n channel field-effect pipe, and the 4th field effect transistor T4 can be p channel field-effect pipe.
The source electrode of the 3rd field effect transistor T3 is as the first link ground connection, the drain electrode of the 3rd field effect transistor T3 is connected with the drain electrode of the 4th field effect transistor T4, the source electrode of the 4th field effect transistor T4, as the second link, also as the input end of oscillator 2, is connected with the output terminal of MN1.
The grid of the 3rd field effect transistor T3 is connected with the grid of the 4th field effect transistor T4, and is connected with the output terminal of previous stage phase inverter as the input end of this grade of phase inverter, and the drain electrode of the 3rd field effect transistor T3 is as the output terminal of this grade of phase inverter.
The course of work of above-mentioned to-be-measured cell 1 and oscillator 2 is: provide an enable signal by external circuit, and when this enable signal is low level signal 0, the signal that the grid of MN0 receives is that 0, MN0 turns off; Phase inverter in to-be-measured cell 1 is by after anti-phase for enable signal 0, and the signal that MN1 receives is 1, MN1 conducting, then the output terminal of to-be-measured cell 1 is discharged to 0 by MN1 and is supplied to oscillator 2.The voltage difference that in oscillator 2, phase inverter two ends at different levels receive is approximately 0, then oscillator 2 can not export periodic pulse signal, that is: oscillator 2 does not work.
When this enable signal is high level signal 1, the phase inverter in to-be-measured cell 1 is by after anti-phase for enable signal 1, and the signal that MN1 receives is that 0, MN1 turns off; And the signal that the grid of MN0 receives is 1, MN0 conducting, because MN0 exists threshold voltage loss, the output terminal of to-be-measured cell 1 is charged to VDD-V by MN0
tH_n, this voltage signal is as the new power supply potential of oscillator 2, and allow oscillator start vibration and output pulse signal, the frequency of this pulse signal is corresponding with the threshold voltage of MN0.
The technical scheme that the present embodiment provides is n channel field-effect pipe for test transistor, adopt oscillator that the electric signal that test transistor exports is converted to pulse signal, detect by the pulse signal frequency exported each test transistor correspondence and compare, namely the situation of the threshold voltage fluctuation of each test transistor can be obtained, and then the technological fluctuation situation of this to-be-measured cell array can be obtained, compared with prior art, the technology that the present embodiment provides is comparatively simple, can realize carrying out detecting fast, easily to the technological fluctuation in semiconductor transistor sheet.
The technical scheme provided from above-described embodiment two and embodiment three, the voltage difference in oscillator 2 between the voltage at phase inverter two ends at different levels and ground is larger, and the speed of field effect transistor conducting is also faster, and the frequency of the pulse signal that oscillator 2 exports is also higher.Combined with to-be-measured cell 1 by oscillator 2, the threshold voltage of test transistor 11 is larger, and the frequency of the pulse signal that oscillator 2 exports is lower.Therefore, outputed signal between corresponding pulse signal frequency by multiple test transistor 11 and compare, namely can obtain the fluctuation relation between each test transistor 1 threshold voltage, and then know the technological fluctuation situation of to-be-measured cell array.
In addition, the source ground of the 3rd field effect transistor T3 of every one-level phase inverter in odd level phase inverter in the present embodiment, the source electrode of the 4th field effect transistor T4 is connected with the output terminal of to-be-measured cell 1, and the second test transistor MN0 outputs signal VDD-V
tH_nto oscillator 2, as the new noble potential of oscillator 2, oscillator is allowed to start vibration and output pulse signal.And when the second test transistor MN0 turns off, if the source electrode of each 4th field effect transistor T4 receives earth potential in oscillator 2, then also can vibrate, the present embodiment adopts the second auxiliary detection transistor MN1 when the second test transistor MN0 turns off, in oscillator 2, the source electrode of each 4th field effect transistor T4 is for an electronegative potential, then inhibit the work of oscillator 2, unnecessary energy consumption can be reduced on the one hand.On the other hand, it also avoid and when the second test transistor MN0 conducting, the device of its hot side and low potential side is protected, avoid occurring the situation of the direct short circuit of equipment of its hot side and low potential side to occur.
Embodiment four
On the basis of above-described embodiment two and embodiment three, for first kind to-be-measured cell and the simultaneous situation of Equations of The Second Kind to-be-measured cell, the structure of oscillator 2 can have multiple implementation, such as, can adopt following implementation:
Oscillator 2 comprises first kind oscillator and Equations of The Second Kind oscillator, and first kind oscillator can refer to embodiment two, and Equations of The Second Kind oscillator can refer to embodiment three.First kind oscillator can be corresponding with first kind to-be-measured cell, and wherein the first link of phase inverter at different levels receives high level signal, and the second link is all connected with the output terminal of first kind to-be-measured cell.Equations of The Second Kind oscillator can be corresponding with Equations of The Second Kind to-be-measured cell, wherein the first link ground connection of phase inverter at different levels, and the second link is all connected with the output terminal of Equations of The Second Kind to-be-measured cell.
The output terminal of selected first kind to-be-measured cell can be connected to the input end of first kind oscillator by ranks selector switch 4, and the output terminal of Equations of The Second Kind to-be-measured cell is connected to the input end of Equations of The Second Kind oscillator, respectively the voltage signal that two class test transistor 11 export is converted to pulse signal to make first kind oscillator and Equations of The Second Kind oscillator.
In addition, for above-mentioned first kind to-be-measured cell, after line decoder 31 and the respective output signal of column decoder 32 can be passed through a Sheffer stroke gate, the first test transistor MP0 is controlled as enable signal, specifically can refer to Fig. 7, the structural representation of first kind to-be-measured cell in the transistor technology surge detection system that Fig. 7 provides for the embodiment of the present invention four.
For above-mentioned Equations of The Second Kind to-be-measured cell, line decoder 31 and the respective output signal of column decoder 32 can be passed through one with behind the door, the second test transistor MN0 is controlled as enable signal, specifically can refer to Fig. 8, the structural representation of Equations of The Second Kind to-be-measured cell in the transistor technology surge detection system that Fig. 8 provides for the embodiment of the present invention four.
The course of work of above-mentioned transistor technology surge detection system is: line decoder 31 and column decoder 32 receive the address date that external circuit is sent, and identify row address and column address respectively, chooses corresponding to-be-measured cell.
If the to-be-measured cell chosen is first kind to-be-measured cell, then ranks selector switch 4 electric signal GND+V that the to-be-measured cell chosen is exported
tH_pbe sent to first kind oscillator, as the new earth signal of first kind oscillator, make first kind oscillator start concussion, and output pulse signal.
If the to-be-measured cell chosen is Equations of The Second Kind to-be-measured cell, then ranks selector switch 4 electric signal VDD-V that the to-be-measured cell chosen is exported
tH_nbe sent to Equations of The Second Kind oscillator, as the new power supply signal of Equations of The Second Kind oscillator, make Equations of The Second Kind oscillator start concussion, and output pulse signal.
Then the frequency of each pulse signal detected and compare, the fluctuation situation of frequency can be obtained, frequency due to pulse signal is corresponding relation with the threshold voltage of corresponding test transistor, therefore, can obtain the situation of threshold voltage fluctuation according to the situation of frequency jitter.
The technical scheme that the present embodiment provides is by forming array structure by least one to-be-measured cell, ranks code translator is adopted to select to-be-measured cell, adopt ranks selector switch by selected to-be-measured cell access oscillator, to make oscillator output pulse signal, the fluctuation situation of the threshold voltage of test transistor in to-be-measured cell can be known by the comparison of pulse signals frequency, and then know the technological fluctuation situation of test transistor.The detection system structure that the present embodiment provides is comparatively simple, can realize simply and detect the technological fluctuation situation of test transistor rapidly, especially detecting comparatively easily for the random fluctuation between the different crystal pipe of same chip inside.
On the basis of technique scheme, frequency divider 5 can also be set in transistor technology surge detection system, be connected to the output terminal of oscillator 2, can refer to Fig. 1.Frequency divider 5 carries out frequency division for the pulse signal exported oscillator 2, to reduce the frequency of pulse signal, is easy to analysis and comparison.
Simultaneously technique scheme includes first kind oscillator and Equations of The Second Kind oscillator in an oscillator, but to those skilled in the art, oscillator 2 also can only include the circuit structure of a set of oscillator, classification according to the to-be-measured cell chosen connects termination high level or ground connection by first of phase inverter at different levels in oscillator, and the second link connects to-be-measured cell.Concrete, technician can design suitable circuit structure, with when selected to-be-measured cell is for first kind to-be-measured cell, termination high level is connected by first of the phase inverters at different levels in oscillator, second link is connected to the output terminal of to-be-measured cell, and when selected to-be-measured cell is Equations of The Second Kind to-be-measured cell, by the first link ground connection of the phase inverters at different levels in oscillator, the second link is connected to the output terminal of to-be-measured cell.
Embodiment five
The process flow diagram of the transistor technology surge detection method that Fig. 9 provides for the embodiment of the present invention five.As shown in Figure 9, the transistor technology surge detection method that the present embodiment provides, can comprise following several step:
Step 101, the to-be-measured cell in the to-be-measured cell array be made up of at least two to-be-measured cells to be selected.
This step can be performed by the ranks code translator in transistor technology surge detection system.Include at least two to-be-measured cells in to-be-measured cell array, each to-be-measured cell composition matrix, ranks code translator is connected with each to-be-measured cell respectively, for selected some to-be-measured cells.
Step 102, the output signal of the test transistor in selected to-be-measured cell is converted to pulse signal, the frequency of pulse signal is corresponding with the threshold voltage of test transistor, to be determined the fluctuation of the threshold voltage of test transistor by the fluctuation of pulse signal frequency.
Test transistor in to-be-measured cell first can be connected to oscillator by ranks selector switch by this step, is then changed by the output signal of a pair of oscillators test transistor.
The specific implementation of above steps all can refer to the various embodiments described above, repeats no more herein.
The technical scheme that the present embodiment provides is by selecting the to-be-measured cell be made up of in array structure at least one to-be-measured cell, then the output signal of the test transistor in selected to-be-measured cell is converted to pulse signal, the fluctuation situation of the threshold voltage of test transistor in to-be-measured cell can be known by the comparison of pulse signals frequency, and then know the technological fluctuation situation of test transistor.The detection system structure that the present embodiment provides is comparatively simple, can realize simply and detect the technological fluctuation situation of test transistor rapidly, especially detecting comparatively easily for the random fluctuation between the different crystal pipe of same chip inside.
In addition, on the basis of technique scheme, pulse signals can also carry out frequency division, to reduce the frequency of pulse signal, by determining the frequency jitter situation of this pulse signal to the frequency jitter of the pulse signal after frequency division, be beneficial to compare the frequency of each pulse signal and analyze.Specifically realize by frequency divider.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (11)
1. a transistor technology surge detection system, is characterized in that, comprises to-be-measured cell array, ranks code translator, ranks selector switch and oscillator;
Described to-be-measured cell array is the array be made up of at least two to-be-measured cells;
Described ranks code translator is connected with each described to-be-measured cell respectively, for selected to-be-measured cell;
Described ranks selector switch is connected with the test transistor in described oscillator and each described to-be-measured cell respectively, for selected test transistor is connected to described oscillator; The output signal of described test transistor is converted to pulse signal by described oscillator, the frequency of described pulse signal is corresponding with the threshold voltage of described test transistor, to be determined the fluctuation of the threshold voltage of described test transistor by the fluctuation of described pulse signal frequency.
2. transistor technology surge detection system according to claim 1, it is characterized in that, described to-be-measured cell also comprises auxiliary detection transistor, and described in described auxiliary detection transistor AND gate, the structure of test transistor is identical;
The data terminal of described auxiliary detection transistor is connected with the data terminal of described test transistor, the control end of described auxiliary detection transistor and the control end of described test transistor receive enable signal anti-phase each other respectively, with when described test transistor turns off, described auxiliary detection transistor turns and suppress described oscillator operation.
3. transistor technology surge detection system according to claim 2, is characterized in that, described test transistor and auxiliary detection transistor are p channel field-effect pipe;
The source electrode of described auxiliary detection transistor receives high level signal, and drain electrode is connected with the source electrode of described test transistor, the grounded drain of described test transistor;
The source electrode of described test transistor, also as the output terminal of described test transistor, is connected with described oscillator.
4. transistor technology surge detection system according to claim 3, is characterized in that, described oscillator comprises the odd level phase inverter being in turn connected into ring-type, and wherein the output terminal of one-level phase inverter is as the output terminal of described oscillator;
First link of phase inverter at different levels receives high level signal, and the second link is all connected with the output terminal of described to-be-measured cell.
5. transistor technology surge detection system according to claim 4, it is characterized in that, every one-level phase inverter in described odd level phase inverter comprises the first field effect transistor and the second field effect transistor, described first field effect transistor is p channel field-effect pipe, and described second field effect transistor is n channel field-effect pipe;
The source electrode of described first field effect transistor receives high level signal, and drain electrode is connected with the drain electrode of described second field effect transistor; The source electrode of described second field effect transistor, as the input end of described oscillator, is connected with the output terminal of described auxiliary transistor;
The grid of described first field effect transistor is connected with the grid of described second field effect transistor, and is connected with the output terminal of previous stage phase inverter as the input end of described phase inverter, and the drain electrode of described first field effect transistor is as the output terminal of described phase inverter.
6. transistor technology surge detection system according to claim 2, is characterized in that, described test transistor and auxiliary detection transistor are n channel field-effect pipe;
The source ground of described auxiliary detection transistor, drain electrode is connected with the source electrode of described test transistor, and the drain electrode of described test transistor receives high level signal;
The source electrode of described test transistor, also as the output terminal of described test transistor, is connected with described oscillator.
7. transistor technology surge detection system according to claim 6, is characterized in that, described oscillator comprises the odd level phase inverter being in turn connected into ring-type, and wherein the output terminal of one-level phase inverter is as the output terminal of described oscillator;
First link ground connection of phase inverter at different levels, the second link is all connected with the output terminal of described to-be-measured cell.
8. transistor technology surge detection system according to claim 7, it is characterized in that, every one-level phase inverter in described odd level phase inverter comprises the 3rd field effect transistor and the 4th field effect transistor, described 3rd field effect transistor is n channel field-effect pipe, and described 4th field effect transistor is p channel field-effect pipe;
The source ground of described 3rd field effect transistor, drain electrode is connected with the drain electrode of described 4th field effect transistor; The source electrode of described 4th field effect transistor, as the input end of described oscillator, is connected with the output terminal of described auxiliary transistor;
The grid of described 3rd field effect transistor is connected with the grid of described 4th field effect transistor, and is connected with the output terminal of previous stage phase inverter as the input end of described phase inverter, and the drain electrode of described 3rd field effect transistor is as the output terminal of described phase inverter.
9. the transistor technology surge detection system according to any one of claim 1-8, is characterized in that, also comprise frequency divider; Described frequency divider is connected with described oscillator, carries out frequency division for the pulse signal exported described oscillator.
10. a transistor technology surge detection method, is characterized in that, comprising:
To-be-measured cell in the to-be-measured cell array be made up of at least two to-be-measured cells is selected;
The output signal of the test transistor in selected described to-be-measured cell is converted to pulse signal, the frequency of described pulse signal is corresponding with the threshold voltage of described test transistor, to be determined the fluctuation of the threshold voltage of described test transistor by the fluctuation of described pulse signal frequency.
11. transistor technology surge detection method according to claim 10, is characterized in that, also comprise:
Frequency division is carried out to described pulse signal, to be determined the frequency jitter of described pulse signal by the frequency jitter of the pulse signal after frequency division.
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