CN103376395A - Test structure of transistor alternating current hot carrier injection characteristics - Google Patents
Test structure of transistor alternating current hot carrier injection characteristics Download PDFInfo
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- CN103376395A CN103376395A CN201210133459XA CN201210133459A CN103376395A CN 103376395 A CN103376395 A CN 103376395A CN 201210133459X A CN201210133459X A CN 201210133459XA CN 201210133459 A CN201210133459 A CN 201210133459A CN 103376395 A CN103376395 A CN 103376395A
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Abstract
The invention discloses a test structure of transistor alternating current hot carrier injection characteristics. The test structure comprises a PMOS P1 to be tested, an NMOS N1 to be tested and a test load N2. A grid electrode of P1 and a grid electrode of N1 are connected to serve as a test pin a of the test structure, a source electrode of the P1 serves as a test pin b of the test structure, a substrate electrode of the P1 serves as a test pin c of the test structure, a drain electrode of the P1 and a drain electrode of the N1 are connected to serve as a test pin d of the test structure, a substrate electrode of the N1 serves as a test pin e of the test structure, a source electrode of the N1 serves as a test pin of the test structure, one end of the test load N2 is connected with the test pin d, and the other end of the test load N2 is grounded to serve as a test pin g of the test structure. The test structure can accurately simulate the working state of a CMOS in a circuit, can accurately evaluate characteristic changes of the PMOS and the NMOS in the CMOS after the PMOS and the NMOS bear alternating current HCI stress, and can also evaluate characteristic changes of the CMOS after the CMOS bears the alternating current HCI stress.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the test structure that a kind of transistor exchanges the hot carrier injection properties.
Background technology
Present interchange HCI (Hot Carrier Injection, hot carrier inject) test structure is the same with the DC test structure, all is independently PMOS or NMOS, perhaps with the common substrate electrode or (with) structure of source electrode.This independently structure often can only load AC signal to an end (grid or drain electrode) when load exchanging HCI stress, the other end is direct current signal, can not the real simulation circuit in the duty of CMOS, do not reach best evaluation effect.Whether if load AC signal for respectively the two ends (grid and drain electrode) of MOS device by two different equipment, it is synchronous then to be difficult to two signals of control, and the CMOS duty in therefore can not the real simulation circuit does not reach best evaluation effect.
Summary of the invention
The technical problem to be solved in the present invention provides the test structure that a kind of transistor exchanges the hot carrier injection properties, the duty of CMOS in the mimic channel exactly, and can estimate exactly PMOS and the characteristic variations (such as saturation current, linear current, mutual conductance, threshold voltage etc.) of NMOS after being subject to exchanging HCI stress among the CMOS, can also estimate CMOS itself characteristic variations (such as time-delay, electric leakage, power consumption etc.) after being subject to exchanging HCI stress.
For solving the problems of the technologies described above, test structure of the present invention comprises:
One PMOS P1 to be measured, a NMOS N1 to be measured, a test load N2; One PMOS P1 to be measured, a NMOS N1 to be measured forms the CMOS phase inverter;
The grid of P1, N1 links to each other as the test pin a of this test structure; The source electrode of P1 is as the test pin b of this test structure; The underlayer electrode of P1 is as the test pin c of this test structure; The drain electrode of P1, N1 links to each other as the test pin d of this test structure; The underlayer electrode of N1 is as the test pin e of this test structure; The source electrode of N1 is as the test pin f of this test structure; The termination test pin d of test load N2, other end ground connection is as the test pin g of this test structure;
Its duration of charging of described test load is consistent by the cycle that electronegative potential uprises current potential with AC signal, and its discharge time is consistent by the cycle of noble potential step-down current potential with AC signal, and its voltage equates with voltage on being carried in P1, N1; Wherein, described test load N2 is electric capacity.
The present invention utilizes the principle of work of phase inverter, to CMOS (Complementary metal-oxide-semiconductor, complementary metal oxide semiconductor (CMOS)) structure is transformed, so that improved structure can be estimated PMOS (the P-type MOS in the CMOS structure, P type MOS) and NMOS (N-type MOS, N-type MOS) interchange HCI (Hot Carrier Injection, hot carrier is injected) characteristic.When device being loaded interchange HCI stress, only need add an AC signal at the input end of CMOS, output terminal generates another AC signal automatically, the state when mimic channel is worked exactly.That can estimate simultaneously NMOS and PMOS exchanges the HCI characteristic, can save at least evaluation time of half.
The present invention not only can estimate the performance change of individual devices (NMOS or PMOS), more can estimate the performance change of CMOS itself, as: time-delay, power consumption, electric leakage.Can when considering DFR (Design for Reliability, reliability design), provide more help for circuit designers.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is structural representation of the present invention.
Embodiment
As shown in Figure 1, the test structure of transistor interchange hot carrier injection properties of the present invention comprises: PMOS P1, NMOS N1, testing capacitor N2;
The grid of P1, N1 links to each other as the test pin a of this test structure; The source electrode of P1 is as the test pin b of this test structure; The underlayer electrode of P1 is as the test pin c of this test structure; The drain electrode of P1, N1 links to each other as the test pin d of this test structure; The underlayer electrode of N1 is as the test pin e of this test structure; The source electrode of N1 is as the test pin f of this test structure; The termination test pin d of testing capacitor N2, other end ground connection is as the test pin g of this test structure;
Its duration of charging of described test load is consistent by the cycle that electronegative potential uprises current potential with AC signal, and its discharge time is consistent by the cycle of noble potential step-down current potential with AC signal, and its voltage equates with voltage on being carried in P1, N1.
Exchange the testing process of HCI, that is: loading HCI stress (only loading AC signal and voltage) → parameter testing (a test transistor parameter) → loading HCI stress → parameter testing ... circulation is until finish test successively, wherein loads HCI stress, parameter testing hockets.
Loading HCI stress path and parameter testing process can both carry out at the dedicated reliable property testing equipment that is equipped with pulse producer:
Test structure of the present invention is when loading HCI stress, and the signal loading method is as follows: a end: AC signal, the Vcc_max of the corresponding test transistor of its crest voltage (the maximum voltage that uses); B, c end: direct current noble potential stress generally equals transistorized Vcc_max; D end: unsettled; E, f, g end: ground connection.
When a end AC signal when low, N1 turn-offs, and can realize to P1 the stress loading of HCI, the output of d end is noble potential simultaneously, can implement charging (electric capacity has been finished discharge before) to electric capacity N2; When a end AC signal when being high, P1 turn-offs, and electric capacity N2 has finished charging and is in noble potential (requiring its voltage to equal the Vcc_max of NMOS), can realize the HCI stress loading to NMOS.Therefore, in whole AC signal in the cycle, that can finish simultaneously N1 and P1 exchanges the HCI stress loading.
Test structure of the present invention when parameter testing, signal loading method following (parameter test method that exchanges HCI and direct current HCI is consistent):
For N1, a end: grid; D end: drain electrode; E end: underlayer electrode (or P trap); F end: source electrode; B, c, g end: unsettled;
Can measure saturation current (I
D (sat)), linear current (I
D (lin)), mutual conductance (g
m), threshold voltage (V
Th) etc. characteristic.
For P1, a end: grid; B end: source electrode; C end: underlayer electrode (or N trap); D end: drain electrode; E, f, g end: unsettled;
Can measure the characteristics such as saturation current, linear current, mutual conductance, threshold voltage.
For CMOS, a end: input exchange signal; B, c end: direct current noble potential; E, f end: ground connection; D, g end: unsettled;
Can test the characteristics such as time-delay, electric leakage, power consumption.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (2)
1. the test structure of a transistor interchange hot carrier injection properties is characterized in that, comprising: a PMOS P1 to be measured, a NMOS N1 to be measured, a test load N2;
The grid of P1, N1 links to each other as the test pin a of this test structure; The source electrode of P1 is as the test pin b of this test structure; The underlayer electrode of P1 is as the test pin c of this test structure; The drain electrode of P1, N1 links to each other as the test pin d of this test structure; The underlayer electrode of N1 is as the test pin e of this test structure; The source electrode of N1 is as the test pin f of this test structure; The termination test pin d of test load N2, other end ground connection is as the test pin g of this test structure;
Its duration of charging of described test load is consistent by the cycle that electronegative potential uprises current potential with AC signal, and its discharge time is consistent by the cycle of noble potential step-down current potential with AC signal, and its voltage equates with voltage on being carried in P1, N1.
2. transistor exchanges the test structure of hot carrier injection properties as claimed in claim 1, and it is characterized in that: described test load N2 is electric capacity.
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| CN201210133459.XA CN103376395B (en) | 2012-04-28 | 2012-04-28 | The test structure of a kind of transistor exchange hot carrier in jection characteristic |
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| CN201210133459.XA CN103376395B (en) | 2012-04-28 | 2012-04-28 | The test structure of a kind of transistor exchange hot carrier in jection characteristic |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103969544A (en) * | 2014-03-04 | 2014-08-06 | 东莞博用电子科技有限公司 | Integrated circuit high-voltage pin connectivity testing method |
| CN105388353A (en) * | 2015-11-26 | 2016-03-09 | 中国工程物理研究院电子工程研究所 | Anti-noise SOI transistor light current test system design |
| WO2021249176A1 (en) * | 2020-06-08 | 2021-12-16 | 长鑫存储技术有限公司 | Method for testing hot current-carrying effect tolerance |
| WO2022142294A1 (en) * | 2021-01-04 | 2022-07-07 | 长鑫存储技术有限公司 | Hot carrier effect degradation performance evaluation method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103969544A (en) * | 2014-03-04 | 2014-08-06 | 东莞博用电子科技有限公司 | Integrated circuit high-voltage pin connectivity testing method |
| CN103969544B (en) * | 2014-03-04 | 2018-02-16 | 深圳博用科技有限公司 | A kind of integrated circuit high pressure pin continuity testing method |
| CN105388353A (en) * | 2015-11-26 | 2016-03-09 | 中国工程物理研究院电子工程研究所 | Anti-noise SOI transistor light current test system design |
| CN105388353B (en) * | 2015-11-26 | 2018-03-30 | 中国工程物理研究院电子工程研究所 | A kind of antinoise SOI transistor photoelectric current test system |
| WO2021249176A1 (en) * | 2020-06-08 | 2021-12-16 | 长鑫存储技术有限公司 | Method for testing hot current-carrying effect tolerance |
| US11953542B2 (en) | 2020-06-08 | 2024-04-09 | Changxin Memory Technologies, Inc. | Test method for tolerance against the hot carrier effect |
| WO2022142294A1 (en) * | 2021-01-04 | 2022-07-07 | 长鑫存储技术有限公司 | Hot carrier effect degradation performance evaluation method |
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| CN103376395B (en) | 2016-06-08 |
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