CN105337602A - Circuit and method for achieving two keys on single PAD - Google Patents
Circuit and method for achieving two keys on single PAD Download PDFInfo
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- CN105337602A CN105337602A CN201510790844.5A CN201510790844A CN105337602A CN 105337602 A CN105337602 A CN 105337602A CN 201510790844 A CN201510790844 A CN 201510790844A CN 105337602 A CN105337602 A CN 105337602A
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Abstract
The invention discloses a circuit and method for achieving two keys on a single PAD. The circuit comprises a first key, a second key, a PAD pin, a first key sampling circuit, a second key sampling circuit, a reference voltage device, a comparator and a key identification circuit, wherein one end of the first key is connected with the PAD pin and the other end is connected with a power source by a first resistor; one end of the second key is connected with the PAD pin and the other end is grounded via a second resistor; the output ends of the first and second key sampling circuits are connected with the PAD pin; and the first and second key sampling circuits are used for sampling the signals of the first and second keys according to the sequence signal interval. The circuit has the beneficial effects that two external keys are achieved on the single PAD through sampling control of the keys, thus avoiding the problem of key aliasing while saving the chip resources; and the circuit can be widely applied to keying circuit systems.
Description
Technical field
The present invention relates to integrated circuit input control field, particularly relate to circuit and method that a kind of single PAD realizes two buttons.
Background technology
PAD: chip pin.
Along with the development of semiconductor integrated circuit, integrated circuit (IC) chip technique used is more and more advanced, chip internal circuits integrated level is very high, internal logic circuit improves with technique that its circuit area is corresponding to be reduced, and the area of the PAD of chip can not reduce with the raising of technique, this just needs current chip product to reduce or multiplexing PAD as far as possible.Particularly applied chip product, the size of chip accounts for the major part of chip cost, reduces chip area and can reach the effect improving chip competitiveness equally.
In prior art, the application of chip button is divided into two kinds: single PAD realizes a button; Many PAD are realization matrix scanning buttons.
As shown in Figure 1, single PAD realizes a button; As shown in Figure 2, many PAD are realization matrix scanning buttons.Single PAD realizes one by key technology, if there is N number of button, just need the size of N number of PAD, PAD substantially can not diminish with the upgrading of technique, under this kind of technology, if button increases, inevasible increase chip area, the pin simultaneously bound increases equally, and package area increases, so not only make chip and packaging cost increase, and have great limitation in chip application place.Many PAD are realization matrix scanning buttons, effectively solve single PAD and realize one by the problem existing for key technology, but bring new problem simultaneously, if occur that three buttons or four buttons just may occur that button is made mistakes at any two lines of rank scanning, be exactly the string key that we often say, no matter this wrong identification is that software or hardware all cannot solve.
In sum, if use single PAD to realize a button, N number of button just needs N number of PAD, PAD area comparatively large, chip area can be caused so large to support by PAD, increase chip cost.If use many PAD to be realization matrix scanning, occur that three buttons will exist string key (the real button of None-identified) problem at any two lines of rank scanning; And cannot save PAD resource below 18 buttons, but the button of major applications product is all below ten buttons at present.
Summary of the invention
In order to solve the problems of the technologies described above, the object of this invention is to provide a kind of PAD resource both can saving chip, key circuit and the method for string key problem can be avoided again.
The technical solution adopted in the present invention is:
Single PAD realizes a circuit for two buttons, and it comprises the first button, the second button, PAD pin, the first button sample circuit, the second button sample circuit, reference voltage, comparator and recognition by pressing keys circuit; Described first button one end is connected with PAD pin, and the other end connects power supply by the first resistance; Described second button one end is connected with PAD pin, and the other end is by the second grounding through resistance; Described first button sample circuit is all connected with PAD pin with the output of the second button sample circuit, samples to the signal of the first button and the second button for being interrupted according to clock signal; Described PAD pin is for gathering the push button signalling of the first button and the second button, and its output is connected with the input of comparator; The output of described reference voltage is connected with the input of comparator; Described comparator for comparing the signal of PAD pin signal and reference voltage, and exports comparative result to recognition by pressing keys circuit; The described input of recognition by pressing keys circuit is connected with the output of voltage comparison module, for key range signal.
Preferably, described first button sample circuit comprises the first PMOS and the 3rd resistance, the source electrode of described first PMOS connects power supply by the 3rd resistance, the drain electrode of described first PMOS is connected to the negative input of PAD pin and comparator simultaneously, and the grid of described first PMOS is for receiving the first clock signal; Described second button sample circuit comprises the first NMOS tube and the 3rd resistance, the source electrode of described first NMOS tube is by the 4th grounding through resistance, the drain electrode of described first NMOS tube is connected to the negative input of PAD pin and comparator simultaneously, and the grid of described first NMOS tube is for receiving the second clock signal.
Preferably, described reference voltage comprises the second PMOS, second NMOS tube, 5th resistance, 6th resistance and the 7th resistance, described power supply is successively through the 5th resistance, 6th resistance and the 7th grounding through resistance, the source electrode of described second PMOS is connected to the node between the 5th resistance and the 6th resistance, the drain electrode of described second PMOS connects the electrode input end of comparator, the grid of described second PMOS is for receiving the first clock signal, the source electrode of described second NMOS tube is connected to the node between the 6th resistance and the 7th resistance, the drain electrode of described second NMOS tube is connected to the electrode input end of comparator, the grid of described second NMOS tube is for receiving the second clock signal.
Preferably, described first resistance is equal with the second resistance, and described 3rd resistance is equal with the 4th resistance, and described 5th resistance, the 6th resistance are equal with the 7th resistance, and the resistance of described 3rd resistance is five times of the first resistance.
Preferably, described comparator is differential comparator.
A kind of single PAD realizes the method for two buttons, it is applied to the circuit that a kind of single PAD realizes two buttons, described method comprises step: S1, produce two the first clock signals and the second clock signal that frequency is identical, phase place is different, described first clock signal and the second clock signal have the enable level of asynchronous detection; Whether whether S2, compare detection first button and press in the enable level time of the detection of the first clock signal, compare detection second button and press in the enable level time of the detection of the second clock signal.
Preferably, described step S2 specifically comprises sub-step: S21, in the enable level time of the detection of the first clock signal, control PAD pin pull-up, current PAD pin voltage and reference voltage are compared, according to the situation comparing output voltage and current clock signal, judge whether the first button is pressed; S22, in the enable level time of the detection of the second clock signal, control PAD pin is drop-down, current PAD pin voltage and reference voltage is compared, and according to the situation comparing output voltage and current clock signal, judges whether the second button is pressed.
Preferably, described first clock signal and the second clock signal comprise in one-period that the first button detects enable level time region, the second button detects enable level time region and PAD refire time region.
The invention has the beneficial effects as follows:
The present invention, by the controlling of sampling to button, single PAD realizes outside two buttons, reaches while saving resources of chip and avoids button string key problem.The present invention and single PAD realize the PAD resource saving chip large compared with a button, decrease the pin of binding and the area of encapsulation simultaneously; Compared with the present invention scans button with many PAD realization matrix, solve string key problem, and when button is less than 16, there is advantage at chip cost in the present invention equally.
The present invention can be widely used in key circuit system.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further:
Fig. 1 is the structural representation that prior art list PAD realizes a button;
Fig. 2 is the structural representation of prior art many PAD realization matrix scanning button;
Fig. 3 is the structural representation that list PAD of the present invention realizes two a kind of embodiments of key circuit;
Fig. 4 is the waveform schematic diagram of the present invention first clock signal and a kind of embodiment of the second clock signal;
Fig. 5 is the waveform schematic diagram of the present invention first clock signal and second clock signal the second embodiment.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.
As shown in Figure 3, single PAD realizes a circuit for two buttons, and it comprises the first button K1, second button K2, PAD pin PAD1/PAD2, the first button sample circuit, the second button sample circuit, reference voltage, comparator and recognition by pressing keys circuit (not shown); Described first button K1 one end is connected with PAD pin PAD1, and the other end meets power vd D by the first resistance R1; Described second button K2 one end is connected with PAD pin PAD1, and the other end is by the second resistance R2 ground connection; Described first button K1 sample circuit is all connected with PAD pin PAD1 with the output of the second button K2 sample circuit, samples to the signal of the first button K1 and the second button K2 for being interrupted according to clock signal; Described PAD pin PAD1 is for the push button signalling of sample the first button K1 and the second button K2, and its output is connected with the input of comparator; The output of described reference voltage is connected with the input of comparator; Described comparator for comparing the signal of PAD pin PAD1 signal and reference voltage, and exports comparative result to recognition by pressing keys circuit; The described input of recognition by pressing keys circuit is connected with the output of voltage comparison module, for key range signal.In this embodiment, the first button K1 sample circuit, the second button K2 sample circuit, reference voltage circuit, comparator and recognition by pressing keys circuit are all arranged on chip internal.
Preferably, described first button K1 sample circuit comprises the first PMOS and the 3rd resistance R3, the source electrode of described first PMOS meets power vd D by the 3rd resistance R3, the drain electrode of described first PMOS is connected to the negative input of PAD pin PAD1 and comparator simultaneously, and the grid of described first PMOS is for receiving the first clock signal CLK1; Described second button K2 sample circuit comprises the first NMOS tube and the 3rd resistance R3, the source electrode of described first NMOS tube is by the 4th resistance R4 ground connection, the drain electrode of described first NMOS tube is connected to the negative input of PAD pin PAD1 and comparator simultaneously, and the grid of described first NMOS tube is for receiving the second clock signal CLK2.
Preferably, described reference voltage comprises the second PMOS, second NMOS tube, 5th resistance R5, 6th resistance R6 and the 7th resistance R7, described power vd D is successively through the 5th resistance R5, 6th resistance R6 and the 7th resistance R7 ground connection, the source electrode of described second PMOS is connected to the node between the 5th resistance R5 and the 6th resistance R6, the drain electrode of described second PMOS connects the electrode input end of comparator, the grid of described second PMOS is for receiving the first clock signal CLK1, the source electrode of described second NMOS tube is connected to the node between the 6th resistance R6 and the 7th resistance R7, the drain electrode of described second NMOS tube is connected to the electrode input end of comparator, the grid of described second NMOS tube is for receiving the second clock signal CLK2.
Preferably, described first resistance R1 is equal with the second resistance R2 resistance, described 3rd resistance R3 is equal with the 4th resistance R4 resistance, and described 5th resistance R5, the 6th resistance R6 are equal with the 7th resistance R7 resistance, and the resistance of described 3rd resistance R3 is five times of the first resistance R1 resistance.
Preferably, described comparator is differential comparator.
In this embodiment, timing sequencer can be utilized to produce the first clock signal and the second clock signal, for gate pull-up resistor and comparative level; Comparator is utilized to compare the voltage that reference voltage and PAD pin input and export comparative result; Recognition by pressing keys module, the signal produced according to timing sequencer and comparator Output rusults, carrying out disappears trembles process, then identifies the button pressed really.Chip periphery be power supply, go here and there a button and resistance respectively with PAD pin.
As shown in Figure 3, this embodiment chip has two PAD pins, is respectively PAD1 and PAD2.For PAD1, the first clock signal CLK1, the second clock signal CLK2 control PAD pin PAD1 inside respectively upper drop-down.
Whether operation principle of the present invention is: when the first clock signal CLK1 is 0, pull-up is opened, now detect the first button K1 and press:
Condition 1, if now the first button K1 does not press, the voltage V of PAD1
pAD1=V
dD; (wherein, V
dDfor supply voltage)
Condition 2, if the first button K1 presses and the second button K2 does not press, due to R1=R2, R3=R4, so V
pAD1=(R2/ (R2+R3)) * V
dD;
Condition 03, also presses, due to R1=R2, R3=R4, so V if the first button K1 presses the second button K2 simultaneously
pAD1=((R1+R3)/(R1+2*R3)) * V
dD;
If R3=5*R1;
In condition 2, expression formula can be exchanged into V
pAD1=(1/6) * V
dD;
In condition 3, expression formula can be exchanged into V
pAD1=(6/11) * V
dD;
Equally, when the second clock signal CLK2 is 1, drop-downly to open, now detect the second button K2 and whether press:
Condition 4, if now K2 does not press, V
pAD1=0;
Condition 5, if K2 presses and K1 does not press, V
pAD1=(R3/ (R1+R3)) * V
dD;
Condition 6, also presses if K2 presses K1 simultaneously, V
pAD1=(R3/ (R1+2*R3)) * V
dD;
If R3=5*R1;
In condition 5, expression formula can be exchanged into VPAD1=(5/6) * VDD;
In condition 6, expression formula can be exchanged into VPAD1=(5/11) * VDD;
According to above-mentioned derivation, whether K2 presses, and detects VPAD1 and whether is more than or equal to (5/11) * VDD; Whether K1 presses, and detects VPAD1 and whether is less than or equal to (6/11) * VDD; Judge by accident to prevent button, we are located at 1/3VDD, 2/3VDD with reference to electrical voltage point, namely 3 resistance (the 5th resistance R5, the 6th resistance R6 and the 7th resistance R7) of connecting between VDD to ground carry out dividing potential drop, the voltage of 2 is linked the anode of comparator by the second PMOS MP2 and the second NMOS tube MN2, compare with the voltage timesharing of PAD pin.Result relatively gives recognition by pressing keys module, show whether respective keys is pressed.
The present invention also provides a kind of single PAD to realize the method for two buttons, it is applied to the circuit that a kind of single PAD realizes two buttons, described method comprises step: S1, produce two the first clock signals and the second clock signal that frequency is identical, phase place is different, described first clock signal and the second clock signal have the enable level of asynchronous detection; Whether whether S2, compare detection first button and press in the enable level time of the detection of the first clock signal, compare detection second button and press in the enable level time of the detection of the second clock signal.
Preferably, described step S2 specifically comprises sub-step: S21, in the enable level time of the detection of the first clock signal, control PAD pin pull-up, current PAD pin voltage and reference voltage are compared, according to the situation comparing output voltage and current clock signal, judge whether the first button is pressed; S22, in the enable level time of the detection of the second clock signal, control PAD pin is drop-down, current PAD pin voltage and reference voltage is compared, and according to the situation comparing output voltage and current clock signal, judges whether the second button is pressed.
Preferably, described first clock signal and the second clock signal comprise in one-period that the first button detects enable level time region, the second button detects enable level time region and PAD refire time region.Wherein, PAD refire time region can be used for other affairs of PAD pin disposal, as the I/O etc. of other signals.
Concrete, method flow of the present invention is:
Whether, when the first clock signal CLK1 is 0, pull-up is opened, now detect the first button K1 and press:
Condition 1, if now the first button K1 does not press, the voltage V of PAD1
pAD1=V
dD; (wherein, V
dDfor supply voltage)
Condition 2, if the first button K1 presses and the second button K2 does not press, due to R1=R2, R3=R4, so V
pAD1=(R2/ (R2+R3)) * V
dD;
Condition 03, also presses, due to R1=R2, R3=R4, so V if the first button K1 presses the second button K2 simultaneously
pAD1=((R1+R3)/(R1+2*R3)) * V
dD;
If R3=5*R1;
In condition 2, expression formula can be exchanged into V
pAD1=(1/6) * V
dD;
In condition 3, expression formula can be exchanged into V
pAD1=(6/11) * V
dD;
Equally, when the second clock signal CLK2 is 1, drop-downly to open, now detect the second button K2 and whether press:
Condition 4, if now K2 does not press, V
pAD1=0;
Condition 5, if K2 presses and K1 does not press, V
pAD1=(R3/ (R1+R3)) * V
dD;
Condition 6, also presses if K2 presses K1 simultaneously, V
pAD1=(R3/ (R1+2*R3)) * V
dD;
If R3=5*R1;
In condition 5, expression formula can be exchanged into VPAD1=(5/6) * VDD;
In condition 6, expression formula can be exchanged into VPAD1=(5/11) * VDD;
According to above-mentioned derivation, whether K2 presses, and detects VPAD1 and whether is more than or equal to (5/11) * VDD; Whether K1 presses, and detects VPAD1 and whether is less than or equal to (6/11) * VDD; Judge by accident to prevent button, we are located at 1/3VDD, 2/3VDD with reference to electrical voltage point, namely 3 resistance (the 5th resistance R5, the 6th resistance R6 and the 7th resistance R7) of connecting between VDD to ground carry out dividing potential drop, the voltage of 2 is linked the anode of comparator by the second PMOS MP2 and the second NMOS tube MN2, compare with the voltage timesharing of PAD pin.Result relatively gives recognition by pressing keys module, show whether respective keys is pressed.
The present invention, by the controlling of sampling to button, single PAD realizes outside two buttons, reaches while saving resources of chip and avoids button string key problem.The present invention and single PAD realize the PAD resource saving chip large compared with a button, decrease the pin of binding and the area of encapsulation simultaneously; Compared with the present invention scans button with many PAD realization matrix, solve string key problem, and when button is less than 16, there is advantage at chip cost in the present invention equally.
The present invention can be widely used in key circuit system.
More than that better enforcement of the present invention is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to spirit of the present invention, and these equivalent distortion or replacement are all included in the application's claim limited range.
Claims (8)
1. single PAD realizes a circuit for two buttons, it is characterized in that, it comprises the first button, the second button, PAD pin, the first button sample circuit, the second button sample circuit, reference voltage, comparator and recognition by pressing keys circuit;
Described first button one end is connected with PAD pin, and the other end connects power supply by the first resistance; Described second button one end is connected with PAD pin, and the other end is by the second grounding through resistance;
Described first button sample circuit is all connected with PAD pin with the output of the second button sample circuit, samples to the signal of the first button and the second button for being interrupted according to clock signal;
Described PAD pin is for gathering the push button signalling of the first button and the second button, and its output is connected with the input of comparator;
The output of described reference voltage is connected with the input of comparator;
Described comparator for comparing the signal of PAD pin signal and reference voltage, and exports comparative result to recognition by pressing keys circuit;
The described input of recognition by pressing keys circuit is connected with the output of voltage comparison module, for key range signal.
2. a kind of single PAD according to claim 1 realizes the circuit of two buttons, it is characterized in that, described first button sample circuit comprises the first PMOS and the 3rd resistance, the source electrode of described first PMOS connects power supply by the 3rd resistance, the drain electrode of described first PMOS is connected to the negative input of PAD pin and comparator simultaneously, and the grid of described first PMOS is for receiving the first clock signal; Described second button sample circuit comprises the first NMOS tube and the 3rd resistance, the source electrode of described first NMOS tube is by the 4th grounding through resistance, the drain electrode of described first NMOS tube is connected to the negative input of PAD pin and comparator simultaneously, and the grid of described first NMOS tube is for receiving the second clock signal.
3. a kind of single PAD according to claim 2 realizes the circuit of two buttons, it is characterized in that, described reference voltage comprises the second PMOS, second NMOS tube, 5th resistance, 6th resistance and the 7th resistance, described power supply is successively through the 5th resistance, 6th resistance and the 7th grounding through resistance, the source electrode of described second PMOS is connected to the node between the 5th resistance and the 6th resistance, the drain electrode of described second PMOS connects the electrode input end of comparator, the grid of described second PMOS is for receiving the first clock signal, the source electrode of described second NMOS tube is connected to the node between the 6th resistance and the 7th resistance, the drain electrode of described second NMOS tube is connected to the electrode input end of comparator, the grid of described second NMOS tube is for receiving the second clock signal.
4. a kind of single PAD according to claim 5 realizes the circuit of two buttons, it is characterized in that, described first resistance is equal with the second resistance, described 3rd resistance is equal with the 4th resistance, described 5th resistance, the 6th resistance are equal with the 7th resistance, and the resistance of described 3rd resistance is five times of the first resistance.
5. a kind of single PAD according to any one of claims 1 to 3 realizes the circuit of two buttons, it is characterized in that, described comparator is differential comparator.
6. single PAD realizes a method for two buttons, it is characterized in that, its a kind of single PAD be applied to as described in any one of claim 1 to 5 realizes the circuit of two buttons, and described method comprises step:
S1, produce two the first clock signals and the second clock signal that frequency is identical, phase place is different, described first clock signal and the second clock signal have the enable level of asynchronous detection;
Whether whether S2, compare detection first button and press in the enable level time of the detection of the first clock signal, compare detection second button and press in the enable level time of the detection of the second clock signal.
7. a kind of single PAD according to claim 6 realizes the method for two buttons, and it is characterized in that, described step S2 specifically comprises sub-step:
S21, in the enable level time of the detection of the first clock signal, control PAD pin pull-up, compares current PAD pin voltage and reference voltage, according to the situation comparing output voltage and current clock signal, judges whether the first button is pressed;
S22, in the enable level time of the detection of the second clock signal, control PAD pin is drop-down, current PAD pin voltage and reference voltage is compared, and according to the situation comparing output voltage and current clock signal, judges whether the second button is pressed.
8. a kind of single PAD according to claim 6 or 7 realizes the method for two buttons, it is characterized in that, described first clock signal and the second clock signal comprise in one-period that the first button detects enable level time region, the second button detects enable level time region and PAD refire time region.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510790844.5A CN105337602B (en) | 2015-11-17 | 2015-11-17 | A kind of list PAD realizes the circuit and method of two buttons |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510790844.5A CN105337602B (en) | 2015-11-17 | 2015-11-17 | A kind of list PAD realizes the circuit and method of two buttons |
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| CN105337602B CN105337602B (en) | 2018-09-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110190841A (en) * | 2019-06-06 | 2019-08-30 | 深圳市兆威机电股份有限公司 | I/O port multiplexing control circuit and electronic equipment |
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| US20140071714A1 (en) * | 2012-09-11 | 2014-03-13 | Chengdu Monolithic Power Systems Co., Ltd. | Switch mode power supply, control circuit and associated control method |
| CN205283514U (en) * | 2015-11-17 | 2016-06-01 | 深圳市汇春科技股份有限公司 | Single PAD realizes circuit of two buttons |
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| US5619196A (en) * | 1995-12-28 | 1997-04-08 | Universal Electronics Inc. | Single wire keyboard encode and decode circuit |
| CN102055357A (en) * | 2009-10-27 | 2011-05-11 | 聚辰半导体(上海)有限公司 | Switch power supply controller circuit and switch power supply system |
| CN102147448A (en) * | 2010-02-09 | 2011-08-10 | 联咏科技股份有限公司 | Keying operation detecting system and method |
| US20140071714A1 (en) * | 2012-09-11 | 2014-03-13 | Chengdu Monolithic Power Systems Co., Ltd. | Switch mode power supply, control circuit and associated control method |
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| CN110190841A (en) * | 2019-06-06 | 2019-08-30 | 深圳市兆威机电股份有限公司 | I/O port multiplexing control circuit and electronic equipment |
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|---|---|
| CN105337602B (en) | 2018-09-11 |
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