CN101521500A - Data-latching circuit adopting phase selector - Google Patents

Data-latching circuit adopting phase selector Download PDF

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CN101521500A
CN101521500A CN200810082309A CN200810082309A CN101521500A CN 101521500 A CN101521500 A CN 101521500A CN 200810082309 A CN200810082309 A CN 200810082309A CN 200810082309 A CN200810082309 A CN 200810082309A CN 101521500 A CN101521500 A CN 101521500A
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clock signal
data
signal
coupled
phase
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CN101521500B (en
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徐建昌
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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Abstract

The invention provides a data-latching circuit. The data-latching circuit comprises a first data-latching unit, a second data-latching unit, a third data-latching unit and a phase selector, wherein the first data-latching unit is used for latching a first input data according to a first clock signal and outputting a first output data; the second data-latching unit is used for latching the first output data according to a second clock signal and outputting a second output data; the third data-latching unit is used for latching the second output data according to a third clock signal and outputting an output data; and the phase selector is coupled with the second data-latching unit and used for generating the second clock signal according to the phase relation between the first and the third clock signals and outputting the second clock signal to the second data-latching unit.

Description

The data-latching circuit of adopting phase selector
Technical field
The present invention relates to a kind of data sink and method, particularly a kind of data-latching circuit of adopting phase selector and method.
Background technology
In some interface systems or relatively large chip, keeping each local clock of chip identical is challenge to system's maximum, usually all can comprise digital circuit part and artificial circuit part in the existing chip, and the digital circuit part has almost accounted for the main area more than 80% of chip, so, circuit designers is when the sequence problem of the whole integrated circuit of planning, normally remove to estimate the driving force of the clock partly exported from digital circuit and the capacity effect that the circuit layout cabling is produced by the Design of Digital Circuit aspect, and via analyzing and estimating the last retardation that arrives between the clock of artificial circuit part and clock that original clock source is exported, partly solve the problem of clock phase mistake at last via digital circuit, the situation of sequence problem can take place for when in the system two clock generators being arranged in another, these two clock generator institute clock signals are under nonsynchronous situation, and the problem (Timing Violation) on the sequential can take place for trigger or data latching element.
Will avoid clock inconsistent in general circuit design, prior art is to use two continuous D flip-flops to be used as the data latching element, goes the data that input is come in are carried out repeated sampling, to guarantee the correctness of data sampling.As shown in Figure 1, available data latch cicuit 100 includes the trigger 102,104,106 of three serial connections, wherein, receives input data D InTrigger 102 be by one first clock CLK 1Trigger, two follow-up continuous trigger devices 104,106 are then by another second clock CLK 2Trigger, the data output end by trigger 106 latchs a dateout D at last OutYet if the setting-up time (setup time) of trigger and data duration (hold time) are not enough, lock circuit 100 still can have the problem of error in data, as shown in Figure 2, and as trigger 104 sampled data D 1Obtain data D 2The time, the input data D if trigger 102 is being taken a sample In, then because data D 1Logical value just on the turn, so trigger 104 resulting data D 2Just can't guarantee correctly, thereby can further influence the dateout D of last generation OutCorrectness.In other words, latch the correctness that element (that is trigger 104,106) promotes sampled data even available data latch cicuit 100 is used two continuous datas, yet it still can be subjected to the first clock CLK 1With second clock CLK 2Between improper phase relation influence and have the probability of missampling.
Summary of the invention
Therefore one of main purpose of the present invention is to provide a kind of data-latching circuit of adopting phase selector and method to solve the problems referred to above.
According to embodiments of the invention, it discloses a kind of data-latching circuit.This data-latching circuit includes: one first data latch unit is used for importing data according to one first clock signal to latch one first, and exports one first dateout; One second data latch unit is used for according to a second clock signal latching this first dateout, and exports one second dateout; One the 3rd data latch unit is used for according to one the 3rd clock signal latching this second dateout, and exports a dateout; And a phase selector, be coupled to this second data latch unit, be used for producing this second clock signal to this second data latch unit according to the phase relation of this first, the 3rd clock signal.
Description of drawings
Fig. 1 is the schematic diagram of available data latch cicuit.
Fig. 2 is the time sequential routine figure of data-latching circuit shown in Figure 1.
Fig. 3 is the schematic diagram of an embodiment of data-latching circuit of the present invention.
Fig. 4 is the circuit diagram of an embodiment of phase selector shown in Figure 3.
Fig. 5 is the phase difference of first, second clock signal and the first corresponding relation schematic diagram of voltage.
Fig. 6 is the phase difference of first, second clock signal and the second corresponding relation schematic diagram of voltage.
Fig. 7 is the circuit diagram of another embodiment of phase selector shown in Figure 3.
Fig. 8 is the flow chart of an embodiment of data latching method of the present invention.
The reference numeral explanation
100、300 Data-latching circuit
102、104、106、302、304、306 Trigger
308 Phase selector
402 Phase detectors
404 Filter
406 Hysteresis buffer
408 Multiplexer
410 Inverter
412 Delay cell
Embodiment
See also Fig. 3, Fig. 3 is the schematic diagram of an embodiment of data-latching circuit 300 of the present invention.In the present embodiment, data-latching circuit 300 includes trigger (for example D flip-flop) 302,304,306 and one phase selector 308 of three serial connections, wherein, receives input data D InTrigger 302 be by one first clock CLK 1Trigger, the trigger 306 that produces dateout at last is then by another the 3rd clock CLK 3Trigger.For the trigger 304 in the middle of the place, position, it is by a second clock CLK 2Trigger and second clock CLK 2Be according to the first clock CLK by phase selector 308 1With the 3rd clock CLK 3Between phase relation produced, in the present embodiment, phase selector 308 is according to the first clock CLK 1With the 3rd clock CLK 3Between phase relation optionally use the 3rd clock CLK 3Or the 3rd clock CLK 3Inversion signal be used as second clock CLK 2Yet,, the present invention is not exceeded with inversion signal, also can adopt the 3rd clock CLK 3Delay clock signals as inventive embodiment.
See also Fig. 4, Fig. 4 is the circuit diagram of an embodiment of phase selector 308 shown in Figure 3.Phase selector 308 includes phase detectors 402, a filter 404, a magnetic hysteresis (hysteresis) buffer 406, a multiplexer 408 and an inverter 410.Among this embodiment, phase detectors 402 are implemented by an xor logic door, filter 404 is the low pass filters that are made of a resistance R and a capacitor C, and magnetic hysteresis (hysteresis) buffer 406 is implemented by Schmidt trigger (Schmitt trigger), please note, above-mentioned xor logic door, low pass filter and Schmidt trigger only are used as phase detectors 402, the example explanation of filter 404 and hysteresis buffer 406, in addition, inverter 410 also can be replaced by delay circuit, to produce needed clock phase, those elements are not to be necessary restrictive condition of the present invention.As shown in the figure, phase detectors 402 can compare the first clock CLK 1With the 3rd clock CLK 3Phase relation export a detection signal S d, then, filter 404 can be to detection signal S dCarry out Filtering Processing (that is low-pass filtering) and come smoothing detection signal S dWaveform to produce a filtering signal S f, wherein, an end of capacitor C can be set up filtering signal S fCorresponding voltage V aBecause hysteresis buffer 406 has hysteresis characteristic, supposes that hysteresis characteristic is by two critical value V TH_ 01 and V TH_ 10 (V TH_ 01〉V TH_ 10) defined, that is, as the hysteresis buffer 406 present control signal S that export cLogic level be " 0 " and voltage V aRise to and meet or exceed critical value V TH_ 01 o'clock, then hysteresis buffer 406 can make control signal S cBy logic level " 0 " transition to logic level " 1 "; On the other hand, as the hysteresis buffer 406 present control signal S that export cLogic level be " 1 " and voltage V aDrop to and reach or subcritical value V TH_ 10 o'clock, then hysteresis buffer 406 can make control signal S cBy logic level " 1 " transition to logic level " 0 ".In the present embodiment, use hysteresis buffer 406 can avoid multiplexer 408 because voltage V aSlight fluctuations promptly at the 3rd clock signal clk 3With its inversion signal CLK 3Constantly switch between _ the B, thereby cause the output instability of phase selector 308, may cause missampling at last.Yet, note that hysteresis buffer 406 can be omitted (optional) element if the slight output pulsation of phase selector 308 can not cause under the situation of system mistake.
See also Fig. 5 and Fig. 6, Fig. 5 is the first, the 3rd clock signal clk 1, CLK 3Phase difference and voltage V aThe first corresponding relation schematic diagram, and Fig. 6 is the first, the 3rd clock signal clk 1, CLK 3Phase difference and voltage V aThe second corresponding relation schematic diagram.If the first, the 3rd clock signal clk 1, CLK 3Have identical cycle (period) and work period (duty cycle), then when the first, the 3rd clock signal clk 1, CLK 3(positive edge differs from 180 degree) can make voltage V when inverting each other aCorrespond to maximum V Dd(V DdBe detection signal S dThe counterlogic level " 1 " time voltage level), and when the first, the 3rd clock signal clk 1, CLK 3Same phase time (positive edge alignment) can make voltage V aCorrespond to minimum value 0, wherein, the equal corresponding critical value V of phase difference PA, PD TH_ 10, and the equal corresponding critical value V of phase difference PB, PC TH_ 01.In addition, if the first, the 3rd clock signal clk 1, CLK 3Have the identical cycle, but have respectively the different work periods, then the first, the 3rd clock signal clk 1, CLK 3Phase difference and voltage V aRelation just as shown in Figure 6, suppose the first, the 3rd clock signal clk 1, CLK 3Cycle be T, and in the period of one-period T, first clock signal clk 1The time span and the 3rd clock signal clk of logic level " 1 " 3Time difference of time span of logic level " 1 " be T DcSo,, when the first, the 3rd clock signal clk 1, CLK 3(positive edge differs 180 degree) can be because time difference T when inverting each other DcA direct current side-play amount (T who is caused Dc/ T) * V DdAnd make voltage V aOnly can rise to V Dd-(T Dc/ T) * V DdBut not aforementioned maximum V Dd, and when the first, the 3rd clock signal clk 1, CLK 3Same phase time (positive edge alignment) can be because time difference T DcDc offset (the T that is caused Dc/ T) * V DdAnd make voltage V aOnly can drop to (T Dc/ T) * V DdBut not aforementioned minimum value 0.In sum, via suitable critical value V TH_ 01, V TH_ 10 set, and hysteresis buffer 406 just can normal operation under the different clocks condition.
At last, two inputs of multiplexer 408 can receive the 3rd clock signal clk respectively 3And correspondence the 3rd clock signal clk of being exported by inverter 410 3Inversion signal CLK 3_ B, and multiplexer 408 is just according to control signal S cLogic level export inversion signal CLK 3_ B or the 3rd clock signal clk 3With as triggering the required second clock CLK of trigger 304 2
See also Fig. 7, Fig. 7 is the circuit diagram of another embodiment of phase selector 308 shown in Figure 3.Except element shown in Figure 4, the phase selector 308 in the present embodiment includes a delay cell 412 in addition, is coupled to the output of multiplexer 408, is used for applying a retardation T dGive output signal (the 3rd clock signal clk of inverter 410 3Or corresponding to the 3rd clock signal clk 3Inversion signal CLK 3_ B), just export desired second clock signal CLK at last 2The setting of delay cell 412 is the phase relations that are used for further finely tuning between trigger 302,304 employed clock signals, that is allows first clock signal clk 1With second clock signal CLK 2The desirable rp state of convergence more, with further improvement because the data sampling problem that caused of the setting-up time (setup time) of trigger and data duration (hold time), in brief, the retardation T that delay cell 412 is provided dCan increase margin (margin) to avoid the generation of data sampling mistake.How to set the retardation T that delay cell 412 is applied dTo describe in detail down.
Retardation T for convenience of explanation dSetting, below only with the first, the 3rd clock signal clk 1, CLK 3Having identical cycle and work period is example.Please consult Fig. 5 and Fig. 7 simultaneously, when the first, the 3rd clock signal clk 1, CLK 3Between phase difference be promoted to above PB or be reduced to and be lower than PC, control signal S then cCan by logic level be " 0 " transition to logic level " 1 ", in addition, as control signal S cLogic level is " 1 " at present, and the first, the 3rd clock signal clk 1, CLK 3Between phase difference drop in the scope of PA-PD control signal S then cLogic level still can remain " 1 ".As control signal S cLogic level when being " 1 ", expression the first, the 3rd clock signal clk 1, CLK 3Than the anti-phase relation of convergence, therefore, multiplexer 408 can be selected output the 3rd clock signal clk 3As from the foregoing, select output the 3rd clock signal clk at multiplexer 408 3Situation under, retardation T dThis moment, maximum only can a corresponding phase difference (360-PD), so, at control signal S cLogic level be under the mode of operation of " 1 ", retardation T dJust have following restriction:
T d ≤ T · V TH _ 10 2 V dd Formula (1)
On the other hand, when the first, the 3rd clock signal clk 1, CLK 3Between phase difference be reduced to and be lower than PA or be promoted to, control signal S then above PD cCan by logic level be " 1 " transition to logic level " 0 ", in addition, as control signal S cPresent logic level is " 0 ", and the first, the 3rd clock signal clk 1, CLK 3Between phase difference do not drop in the scope of PB-PC control signal S then cLogic level still be maintained " 0 ".As control signal S cLogic level when being " 0 ", expression the first, the 3rd clock signal clk 1, CLK 3Than the same phase relation of convergence, therefore, multiplexer 408 can be selected output inversion signal CLK 3_ B.As from the foregoing, select output inversion signal CLK at multiplexer 408 3Under the situation of _ B, because the running of inverter 410 is equivalent to the delay that applies the 180 degree phase deviations of a correspondence, so retardation T dThis moment, maximum only can a corresponding phase difference (180-PB), so, at control signal S cLogic level be under the mode of operation of " 0 ", retardation T dJust have following restriction:
T d ≤ T · ( V dd - V TH _ 01 ) 2 V dd Formula (2)
In sum, for delay circuit 412 of the present invention, retardation T dSetting must meet following formula:
T d ≤ min { T · V TH _ 10 2 V dd , T · ( V dd - V TH _ 01 ) 2 V dd } Formula (3)
In formula (3), min{} gets minimum operation.
See also Fig. 8, Fig. 8 is the flow chart of an embodiment of data latching method of the present invention.Data latching method of the present invention is implemented by above-mentioned data-latching circuit 300, and its running is summarized as follows.Note that defined step execution sequence only is for convenience of explanation in the flow chart shown in Figure 8, is not to be restrictive condition of the present invention, and for example, under the prerequisite that obtains identical result, its execution order can be carried out or exchange to some step synchronously.
Step 800: phase relation and the 3rd clock signal according to the first, the 3rd clock signal produce the second clock signal;
Step 802: carry out the phase place fine setting? if then carry out step 804; Otherwise, carry out step 806;
Step 804: apply a retardation and give the second clock signal and adjust its phase place, then execution in step 806;
Step 806: use first clock signal to trigger first data latch unit and with input data latching that its data input pin received at its data output end;
Step 808: use second clock signal triggering second data latch unit and with input data latching that its data input pin received at its data output end; And
Step 810: use the 3rd clock signal to trigger the 3rd data latch unit and with input data latching that its data input pin received at its data output end.
In above-mentioned steps, first, second, third clock signal is corresponding above-mentioned CLK respectively 1, CLK 2, CLK 3, first, second, third data latch unit is then distinguished corresponding above-mentioned trigger 302,304,306.Note that because the running of data-latching circuit 300 is described in detail as above, so its performed corresponding data latching method gets the running of thin portion and does not just give unnecessary details in addition.
Data-latching circuit of the present invention has many different application categories in the application of reality, with data-latching circuit 300, the first clock CLK of first embodiment 1With the 3rd clock CLK 3Can be produced or different clock generators is produced by same clock generator, perhaps in this data-latching circuit 300, trigger 302 is arranged in the analog circuit, trigger 304,306 are arranged in the digital circuit, opposite, trigger 302 also can be arranged in the digital circuit, then trigger 304,306 are arranged in the analog circuit, in addition, data-latching circuit 300 also may be arranged on the different chips, for example, trigger 302 is the outputs that are set at a chip, and trigger 304,306 and 308 inputs that are set at another chip of phase selector, when trigger 302 outputting data signals, 304 a certain pin positions (Pin) that see through chip of trigger receive this data-signal, finish latching of data.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.

Claims (25)

1. data-latching circuit comprises:
First data latch unit is used for importing data according to one first clock signal to latch one first, and exports one first dateout;
Second data latch unit is used for according to a second clock signal latching this first dateout, and exports one second dateout;
The 3rd data latch unit is used for according to one the 3rd clock signal latching this second dateout, and exports a dateout; And
Phase selector is coupled to this second data latch unit, is used for producing this second clock signal to this second data latch unit according to the phase relation of this first, the 3rd clock signal.
2. data-latching circuit as claimed in claim 1, wherein, this first, second, third data latch unit is a trigger.
3. data-latching circuit as claimed in claim 1, wherein, the data output end of this first data latch unit is the data input pin that is serially connected with this second data latch unit, and the data output end of this second data latch unit is the data input pin that is serially connected with the 3rd data latch unit.
4. data-latching circuit as claimed in claim 1, wherein, this phase selector is to be used as this second clock signal according to the inversion signal that the phase relation of this first, the 3rd clock signal is optionally exported the 3rd clock signal or the 3rd clock signal.
5. data-latching circuit as claimed in claim 1, wherein, this phase selector comprises:
Phase detectors are coupled to this first, the 3rd clock signal, are used for detecting the phase relation of this first, the 3rd clock signal to produce a detection signal;
Phasing unit is coupled to the 3rd clock signal, is used for according to the 3rd clock signal wherein, having a phase difference between the 4th clock signal and the 3rd clock signal to produce one the 4th clock signal; And
Selected cell is coupled to this phasing unit and the 3rd clock signal, is used for optionally exporting the 3rd clock signal or the 4th clock signal with as this second clock signal according to this detection signal.
6. data-latching circuit as claimed in claim 5, wherein, these phase detectors are xor logic doors, are used for this first, the 3rd clock signal is carried out an xor logic computing to produce this detection signal.
7. data-latching circuit as claimed in claim 5, wherein, this phase selector comprises in addition:
Delay cell is coupled to this selected cell, is used for increasing the output of a retardation in this selected cell.
8. data-latching circuit as claimed in claim 5, wherein, this phasing unit is an inverter, and this inverter is to be used for receiving the 3rd clock signal to export the 4th clock number, wherein, has 180 ° phase difference in fact between the 4th clock number and the 3rd clock signal.
9. data-latching circuit as claimed in claim 5, wherein, this phase selector comprises in addition:
Filter is coupled to this phase detectors, is used for this detection signal is carried out filtering to produce a filtering signal; And
Hysteresis buffer, be coupled to this filter and this selected cell, be used for this filtering signal being converted to a control signal according to a hysteresis characteristic, and export this and control signal to this selected cell and control this selected cell and export the 3rd clock signal or the 4th clock number.
10. data-latching circuit as claimed in claim 8, wherein, this hysteresis buffer is a Schmidt trigger.
11. a data-latching circuit comprises:
First data latch unit is used for importing data according to one first clock signal to latch one first, and exports one first dateout;
Second data latch unit is used for according to a second clock signal latching this first dateout, and exports one second dateout; And
Phase selector is coupled to this second data latch unit, is used for producing this second clock signal to this second data latch unit according to the phase relation of this first clock signal and one the 3rd clock signal;
Wherein, this second clock signal be the 3rd clock signal or the 3rd clock signal inversion signal one of them.
12. data-latching circuit as claimed in claim 11, wherein, this phase selector comprises:
Phase detectors are coupled to this first, the 3rd clock signal, are used for detecting the phase relation of this first, the 3rd clock signal to produce a detection signal;
Inverter is coupled to the 3rd clock signal, is used for according to the 3rd clock signal to produce the inversion signal of the 3rd clock signal; And
Selected cell is coupled to this inverter and the 3rd clock signal, is used for optionally exporting according to this detection signal the inversion signal of the 3rd clock signal or the 3rd clock signal.
13. data-latching circuit as claimed in claim 12, wherein, these phase detectors are xor logic doors, are used for this first, the 3rd clock signal is carried out an xor logic computing to produce this detection signal.
14. data-latching circuit as claimed in claim 13, wherein, this phase selector comprises in addition:
Filter is coupled to this phase detectors, is used for this detection signal is carried out filtering to produce a filtering signal; And
Hysteresis buffer, be coupled to this filter and this selected cell, be used for this filtering signal being converted to a control signal according to a hysteresis characteristic, and export this and control signal to this selected cell and control the inversion signal that this selected cell is exported the 3rd clock signal or the 3rd clock signal.
15. data-latching circuit as claimed in claim 14, wherein, this hysteresis buffer is a Schmidt trigger.
16. a data-latching circuit comprises:
First data latch unit is used for importing data according to one first clock signal to latch one first, and exports one first dateout;
Second data latch unit is used for according to a second clock signal latching this first dateout, and exports one second dateout; And
Phase selector is coupled to this second data latch unit, is used for phase relation according to this first clock signal and one the 3rd clock signal to produce this second clock signal to this second data latch unit:
Wherein, this first clock signal is produced by different clock generators respectively with the 3rd clock signal.
17. data-latching circuit as claimed in claim 16, wherein, this phase selector comprises:
Phase detectors are coupled to this first, the 3rd clock signal, are used for detecting the phase relation of this first, the 3rd clock signal to produce a detection signal;
Phasing unit is coupled to the 3rd clock signal, is used for according to the 3rd clock signal wherein, having a phase difference between the 4th clock signal and the 3rd clock signal to produce one the 4th clock signal; And
Selected cell is coupled to this phasing unit and the 3rd clock signal, is used for optionally exporting the 3rd clock signal or the 4th clock signal with as this second clock signal according to this detection signal.
18. data-latching circuit as claimed in claim 17, wherein, this phase selector comprises in addition:
Filter is coupled to this phase detectors, is used for this detection signal is carried out filtering to produce a filtering signal; And
Hysteresis buffer, be coupled to this filter and this selected cell, be used for this filtering signal being converted to a control signal according to a hysteresis characteristic, and export this and control signal to this selected cell and control the inversion signal that this selected cell is exported the 3rd clock signal or the 3rd clock signal.
19. data-latching circuit as claimed in claim 16, wherein, this first data latch unit is arranged in the digital circuit, and this second data latch unit is arranged in the analog circuit.
20. data-latching circuit as claimed in claim 16, wherein, this first data latch unit is arranged in the analog circuit, and this second data latch unit is arranged in the digital circuit.
21. a data-latching circuit is used for latching input data, comprises:
First data latch unit is used for according to a clock signal latching this input data, and exports one first dateout;
Second data latch unit is used for according to a second clock signal latching this first dateout, and exports a dateout; And
Phase selector is coupled to this first data latch unit, is used for phase relation according to one first clock signal and this second clock signal to produce this clock signal to this first data latch unit:
Wherein, this first clock signal is produced by different clock generators with this second clock signal.
22. data-latching circuit as claimed in claim 21, wherein, this phase selector comprises:
Phase detectors are coupled to this first, second clock signal, are used for detecting the phase relation of this first, second clock signal to produce a detection signal;
Phasing unit is coupled to this second clock signal, is used for according to this second clock signal wherein, having a phase difference between the 3rd clock signal and this second clock signal to produce one the 3rd clock signal; And
Selected cell is coupled to this phasing unit, is used for optionally exporting this second clock signal or the 3rd clock signal with as this clock signal according to this detection signal.
23. data-latching circuit as claimed in claim 22, wherein, this phasing unit is an inverter, and this inverter is to be used for receiving this second clock signal to export the 3rd clock number, wherein, has 180 ° phase difference in fact between this second clock number and the 3rd clock signal.
24. data-latching circuit as claimed in claim 22, wherein, this phase selector comprises in addition:
Filter is coupled to this phase detectors, is used for this detection signal is carried out filtering to produce a filtering signal; And
Hysteresis buffer, be coupled to this filter and this selected cell, be used for this filtering signal being converted to a control signal according to a hysteresis characteristic, and export this and control signal to this selected cell and control this selected cell and export this second clock signal or the 3rd clock signal with as this clock signal.
25. data-latching circuit as claimed in claim 21, wherein, these input data are to import by the pin position of a chip.
CN200810082309A 2008-02-29 2008-02-29 Data-latching circuit adopting phase selector Active CN101521500B (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102122480A (en) * 2010-01-12 2011-07-13 瑞鼎科技股份有限公司 Data transmission method and data transmission structure
CN102638251A (en) * 2011-02-14 2012-08-15 南亚科技股份有限公司 Circuit for detecting and preventing setup fails and the method thereof
CN102780485A (en) * 2012-07-27 2012-11-14 华南理工大学 Configurable D latch for chaos computing
CN104375426A (en) * 2014-10-15 2015-02-25 成都振芯科技股份有限公司 Information processing and delay control circuit for phases between on-chip signals

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0556085A (en) * 1991-08-23 1993-03-05 Nec Ic Microcomput Syst Ltd Interface circuit
CN2872451Y (en) * 2005-11-01 2007-02-21 智多微电子（上海）有限公司 Dynamic switching circuit of clock

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102122480A (en) * 2010-01-12 2011-07-13 瑞鼎科技股份有限公司 Data transmission method and data transmission structure
CN102638251A (en) * 2011-02-14 2012-08-15 南亚科技股份有限公司 Circuit for detecting and preventing setup fails and the method thereof
CN102638251B (en) * 2011-02-14 2015-07-01 南亚科技股份有限公司 Circuit for detecting and preventing setup fails and the method thereof
CN102780485A (en) * 2012-07-27 2012-11-14 华南理工大学 Configurable D latch for chaos computing
CN102780485B (en) * 2012-07-27 2014-07-16 华南理工大学 Configurable D latch for chaos computing
CN104375426A (en) * 2014-10-15 2015-02-25 成都振芯科技股份有限公司 Information processing and delay control circuit for phases between on-chip signals

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