CN102967824A - Scan chain control circuit and implementation method thereof - Google Patents
Scan chain control circuit and implementation method thereof Download PDFInfo
- Publication number
- CN102967824A CN102967824A CN2011102558875A CN201110255887A CN102967824A CN 102967824 A CN102967824 A CN 102967824A CN 2011102558875 A CN2011102558875 A CN 2011102558875A CN 201110255887 A CN201110255887 A CN 201110255887A CN 102967824 A CN102967824 A CN 102967824A
- Authority
- CN
- China
- Prior art keywords
- scan chain
- configuration register
- control circuit
- control
- door
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a scan chain control circuit and an implementation method thereof. The scan chain control circuit comprises a scan chain which is connected with clock input, reset control, a test mode control signal and a scan enable signal, and a gate is connected with the scan chain and a configuration register. According to the scan chain control circuit, the configuration register is configured, and a scan chain function is started to perform a scanning test; and when a product test is finished, the configuration register is configured, the scan chain is disconnected, the access to the configuration register is canceled or hidden, so that the scan chain can not work, and a potential safety hazard that chip inner information is read through the scan chain can be eliminated. The invention further discloses an implementation method of the scan chain control circuit. The scan chain control circuit and the implementation method thereof can control the scan chain to disconnect or connect, and the safety of the chip inner information can be guaranteed.
Description
Technical field
The present invention relates to electronic chip and make the field, particularly relate to a kind of scan chain control circuit.The invention still further relates to a kind of implementation method of scan chain control.
Background technology
Along with the manufacturing development of electronic chip, the chip testing cost gradually in the whole manufacturing process proportion increasing, the volume production method of testing has been widely applied in the chip, for example the testing scanning chain method.But based on security consideration, Partial security class chip still uses the most original method of testing, causes the chip testing cost to reduce.Such as Fig. 1, scan chain circuits shown in Figure 2, all registers are subjected to external pin CLK (clock input), RST (control resets), TEST_MODE (test mode signal), SCAN_EN (scan enable signals) directly controls, the user can read the numerical value of any register at any time, so that whole chip internal information can be sayed without any secret, for the chip that is applied to some field, safety is the first element, the partial logic that safety of information inside chip can show as in the chip not can read, and traditional scan chain circuit and control method can't realize the control to scan chain, causes chip internal information to have potential safety hazard.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of scan chain control circuit, can disconnect or unlatching by the gated sweep chain, guarantees the safety of chip internal information.For this reason, the present invention also provides a kind of implementation method of scan chain control.For solving the problems of the technologies described above, scan chain control circuit of the present invention comprises:
A scan chain, this scan chain are connected with respectively clock input, reset control, test pattern control signal and scan enable signals, and wherein: one connects described scan chain, and described door connects a configuration register.
Described test pattern control signal is closed for " 1 ", and " 0 " when opening, described door is or door.
Described test pattern control signal is closed for " 0 ", and " 1 " when opening, described Men Weiyu door.
Described register can be set to and can't access.
A kind of scan chain control method may further comprise the steps:
(1) analyzing scan chains state determines that scan chain need control position and the quantity of node;
(2) determine the number bit wide of configuration register according to the quantity of control node in the step (1);
(3) determine the access mode of configuration register;
(4) definite Configuration Values of opening the scan chain configuration register;
(5) insert door according to Configuration Values described in the step (4) at the control node, and door is connected with register corresponding positions signal;
(6) carry out emulation testing.
During implementation step (5), the configuration register control signal is closed for " 1 ", and open " 0 ", inserts door to be or door.
During implementation step (5), the configuration register control signal is closed for " 0 ", and open " 1 ", inserts door to be or door.
When implementation step (1), need to consider following 2 points:
(A) the control node is more, and steering logic is more complicated, and the probability that is broken is just lower, but can increase accordingly the expense of area and sequential, so need to control according to the actual requirements Node configuration, has a control node on each scan chain at least;
(B) the at random mode of chosen position can be taked in the position of control node, and prerequisite is other performances that can not affect chip, and for example sequence problem is namely controlled node and can not be designed on critical path; Can not affect chip functions equally, for example can not be placed on the very high register of utilization factor, avoid fighting for original just very nervous placement-and-routing's resource.
Scan chain control circuit of the present invention can by configuration register is configured, be opened the scan chain function under test pattern, carry out sweep test; Finish when product test, configuration register is configured, disconnect scan chain, and the access of cancellation or hiding these configuration registers, scan chain can't be worked, can eliminate the potential safety hazard that reads chip internal information by scan chain.Scan chain control circuit of the present invention and its implementation can disconnect or unlatching by the gated sweep chain, guarantee the safety of chip internal information
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is a kind of traditional scan chain structural representation.
Fig. 2 is the inner structure synoptic diagram of ScanChain1 among Fig. 1.
Fig. 3 is the structural representation of scan chain control circuit one embodiment of the present invention.
Fig. 4 is the inner structure synoptic diagram of ScanChain1 among Fig. 3.
Fig. 5 is the process flow diagram of scan chain control method of the present invention.
Description of reference numerals
ScanChain1, ScanChain2, ScanChain3, ScanChainN are the scan chain numberings
CLK is the clock input
RST is the control that resets
TEST_MODE is the test pattern control signal
SCAN_EN is scan enable signals
1, the 2nd, the control node
Embodiment
As shown in Figure 3, Figure 4, scan chain control circuit one embodiment of the present invention comprises:
Article three, scan chain, be numbered: ScanChain1 to ScanChain3, every scan chain is connected with respectively clock input (CLK), the control (RST) that resets, test pattern control signal (TEST_MODE) and scan enable signals (SCAN_EN), wherein, the PART1 of ScanChain1 and the control node 1 between the PART2 have one or the door, control node 2 between PART2 and the PART 3 have one with the door, one configuration register connect described or door and with door, the disconnection of gated sweep chain or unlatching.
Wherein, control node 1 is closed for " 1 " in the configuration register control signal, and open " 0 "; Control node 2 is closed for " 0 " in the configuration register control signal, and open " 1 ".
As shown in Figure 5, scan chain control method of the present invention comprises:
(1) analyzing scan chains state determines that scan chain need control position and the quantity of node;
(2) determine the number bit wide of configuration register according to the quantity of control node in the step (1);
(3) determine the access mode of configuration register;
(4) definite Configuration Values of opening the scan chain configuration register;
(5) insert door according to Configuration Values described in the step (4) at the control node, door is connected with register corresponding positions signal;
Wherein, the configuration register control signal is closed for " 1 ", and open " 0 ", inserts door to be or door; The configuration register control signal is closed for " 0 ", and open " 1 ", inserts door to be or door.
(6) carry out emulation testing.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (7)
1. scan chain control circuit comprises: one scan chain, this scan chain are connected with clock input, reset control, test pattern control signal and scan enable signals, it is characterized in that: one connects described scan chain, described door connection one configuration register.
2. scan chain control circuit as claimed in claim 1 is characterized in that: described test pattern control signal is closed for " 1 ", and " 0 " when opening, described door be or.
3. scan chain control circuit as claimed in claim 1 is characterized in that: described test pattern control signal is closed for " 0 ", and " 1 " when opening, described Men Weiyu door.
4. scan chain control circuit as claimed in claim 1, it is characterized in that: described configuration register can be set to and can't access.
5. a scan chain control method is characterized in that, may further comprise the steps:
(1) analyzing scan chains state determines that scan chain need control position and the quantity of node;
(2) determine the number bit wide of configuration register according to the quantity of control node in the step (1);
(3) determine the access mode of configuration register;
(4) definite Configuration Values of opening the scan chain configuration register;
(5) insert door according to Configuration Values described in the step (4) at the control node, and door is connected with register corresponding positions signal;
(6) carry out emulation testing.
6. method as claimed in claim 5 is characterized in that: during implementation step (5), the configuration register control signal is closed for " 1 ", and open " 0 ", insert door and be or.
7. method as claimed in claim 5 is characterized in that: during implementation step (5), the configuration register control signal is closed for " 0 ", and open " 1 ", insert door and be or.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110255887.5A CN102967824B (en) | 2011-08-31 | 2011-08-31 | A kind of scan chain control circuit and its implementation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110255887.5A CN102967824B (en) | 2011-08-31 | 2011-08-31 | A kind of scan chain control circuit and its implementation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102967824A true CN102967824A (en) | 2013-03-13 |
| CN102967824B CN102967824B (en) | 2016-05-25 |
Family
ID=47798101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110255887.5A Expired - Fee Related CN102967824B (en) | 2011-08-31 | 2011-08-31 | A kind of scan chain control circuit and its implementation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102967824B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104346583A (en) * | 2013-07-23 | 2015-02-11 | 阿尔特拉公司 | Method and apparatus for securing configuration scan chains of a programmable device |
| CN106324463A (en) * | 2015-06-19 | 2017-01-11 | 上海华虹集成电路有限责任公司 | Scan chain control circuit design method and scan chain circuit |
| CN106556792A (en) * | 2015-09-28 | 2017-04-05 | 飞思卡尔半导体公司 | The integrated circuit of security sweep can be carried out |
| CN107452323A (en) * | 2016-05-31 | 2017-12-08 | 无锡华润矽科微电子有限公司 | Realize the circuit and method that any passage continuously scans |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5357572A (en) * | 1992-09-22 | 1994-10-18 | Hughes Aircraft Company | Apparatus and method for sensitive circuit protection with set-scan testing |
| CN1460923A (en) * | 2003-06-25 | 2003-12-10 | 中国科学院计算技术研究所 | Single-output feedback-free sequential test response compression circuit |
| CN101627370A (en) * | 2007-02-28 | 2010-01-13 | 惠瑞捷（新加坡）私人有限公司 | The position of the stuck-at defect in the scan chain of estimation device under test |
| CN102565684A (en) * | 2010-12-13 | 2012-07-11 | 上海华虹集成电路有限责任公司 | Security-based scan chain control circuit, scan chain testing circuit and use method |
| CN102692595A (en) * | 2011-03-25 | 2012-09-26 | Nxp股份有限公司 | Circuit for securing scan chain data |
-
2011
- 2011-08-31 CN CN201110255887.5A patent/CN102967824B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5357572A (en) * | 1992-09-22 | 1994-10-18 | Hughes Aircraft Company | Apparatus and method for sensitive circuit protection with set-scan testing |
| CN1460923A (en) * | 2003-06-25 | 2003-12-10 | 中国科学院计算技术研究所 | Single-output feedback-free sequential test response compression circuit |
| CN101627370A (en) * | 2007-02-28 | 2010-01-13 | 惠瑞捷（新加坡）私人有限公司 | The position of the stuck-at defect in the scan chain of estimation device under test |
| CN102565684A (en) * | 2010-12-13 | 2012-07-11 | 上海华虹集成电路有限责任公司 | Security-based scan chain control circuit, scan chain testing circuit and use method |
| CN102692595A (en) * | 2011-03-25 | 2012-09-26 | Nxp股份有限公司 | Circuit for securing scan chain data |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104346583A (en) * | 2013-07-23 | 2015-02-11 | 阿尔特拉公司 | Method and apparatus for securing configuration scan chains of a programmable device |
| CN106324463A (en) * | 2015-06-19 | 2017-01-11 | 上海华虹集成电路有限责任公司 | Scan chain control circuit design method and scan chain circuit |
| CN106556792A (en) * | 2015-09-28 | 2017-04-05 | 飞思卡尔半导体公司 | The integrated circuit of security sweep can be carried out |
| CN107452323A (en) * | 2016-05-31 | 2017-12-08 | 无锡华润矽科微电子有限公司 | Realize the circuit and method that any passage continuously scans |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102967824B (en) | 2016-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20220221513A1 (en) | Chip, chip testing method and electronic device | |
| CN106556792B (en) | Integrated circuit capable of secure scanning | |
| US10347630B2 (en) | Semiconductor chip using logic circuitry including complementary FETs for reverse engineering protection | |
| US8051345B2 (en) | Method and apparatus for securing digital information on an integrated circuit during test operating modes | |
| CN112115664B (en) | Multi-mode multi-clock domain chip integrated control system | |
| CN104101828B (en) | Anti- hardware Trojan horse circuit design method based on activation probability analysis | |
| CN102967824A (en) | Scan chain control circuit and implementation method thereof | |
| CN104951698B (en) | The circuit safety design for Measurability method of inactive hardware Trojan horse and the detection method to hardware Trojan horse can be detected | |
| CN109039307A (en) | It is double along Anti-shaking circuit structure | |
| CN103631738A (en) | Off-chip configuration and readback FPGA device | |
| CN105068950A (en) | Pin multiplexing system and method | |
| CN102831934A (en) | Method for entering into internal test mode of ASRAM chip | |
| CN102565684A (en) | Security-based scan chain control circuit, scan chain testing circuit and use method | |
| US8397079B2 (en) | Method and apparatus for securing digital information on an integrated circuit read only memory during test operating modes | |
| CN105760558B (en) | The layout method of multi input look-up table in fpga chip | |
| US6990647B2 (en) | Variable stage ratio buffer insertion for noise optimization in a logic network | |
| CN106324463A (en) | Scan chain control circuit design method and scan chain circuit | |
| KR20040098690A (en) | Signal squelch detector and signal detecting method | |
| CN106571815A (en) | Level-type high-resistance digital phase discriminator | |
| CN102565665B (en) | Circuit detection device and circuit detection method | |
| CN107340992A (en) | A kind of fixed-point data screening circuit | |
| US7231572B2 (en) | Method and circuit for parametric testing of integrated circuits with an exclusive-or logic tree | |
| CN106407533B (en) | A kind of comprehensive optimization method of register | |
| US20230366931A1 (en) | Secure joint test action group (jtag) | |
| CN104750481A (en) | FPGA output pin multiplex circuit, method and equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160525 Termination date: 20210831 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |