CN101488742A - Electric level converting apparatus and method - Google Patents
Electric level converting apparatus and method Download PDFInfo
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- CN101488742A CN101488742A CNA2008100029983A CN200810002998A CN101488742A CN 101488742 A CN101488742 A CN 101488742A CN A2008100029983 A CNA2008100029983 A CN A2008100029983A CN 200810002998 A CN200810002998 A CN 200810002998A CN 101488742 A CN101488742 A CN 101488742A
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Abstract
The invention provides a level switching device and a method thereof, wherein, the level switching device comprises a first level switching circuit and an output stage circuit, wherein, the first level switching is used for receiving the input of a first working-voltage level and converting the first working-voltage level into a positive second working-voltage level and a negative second working-voltage level; and the output stage circuit is used for producing the output according to the electric potential height between the positive and the negative second working-voltage levels.
Description
Technical field
The present invention relates to a kind of level converter (Level Shift Device), referring to especially a kind ofly can provide the work period close level converter and method thereof.
Background technology
For asking the saving energy consumption, current trends are the internal work voltage (for example 1.2V even lower) that downgrades circuit chip, but the communication voltage between chip and the chip then still must be gone up execution in higher voltage (for example 3.3V).Therefore, must use level converter to be used as the input/output interface circuit of chip, convert the general higher operating voltage of chip chamber ditch to lower operating voltage with chip internal.Level converter 10 in the prior art, its basic structure roughly as shown in Figure 1, comprising two PMOS transistor M1, M2 and two nmos pass transistor M3, M4.The purpose of supposing circuit is to convert the builtin voltage of 1.2V to 3.3V, and then the input IN in the circuit can use the operating voltage (calling first operating voltage in the following text) of 1.2V, and the voltage of VP2 can be 3.3V (calling second operating voltage in the following text).
Please also refer to Fig. 1 and Fig. 2, the working method of this circuit is as follows.Suppose that when time T 0 initial condition of circuit is: input IN is in the low level (for example 0V) of first operating voltage, and anti-phase input INB is at the high level (for example 1.2V) of first operating voltage.Because anti-phase input INB is at high level, so nmos pass transistor M4 conducting, Node B is by nmos pass transistor M4 ground connection, so be positioned at the low level of 0V; Because of the voltage of Node B promptly equals to export the voltage of OUT, so export OUT also in 0V (low level of second operating voltage).And in low level, so PMOS transistor M1 conducting, voltage VP2 arrives node A by PMOS transistor M1, so node A is in the high level (high level of second operating voltage, for example 3.3V) that is equal to VP2 because of Node B.And because node A is in high level, so PMOS transistor M2 closes, the voltage of VP2 can not influence the voltage of output OUT.
When this circuit need produce high pressure output, shown in during as Fig. 2 time T 1, input IN changes over high level by low level, this moment is because nmos pass transistor M3 conducting, so node A is by nmos pass transistor M3 ground connection, but when conversion instantaneous (transition state), PMOS transistor M1 also still is in conducting state, so the voltage of VP2 still influences node A, the voltage that makes this place is not to arrive low level at once, but slowly descends from high level; PMOS transistor M2 is controlled by node A, so also conducting gradually thereupon, when time T 2, the complete conducting of PMOS transistor M2 so voltage VP2 could arrive Node B by PMOS transistor M2 fully, draws high to the high level that is equal to VP2 output voltage OUT, and simultaneously, voltage arrival high level because of Node B so PMOS transistor M1 also just closes fully, makes node A be stabilized in the low level of 0V.
Shown in Figure 2, at PMOS transistor M1 and corresponding nmos pass transistor M3, PMOS transistor M2 and corresponding nmos pass transistor M4, under the suitable each other situation of its driving force, the ideal waveform that is produced.But generally speaking; change in low pressure under the situation of high pressure; be the strength serious offense PMOS transistor M1 that really makes nmos pass transistor M3, M4, the strength of M2; particularly consider when nmos pass transistor and be in the most bad situation and PMOS transistor when being in optimum; nmos pass transistor M3, M4 must still can drive PMOS transistor M1, M2; therefore the width of nmos pass transistor M3, M4 can be strengthened usually, its driving force is strengthened.But thus, the driving force of PMOS transistor M1 is weaker than corresponding nmos pass transistor M3, PMOS transistor M2 and is weaker than corresponding nmos pass transistor M4, to cause producing waveform shown in Figure 3, wherein the output signal of level converter from low transition the time to high level, far beyond its from high level be converted to the low level time slowly, ask for an interview time T 2, T3, T4, T5.
See also Fig. 4, when the time of high-low level conversion is unbecoming, will cause the work period of high-low level unequal (TL〉TH) (in other words, the time of the rise and fall of signal is inequality).If when this level converter is applied to DDR DRAM or its relevant similar products, because the rise and fall edge of signal all is significant, so the work period of high-low level is unequal, will have a strong impact on the correctness as frequency signal, data-signal, data sampling (data strobe) signal etc.If desire ensures that signal is correct, then Signal Processing time such as lead time (set-uptime) and retention time (hold time) etc. all must prolong, and reduce the performance of circuit.
Therefore, be necessary to propose a kind of can providing and export close level converter of high-low level work period.
Summary of the invention
The present invention's first purpose is providing a kind of close level converter of high-low level work period that can keep exporting.
The present invention's second purpose is providing a kind of level conversion method.
For reaching above-mentioned purpose, the invention provides a kind of level converter, comprise: first level shifting circuit in order to accept the input of first operational voltage level, converts the second just anti-phase operational voltage level to; And output-stage circuit, it is exported and produce according to the mutual current potential height of this second just anti-phase operational voltage level.
In aforementioned level converter, its output-stage circuit for example can be comparator or another level shifting circuit.
In addition, the present invention also provides a kind of level conversion method, comprising: with the input of first operational voltage level, convert the second just anti-phase operational voltage level to; And according to the correlation between this second just anti-phase operational voltage level, the decision output level.
In foregoing circuit and the method, preferably, when second operational voltage level of positive is higher than the second anti-phase operational voltage level, be output as high level; When the second anti-phase operational voltage level is higher than second operational voltage level of positive, be output as low level.
The effect that should be easier to understand purpose of the present invention, technology contents, characteristics and be reached is described in detail by specific embodiment below.
Description of drawings
Fig. 1 is the circuit diagram of the level converter of prior art.
Corresponding time diagram when Fig. 2 is the input and output generation conversion of level converter of prior art.
Fig. 3 and Fig. 4 illustrate the schematic diagram of the problem that prior art meets with.
Fig. 5 is the circuit diagram according to the level converter of first embodiment of the invention.
Corresponding time diagram when Fig. 6 shows the input and output generation conversion of Fig. 5 circuit.
Fig. 7 is the circuit diagram according to the level converter of second embodiment of the invention.
Corresponding time diagram when Fig. 8 shows the input and output generation conversion of Fig. 7 circuit.
The primary clustering symbol description
10 level converters, 20 level shifting circuits
30 comparators, 40 level shifting circuits
100 level converters, 200 level converters
A, B node IN input
The anti-phase input of INB M1, M2, M3, M4 transistor
M5, M6, M7, M8 transistor OUT output
The anti-phase output of OUTB VP2 second operating voltage
Embodiment
In following all embodiment, for the purpose of convenient illustrations, the high level of supposing first operating voltage is 1.2V, and low level is 0V, and the high level of the second operating voltage VP2 is 3.3V, and low level is 0V; Input signal and output signal for example are all frequency signal, and its high level is equal to the high level of first operating voltage and second operating voltage in essence respectively.But certainly, the present invention is not limited thereto, and applicable to the conversion between any voltage level, and input and output signal also be not limited to frequency signal, and can be data or other signal.
Please refer to Fig. 5, this is the schematic circuit diagram of first embodiment of the invention.As shown in the figure, in the level converter 100 of present embodiment, except basic a pair of PMOS transistor M1, M2 and pair of NMOS transistors M3, M4 (level shifting circuit 20 that above formation is basic), include one in addition according to the potential difference between node A, B, decide the output-stage circuit of the level of actual output OUT.This output-stage circuit has multiple possible enforcement aspect, realize this output-stage circuit with comparator 30 in the present embodiment, but the present invention is not limited thereto.
Please refer to Fig. 6 and contrast Fig. 5, when the state of input IN changed over high level (1.2V) by low level (0V), the current potential of node A descended fast, the current potential of Node B slowly rises.Because the output OUT of entire circuit is directly exported by Node B, but through the result of comparator 30 after the current potential between node A, B is made comparisons, therefore the current potential of Node B surpasses after the node A by the time, the voltage of output OUT just converts high level (3.3V) to, shown in time point T1.
Yet, when the state of input IN changes over low level by high level, must wait until that the current potential of Node B is lower than after the node A, the voltage of output OUT just converts low level to, shown in time point T2.
So, as can be seen from Figure 6, output signal OUT is identical in the work period of high-low level, that is TH=TL, has therefore just reached purpose of the present invention.
Key of the present invention is that the output of entire circuit is to produce according to the current potential comparative result between node A, B.But as previously mentioned, its execution mode is not limited to use comparator 30.
Please refer to Fig. 7, this is the schematic circuit diagram of second embodiment of the invention.As shown in the figure, in the level converter 200 of present embodiment, change and adopted another level shifting circuit 40, wherein comprise a pair of PMOS transistor M5, M6 and pair of NMOS transistors M7, M8.But in this level shifting circuit 40, its nmos pass transistor M7, M8 are identical with the width of PMOS transistor M5, M6.In this, level shifting circuit 40 can be considered a level shifting circuit that waits voltage level, and is identical with its second operating voltage of exporting because of its first operating voltage of accepting input (grid voltage of transistor M7, M8), is all 3.3V in the present embodiment.
Please refer to Fig. 8 and contrast Fig. 7, when the state of input IN changed over high level by low level, the current potential of node A descended fast, the current potential of Node B slowly rises; Accordingly, nmos pass transistor M7 quick closedown, and the slow conducting of nmos pass transistor M8.Though nmos pass transistor M7 quick closedown, because the slow conducting of nmos pass transistor M8, so the grid voltage of PMOS transistor M5 only is slow decline, so the output OUT of entire circuit does not obviously change state as yet; By the time the current potential of Node B surpasses after the node A, and the output OUT of entire circuit just significantly changes state and converts high level to, shown in time T 1.
Yet, when the state of input IN changes over low level by high level, must wait until that the current potential of Node B is lower than after the node A, the voltage of output OUT just significantly converts low level to, shown in time T 2.
Among Fig. 8, similarly, output signal OUT is identical in the work period of high-low level, that is TH=TL, thereby has reached purpose of the present invention.
Below enumerated several embodiment the present invention is described, the above person only only is familiar with present technique person and is easy to understand content of the present invention for making, and is not to be used for limiting interest field of the present invention; For being familiar with present technique person, when thinking according to notion of the present invention and the variation of various equivalences.As previously mentioned, any according to the potential difference between node A, B for the present invention, decide the mode of actual output OUT level, all the purpose of attainable cost invention also all should belong to scope of the present invention.In addition, the present invention also can be applicable to the level converter of high pressure to low pressure, and may not be confined to be applied in the level converter of low pressure to high pressure.In a word, all various variations or modifications of having done according to notion of the present invention and spirit all should be included in the claim of the present invention.
Claims (26)
1. level converter comprises:
One first level shifting circuit in order to accept the input of first operational voltage level, converts the second just anti-phase operational voltage level to; And
One output-stage circuit, it is exported and produce according to the mutual current potential height of this second just anti-phase operational voltage level.
2. level converter as claimed in claim 1, wherein this second operating voltage is higher than this first operating voltage.
3. level converter as claimed in claim 1 wherein when second operational voltage level of positive is higher than the second anti-phase operational voltage level, is output as high level; When the second anti-phase operational voltage level is higher than second operational voltage level of positive, be output as low level.
4. level converter as claimed in claim 1, wherein this output-stage circuit is a comparator, and two inputs of this comparator receive this second just anti-phase operational voltage level respectively, and its output is then as the output of whole level converter.
5. level converter as claimed in claim 1, wherein this output-stage circuit is second level shifting circuit, and its input receives this second just anti-phase operational voltage level, and its output is as the output of whole level converter.
6. level converter as claimed in claim 5, wherein this second level shifting circuit comprises a pair of PMOS transistor AND gate pair of NMOS transistors, the drain electrode of this pair pmos transistor is electrically connected with the other side's grid mutually, and the source grounding of this pair nmos transistor, drain electrode is electrically connected with the drain electrode of this pair pmos transistor respectively, and grid receives this second just anti-phase operational voltage level respectively.
7. level converter as claimed in claim 6, wherein in second level shifting circuit, one of them PMOS transistor drain, the output that produces whole level converter.
8. level conversion method comprises:
With the input of first operational voltage level, convert the second just anti-phase operational voltage level to; And
According to the correlation between this second just anti-phase operational voltage level, the decision output level.
9. method as claimed in claim 8, wherein this second operating voltage is higher than this first operating voltage.
10. method as claimed in claim 8 wherein when second operational voltage level of positive is higher than the second anti-phase operational voltage level, is output as high level; When the second anti-phase operational voltage level is higher than second operational voltage level of positive, be output as low level.
11. method as claimed in claim 8, wherein the step of this decision output level comprises: this second just anti-phase operational voltage level relatively.
12. method as claimed in claim 8, wherein the step of this decision output level comprises: a level shifting circuit is provided, and its input receives this second just anti-phase operational voltage level, and its output is as the output of whole level converter.
13. method as claimed in claim 12, wherein this level shifting circuit comprises a pair of PMOS transistor AND gate pair of NMOS transistors, the drain electrode of this pair pmos transistor is electrically connected with the other side's grid mutually, and the source grounding of this pair nmos transistor, drain electrode is electrically connected with the drain electrode of this pair pmos transistor respectively, and grid receives this second just anti-phase operational voltage level respectively.
14. method as claimed in claim 13, wherein in second level shifting circuit, one of them PMOS transistor drain, the output that produces whole level converter.
15. a device that is used for the changing voltage level, this device includes:
One first voltage level converting, an input signal that has first operational voltage level in order to reception, convert one first switching signal and one second switching signal with second voltage level to, wherein this first operational voltage level and this second operational voltage level are inequality; And
One output circuit is coupled to this first voltage level converting, in order to according to this first and the current potential of this second switching signal produce an output signal.
16. device as claimed in claim 15, wherein this input signal is a frequency signal, and the high level current potential of this frequency signal is identical in essence with this first operational voltage level.
17. device as claimed in claim 15, wherein this first and this second switching signal be respectively a first frequency signal and a second frequency signal, and this first and the high level current potential of this second frequency signal identical in essence with this second operational voltage level, and this first and this second frequency signal between have 180 ° phase difference.
18. device as claimed in claim 15, wherein when the voltage level of this first switching signal was higher than the voltage level of this second switching signal, then this output signal had the high level current potential; When the voltage level of this first switching signal was lower than the voltage level of this second switching signal, then this output signal had the low level current potential, and wherein this high level current potential of this output signal is identical in essence with this second voltage level.
19. device as claimed in claim 15, wherein this output circuit can be a comparator or one second voltage level converting.
20. device as claimed in claim 15, this voltage level converting wherein includes:
One the first transistor, its source electrode are coupled to this second operating voltage;
One transistor seconds, its source electrode are coupled to this second operating voltage;
One the 3rd transistor, its source electrode are coupled to this first operating voltage, and its drain electrode is coupled to the drain electrode of this first transistor and the grid of this transistor seconds; And
One the 4th transistor, its source electrode are coupled to this second operating voltage, and its drain electrode is coupled to the drain electrode of this transistor seconds and the grid of this first transistor;
Wherein the 3rd is used for received signal with the 4th transistorized grid, and this first is used for output signal with the drain electrode of this transistor seconds.
21. a method that is used for the changing voltage level, this method includes:
Reception has an input signal of first operational voltage level;
Changing this input signal becomes one first switching signal and one second switching signal with second voltage level, and wherein this first operational voltage level and this second operational voltage level are inequality; And
According to this first and the voltage level magnitude relationship of this second switching signal produce an output signal.
22. method as claimed in claim 21, the step that wherein produces this output signal also includes:
Relatively this first and the voltage level size of this second switching signal to produce this output signal.
23. method as claimed in claim 21, wherein this second operational voltage level is than this first operational voltage level height.
24. method as claimed in claim 21, wherein this input signal is a frequency signal, and the high level current potential of this frequency signal is identical in essence with this first operational voltage level.
25. method as claimed in claim 21, wherein this first and this second switching signal be respectively a first frequency signal and a second frequency signal, and this first and the high level current potential of this second frequency signal identical in essence with this second operational voltage level, and this first and this second frequency signal between have 180 ° phase difference.
26. method as claimed in claim 21, wherein when the voltage level of this first switching signal was higher than the voltage level of this second switching signal, then this output signal had the high level current potential; When the voltage level of this first switching signal was lower than the voltage level of this second switching signal, then this output signal had the low level current potential, and wherein this high level current potential of this output signal is identical in essence with this second voltage level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100029983A CN101488742A (en) | 2008-01-15 | 2008-01-15 | Electric level converting apparatus and method |
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| CNA2008100029983A CN101488742A (en) | 2008-01-15 | 2008-01-15 | Electric level converting apparatus and method |
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| CN101488742A true CN101488742A (en) | 2009-07-22 |
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| CNA2008100029983A Pending CN101488742A (en) | 2008-01-15 | 2008-01-15 | Electric level converting apparatus and method |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103489425A (en) * | 2013-10-12 | 2014-01-01 | 合肥京东方光电科技有限公司 | Level switching circuit, array substrate and display device |
| CN103929172A (en) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Level shift circuit |
| CN104505118A (en) * | 2014-12-18 | 2015-04-08 | 西安华芯半导体有限公司 | Electrical level converter for high-speed dynamic random access memory (DRAM) |
| CN107370485A (en) * | 2017-06-30 | 2017-11-21 | 湖南国科微电子股份有限公司 | Negative pressure level shifting circuit |
| CN107404307A (en) * | 2016-05-18 | 2017-11-28 | 英飞凌科技股份有限公司 | Measurement apparatus, level shifter circuit, charge pump stage and charge pump and its method |
| WO2018188017A1 (en) * | 2017-04-13 | 2018-10-18 | 深圳市汇顶科技股份有限公司 | Level conversion circuit and fingerprint recognition device |
| CN109347473A (en) * | 2018-09-04 | 2019-02-15 | 上海东软载波微电子有限公司 | Level shift circuit |
| US10685802B2 (en) | 2016-05-18 | 2020-06-16 | Infineon Technologies Ag | Circuit architecture for a measuring arrangement, a level converter circuit, a charge pump stage and a charge pump, and method for operating same |
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- 2008-01-15 CN CNA2008100029983A patent/CN101488742A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103929172A (en) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Level shift circuit |
| CN103929172B (en) * | 2013-01-10 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | Level shift circuit |
| CN103489425B (en) * | 2013-10-12 | 2015-11-25 | 合肥京东方光电科技有限公司 | Level shifting circuit, array base palte and display device |
| US9583059B2 (en) | 2013-10-12 | 2017-02-28 | Boe Technology Group Co., Ltd. | Level shift circuit, array substrate and display device |
| CN103489425A (en) * | 2013-10-12 | 2014-01-01 | 合肥京东方光电科技有限公司 | Level switching circuit, array substrate and display device |
| CN104505118A (en) * | 2014-12-18 | 2015-04-08 | 西安华芯半导体有限公司 | Electrical level converter for high-speed dynamic random access memory (DRAM) |
| CN107404307B (en) * | 2016-05-18 | 2021-02-09 | 英飞凌科技股份有限公司 | Measuring device, level converter circuit, charge pump stage and charge pump and method thereof |
| CN107404307A (en) * | 2016-05-18 | 2017-11-28 | 英飞凌科技股份有限公司 | Measurement apparatus, level shifter circuit, charge pump stage and charge pump and its method |
| US10685802B2 (en) | 2016-05-18 | 2020-06-16 | Infineon Technologies Ag | Circuit architecture for a measuring arrangement, a level converter circuit, a charge pump stage and a charge pump, and method for operating same |
| WO2018188017A1 (en) * | 2017-04-13 | 2018-10-18 | 深圳市汇顶科技股份有限公司 | Level conversion circuit and fingerprint recognition device |
| US11005476B2 (en) | 2017-04-13 | 2021-05-11 | Shenzhen GOODIX Technology Co., Ltd. | Level shift circuit and fingerprint identification device |
| CN107223310B (en) * | 2017-04-13 | 2021-03-02 | 深圳市汇顶科技股份有限公司 | Level conversion circuit and fingerprint identification device |
| CN107370485A (en) * | 2017-06-30 | 2017-11-21 | 湖南国科微电子股份有限公司 | Negative pressure level shifting circuit |
| CN107370485B (en) * | 2017-06-30 | 2020-11-17 | 湖南国科微电子股份有限公司 | Negative voltage level conversion circuit |
| CN109347473A (en) * | 2018-09-04 | 2019-02-15 | 上海东软载波微电子有限公司 | Level shift circuit |
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Application publication date: 20090722 |