CN105336773B - Fin formula field effect transistor and forming method thereof - Google Patents
Fin formula field effect transistor and forming method thereof Download PDFInfo
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- CN105336773B CN105336773B CN201410261126.4A CN201410261126A CN105336773B CN 105336773 B CN105336773 B CN 105336773B CN 201410261126 A CN201410261126 A CN 201410261126A CN 105336773 B CN105336773 B CN 105336773B
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Abstract
A kind of fin formula field effect transistor of present invention offer and forming method thereof.The forming method of fin formula field effect transistor includes that ion is injected into semiconductor substrate, the first area doped with ion is formed in semiconductor substrate, other regions of semiconductor substrate are second area；First area and second area are etched, to form fin, the etch rate of first area is less than the etch rate of second area, and it includes the ion implanted layer for etching first area and being formed to make fin, and the width of ion implanted layer is more than the width of fin above ion implanted layer；Later, dielectric layer is formed on a semiconductor substrate, and dielectric layer exposes ion implanted layer, and is developed across the grid of fin, and source-drain area is formed in fin.Source and drain ion diffusion when ion implanted layer can effectively inhibit to inject from source and drain ion to fin, so as to reduce the depth of ion in source-drain area, and then the fixed charge amount of the accumulation in fin Yu dielectric layer intersection is reduced in use, improve the electric property of fin formula field effect transistor.
Description
Technical field
The present invention relates to semiconductors to form field, more particularly, to a kind of fin formula field effect transistor and forming method thereof.
Background technology
With the rapid development of integrated circuit (abbreviation IC) manufacturing technology, the process node of traditional integrated circuit gradually subtracts
Small, the size of integrated circuit device constantly reduces, and integrated circuit device preparation process constantly innovation is to improve integrated circuit device
Performance.
In MOS transistor, obtained by forming the metal with different work functions between high-K dielectric layer and metal gates
Ideal threshold voltage is obtained, so as to improve device performance.But with being gradually reduced for characteristic size, traditional plane formula MOS is brilliant
Body pipe cannot be satisfied the demand to device performance, if plane formula MOS transistor dies down to the control ability of channel current, cause
Serious leakage current.For this purpose, multi-gate device has obtained extensive concern as the replacement of conventional device.
Fin formula field effect transistor (Fin FET) is one kind of the multi-gate device.Refering to what is shown in Fig. 1, Fin FET packets
It includes：Semiconductor substrate 1；Fin 3 in semiconductor substrate 1；Oxide layer 2 in semiconductor substrate 1；It is sequentially located at oxidation
2 surface of layer and gate dielectric layer (not shown) and grid 4 across fin 3；The side wall 6 between the fin of 3 both sides of fin；Positioned at 4 liang of grid
The grid curb wall 5 of side；Source/drain 31 in 5 liang of lateral fins 3 of grid 4 and grid curb wall.
The part that the top of the fin 3 of Fin FET and the side wall of both sides are in contact with grid all becomes channel region, i.e., above-mentioned
Structure makes a Fin FET while having the effect of multiple grid, to be conducive to increase driving current, improves device performance.
Incorporated by reference to refering to what is shown in Fig. 2, the preparation process of Fin FET includes：
It first etches and forms multiple fins 3 in semiconductor substrate 1；Form oxide skin(coating) 2 on semiconductor substrate 1 later；Removal
The oxide skin(coating) 2 of segment thickness so that after the oxide skin(coating) 2 is exposed in 3 upper end of fin, above the fin 3 and oxide skin(coating) 2 according to
This forms gate dielectric and semiconductor material layer (not shown), and in the fin 3 and semiconductor material layer both sides shape
At side wall 6 between fin as shown in Figure 1, side wall 6 between the fin 3 and fin is developed across on side wall 6 between the fin 3 and fin
Grid 4 forms grid curb wall 5, later by modes such as ion implantings in the grid 4 and grid on the side wall of the grid 4
Source/drain 31 is formed in the fin 3 that pole side wall 5 exposes.
It is continued to develop however as Fin FET, it is found that the electric property of the Fin FET formed by prior art is unstable
Fixed, to affect the performance of Fin FET, how to improve the performance of Fin FET thus is those skilled in the art's urgent need to resolve
The problem of.
Invention content
Problems solved by the invention is in a kind of fin formula field effect transistor of offer and forming method thereof, optimization fin field effect
Answer the performance of transistor.
To solve the above problems, the present invention provides a kind of forming methods of semiconductor devices, including：
Semiconductor substrate is provided；
Ion is injected into the semiconductor substrate, is formed doped with the first of the ion in the semiconductor substrate
Other regions in region, semiconductor substrate are second area；
First area and the second area for etching the semiconductor substrate, to form fin, the etching speed of the first area
Rate is less than the etch rate of the second area, and it includes the ion implanted layer that the etching first area is formed to make the fin, and
The width of the ion implanted layer is more than the width of fin above the ion implanted layer；
Dielectric layer is formed in the semiconductor substrate that the fin exposes, the dielectric layer exposes the ion implanted layer；
The grid of the fin is developed across on the dielectric layer；
Source-drain area is formed in the fin that the grid exposes.
Optionally, inject ion into the semiconductor substrate, in the semiconductor substrate formed doped with it is described from
Son first area the step of include：
Carbon ion is injected into the semiconductor substrate.
Optionally, include the step of injection ion into the semiconductor substrate：Inject carbon ion dosage be 1.0 ×
1013~1.0 × 1017/cm2, energy is 1~20eV.
Optionally, first area and the second area for etching the semiconductor substrate, to form fin the step of include：
Keep the width of the ion implanted layer bigger by 5%~20% than the width of fin above the ion implanted layer.
Optionally, the thickness of the ion implanted layer is greater than or equal to
Optionally, first area and the second area for etching the semiconductor substrate, the step of to form fin in, the quarter
Erosion is dry etching.
Optionally, the dry etching is using the mixed gas of carbon tetrafluoride, Nitrogen trifluoride and oxygen as etching gas.
Optionally, the step of dry etching includes：Air pressure be 10~200mtorr, radio-frequency power be 100~
1000W, bias power are 0~300W, the flow of the carbon tetrafluoride is 10~200sccm, the flow of Nitrogen trifluoride be 0~
The flow of 200sccm, the oxygen are 1~100sccm.
Optionally, the etching gas further includes one or more in hydrogen bromide, difluoromethane and chlorine.
Optionally, the etching gas includes：Hydrogen bromide, difluoromethane and chlorine, the wherein flow of hydrogen bromide be 10~
The flow of 200sccm, difluoromethane are 10~200sccm, and the flow of chlorine is 10~200sccm.
Optionally, first area and the second area for etching the semiconductor substrate, to form fin the step of include：
Continue the semiconductor substrate that etching is located at below the first area after etching the first area, reveals in the fin
Groove is formed in the semiconductor substrate gone out, and the bottom of the groove is located at the lower section of the ion implanted layer.
Optionally, the semiconductor substrate includes NMOS area and PMOS area；
Ion is injected into the semiconductor substrate, is formed doped with the first of the ion in the semiconductor substrate
The step of region includes：
The ion is injected into the NMOS area, and described first is formed in the NMOS area of the semiconductor substrate
Region.
Optionally, before injecting ion into the semiconductor substrate, the forming method of the fin formula field effect transistor
Further include：
To the NMOS area implanting p-type ion of the semiconductor substrate, p-well is formed；
N-type ion is injected to the PMOS area of the semiconductor substrate, forms N traps；
Ion is injected into the semiconductor substrate, is formed doped with the first of the ion in the semiconductor substrate
Other regions in region, semiconductor substrate include for the step of second area：To injecting ion in the NMOS area, described
The first area is formed in NMOS area；
First area and the second area for etching the semiconductor substrate, to form fin the step of include：Described in etching
PMOS area and NMOS area, PMOS fins are formed in PMOS area, form NMOS fins in NMOS area, the NMOS fins include institute
State ion implanted layer.
Optionally, include the step of forming dielectric layer in the semiconductor substrate that the fin exposes：Using fluid chemistry gas
Phase sedimentation forms dielectric layer in the semiconductor substrate between the fin.
The present invention also provides a kind of fin formula field effect transistors, including：
Semiconductor substrate；
Fin in the semiconductor substrate includes the ion implanted layer doped with ion, the ion in the fin
The width of implanted layer is more than the width of fin above the ion implanted layer；
Dielectric layer in the semiconductor substrate that the fin exposes, the dielectric layer expose the ion implanted layer；
On the dielectric layer, and across the grid of the fin；
Source-drain area in the fin that the grid exposes.
Optionally, the width of the ion implanted layer in the fin it is bigger by 5% than the width of fin above the ion implanted layer~
20%.
Optionally, the top of ion implanted layer semiconductor substrate between adjacent fins.
Optionally, the fin formula field effect transistor is NMOS fin formula field effect transistors.
Optionally, the ion is carbon ion.
Optionally, the thickness of the ion implanted layer is greater than or equal to
Compared with prior art, technical scheme of the present invention has the following advantages：
After semiconductor substrate is provided, ion is injected into the semiconductor substrate, is formed in the semiconductor substrate
Doped with the first area of the ion, other regions of semiconductor substrate are second area；Etch the semiconductor substrate
First area and second area, to form fin, the etch rate of the first area is less than the etch rate of the second area,
Make the fin include the ion implanted layer that the etching first area is formed, and the width of the ion implanted layer be more than it is described from
The width of fin above sub- implanted layer；Later, dielectric layer is formed in the semiconductor substrate that the fin exposes, the dielectric layer exposes
The ion implanted layer, and it is developed across on the dielectric layer grid of the fin, it is formed in the fin that the grid exposes
Source-drain area, to form fin formula field effect transistor.The ion implanted layer can effectively inhibit source and drain ion in fin to spread, so as to
Reduce the depth of ion in source-drain area, and then reduces the fixed charge in fin and the accumulation of dielectric layer boundary place in use
Amount, to improve the electric property of fin formula field effect transistor.
In alternative, after forming N traps and p-well in the semiconductor substrate, then etches the semiconductor substrate and formed
PMOS fins and NMOS fins.In forming method compared to existing fin formula field effect transistor, first etch semiconductor substrates are formed
Fin, later with photoresist covering PMOS area (or NMOS area), into the fin of NMOS area (or PMOS area) implanting p-type from
Sub (N-type ion) after forming p-well (or N traps) technique, can cause PMOS (or NMOS fins) to damage when removing photoresist.Above-mentioned skill
Art scheme is initially formed N traps and p-well, and etch semiconductor substrates form PMOS fins again later and the technical solution of NMOS fins can be effective
PMOS fins and the damage of NMOS fins are reduced, so as to improve performance of semiconductor device.
Description of the drawings
The structural schematic diagram of the existing fin formula field effect transistors of Fig. 1；
The preparation process structural schematic diagram of the existing fin formula field effect transistors of Fig. 2；
Fig. 3 is the electric property figure of existing NMOS fin formula field effect transistors；
Fig. 4 is the electric property figure of existing PMOS fin formula field effect transistors；
Fig. 5 to Figure 11 is the schematic diagram of the forming method for the fin formula field effect transistor that one embodiment of the invention provides；
Figure 12 is existing NMOS fin formula field effect transistors and the NMOS fin field effects that one embodiment of the invention provides
The electric property comparison diagram of transistor；
Figure 13 and 14 is the schematic diagram of the forming method for the fin formula field effect transistor that another embodiment of the present invention provides；
Figure 15~16 are the structural schematic diagrams for the fin formula field effect transistor that one embodiment of the invention provides；
Figure 17~18 are the structural schematic diagrams for the fin formula field effect transistor that another embodiment of the present invention provides.
Specific implementation mode
As described in the background art, the stable electrical properties of the fin formula field effect transistor formed by existing technique
Property it is poor, in order to obtain the poor reason of electrical performance stability, in running order fin formula field effect transistor is carried out
Analysis：After fin formula field effect transistor grid applies voltage, a large amount of fixed charge can be gathered in fin and the intersection of oxide layer
(fixed oxide charge)。
With reference to figure 3 and Fig. 4, respectively illustrate in existing NMOS transistor and PMOS transistor fin and with oxide layer intersection
Electrical performance testing figure.Wherein, the longitudinal axis is threshold voltage, and horizontal axis is fixed charge amount, and it is 6nm's or so that L1 and L3, which are width,
The electric property curve of fin, L2 and the electric property curve that L4 is the fin that width is 9nm or so.Comparison diagram 4 and Fig. 3 it is found that
During use, fin and dielectric layer intersection can gather a large amount of fixed charge in N-type fin formula field effect transistor, and with threshold
Threshold voltage increases, and the amount of charge of accumulation increased dramatically.These, which accumulate in fin and the fixed charge of dielectric layer intersection, to cause
Fin is punctured by electric current, to reduce the electrical performance stability of Fin FET, thereby reduces the performance of Fin FET.
For this purpose, the present invention provides a kind of fin formula field effect transistors and forming method thereof, wherein fin field effect crystal
The forming method of pipe includes：Ion is injected into the semiconductor substrate, is formed doped with described in the semiconductor substrate
Other regions of the first area of ion, semiconductor substrate are second area；Etch the semiconductor substrate first area and
Second area, to form fin, the etch rate of the first area is less than the etch rate of the second area so that the fin
The ion implanted layer formed including etching the first area, and the width of the ion implanted layer is more than the ion implanted layer
The width of top fin；Later, dielectric layer is formed in the semiconductor substrate that the fin exposes, the dielectric layer exposes the ion
Implanted layer, and it is developed across on the dielectric layer grid of the fin, source-drain area is formed in the fin that the grid exposes, with
Form fin formula field effect transistor.The ion implanted layer can effectively inhibit to inject source and drain ion into the fin of metal gates both sides
When source and drain ion diffusion, so as to reduce the depth of ion in source-drain area, and then in use compared to existing fin
Formula field-effect transistor, the fin formula field effect transistor formed using the forming method of fin formula field effect transistor of the present invention can have
Effect reduces in FinFET, the fixed charge amount of fin and the accumulation of oxide layer intersection, so as to improve the electric property of Fin FET.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific implementation mode be described in detail.
Fig. 5 to Figure 11 is the schematic diagram of the forming method for the fin formula field effect transistor that one embodiment of the invention provides.
The forming method of the present embodiment fin formula field effect transistor includes：
Shown in Fig. 5, semiconductor substrate 100 is provided.
Semiconductor substrate 100 in the present embodiment is silicon substrate, and the semiconductor substrate 100 may be used also in other embodiments
To be germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate, common semiconductor substrate can be used as half in the present embodiment
Conductor substrate.
The semiconductor substrate 100 includes NMOS area I and PMOS area II.The NMOS area I is used to form NMOS
Fin formula field effect transistor, the PMOS area II are used to form PMOS fin formula field effect transistors.
Into the NMOS area I, implanting p-type ion to be to form p-well 110, injected into the PMOS area II N-type from
Son forms N traps 120.
The p-type ion includes B plasmas, and the N-type ion includes phosphorus (P), arsenic (As) plasma.To the semiconductor
Implanting p-type ion and N-type ion processes are this field maturation process in substrate, and details are not described herein.
Refering to what is shown in Fig. 6, ion is injected into the semiconductor substrate 100, in the NMOS area of the semiconductor substrate 100
The first area 130 doped with the ion is formed in the I of domain, other regions of the semiconductor substrate 100 are second area.Its
In, it is in the NMOS area I of the semiconductor substrate 100, above and below first area 130 described in through-thickness
The part in two regions.
In the present embodiment, the first area 130 is located in the p-well 110.
In the present embodiment, the specific steps that ion is injected into the semiconductor substrate 100 include：
Photoresist layer 210 is formed in the semiconductor substrate 100, the photoresist layer 210 covers the PMOS area
II, exposed portion NMOS area I are later that mask injects ion into the NMOS area with the photoresist layer 210, with shape
At the first area 130.In the present embodiment, the ion is carbon ion (C), and the parameter of the technique of ion implanting includes：Note
The carbon ion dosage entered is 1.0 × 1013~1.0 × 1017/cm2, energy is 1~20xV。
With reference to shown in figure 7 and Fig. 8, the semiconductor substrate 100 is etched, NMOS is formed in the semiconductor substrate 100
Fin and PMOS fins.Detailed process includes：
It sequentially forms hard mask layer 221, amorphous carbon layer 222 from the bottom to top in the semiconductor substrate 100 and is based on
The anti-reflecting layer (Si-ARC layers) 223 of Si forms photoetching agent pattern 224 on the Si-ARC layers 223 later, and with the light
Photoresist pattern 224 is Si-ARC layers 223, amorphous carbon layer 222 and hard mask layer 221 described in mask etching, forms hard mask
220。
It is semiconductor substrate 100 described in mask etching with the hard mask 220, in the NMOS shown in Fig. 8
Region I forms NMOS fins 310, the formation PMOS fins 320 in PMOS area II, and adjacent fin (including PMOS fins and NMOS fins)
Between, groove (not indicated in figure) is formed in the semiconductor substrate that fin is exposed.
In the present embodiment, when etching the NMOS area I, ion implanting is formed having etched the first area 130
After layer 131, continue to etch the semiconductor substrate 100 so that the ion implanted layer 131 of formation is located at the upper of the channel bottom
There is certain distance, i.e., the described ion implanted layer 131 to be located at described between the ion implanted layer 131 and channel bottom for side
The centre position of NMOS fins 310.
In etching process, in the NMOS area I, doped with the etch rate of the first area 130 of carbon ion
Less than the etch rate undoped with the second area for having carbon ion in semiconductor substrate 100, the i.e. etching of the first area 130
Rate is less than the etch rate of the semiconductor substrate 100 of 130 top of the first area and lower section.It is partly led so that etching is described
In the NMOS fins 310 that the NMOS area I of body substrate 100 is formed, etches the first area 130 and be formed by ion implanting
The width of layer 131 is more than the width of the fin of the top of the ion implanted layer 131 and lower section, i.e., described in the NMOS fins 310
Ion implanted layer 131 protrudes from the side wall of the NMOS fins 310.
In the NMOS fins 310, if the width of the ion implanted layer 131 is excessive, make the size mistake of the fin 310
Greatly, the other structures such as the grid in the NMOS transistor being subsequently formed and the performance of the NMOS fins 310 are influenced；If width mistake
It is small, subsequently into fin inject source and drain ion to form source-drain area when, the ion implanted layer 131 can not effectively prevent source and drain from
Son is spread into the fin of 131 lower section of ion implanted layer and semiconductor substrate, is caused in finally formed fin field effect crystal
During managing follow-up use, a large amount of fixed charge can be gathered in NMOS fins 310 and the dielectric layer junction being subsequently formed, to
Reduce performance of semiconductor device.
In the present embodiment, the width of 310 intermediate ion implanted layer 131 of NMOS fins is than 131 top fin of the ion implanted layer
Width is big by 5%~20%.
In the present embodiment, it is dry etch process to etch the step of semiconductor substrate 100 forms fin, and the dry method is carved
Etching technique specifically includes：With carbon tetrafluoride (CF4), Nitrogen trifluoride (NF3) and oxygen (O2) mixed gas be etching gas, control
The air pressure of etching gas processed is 10~200mtorr, and radio-frequency power is 100~1000W, and bias power is 0~300W.Wherein, institute
The flow for stating carbon tetrafluoride is 10~200sccm, the flow of Nitrogen trifluoride is 0~200sccm, the flow of the oxygen is 1~
100sccm。
Optionally, the etching gas further includes hydrogen bromide (HBr), difluoromethane (CH2F2) and chlorine (Cl2) in one
Kind is a variety of, to improve the etch rate for etching the semiconductor substrate 100.In the present embodiment, the etching gas includes
Hydrogen bromide, difluoromethane and chlorine, wherein the flow of hydrogen bromide is 10~200sccm, the flow of difluoromethane is 10~
The flow of 200sccm, chlorine are 10~200sccm.
In the present embodiment, the material of the hard mask layer 221 is silicon nitride layer, and with Si-ARC layers 223, amorphous
Carbon-coating 222 and hard mask layer 221, which are whole as hard mask 220, can effectively improve the pattern precision in hard mask 220, to carry
The structure precision of the fin formed after semiconductor substrate 100 described in high subsequent etching.But in the other embodiment in addition to the present embodiment
In, photoetching agent pattern can be only formed on the hard mask layer 221, be later mask patterning described with the photoetching agent pattern
Hard mask layer 221, and be semiconductor substrate 100 described in mask etching with the hard mask layer 221 after graphical, it is same to can be achieved
The purpose of the present invention, these simple changes are within the scope of the invention.
Refering to what is shown in Fig. 9, after removing the photoetching agent pattern 224, Si-ARC layers 223 and amorphous carbon layer 222, in institute
Formation dielectric layer 140 in semiconductor substrate 100 is stated, the dielectric layer covers the PMOS fins 320 and NMOS fins 310；Later, it adopts
Certain media layer is removed with planarizations such as chemical mechanical grindings (Chemical Mechanical polishing, CMP),
To exposing the hard mask layer 211.
In the present embodiment, the dielectric layer 140 is silicon oxide layer, and formation process is fluid chemistry vapour deposition process (F-
CVD).Filling capacity of the dielectric layer material between each fin can be effectively improved using fluid chemistry vapour deposition process, after raising
The performance of the continuous semiconductor devices formed.But the material and its formation process of the dielectric layer do not limit the protection model of the present invention
It encloses, dielectric layer material in the prior art and its formation process are suitable for the present invention.
Refering to what is shown in Fig. 10, continuing with the hard mask layer 221 to be mask, the dielectric layer 140 of segment thickness is removed,
Until exposing the ion implanted layer of 131 surface of ion implanted layer or exposed portion thickness rather than full depth
131.Wherein, 131 lower section of the ion implanted layer 131 of 141 covering part thickness of remaining dielectric layer and ion implanted layer
NMOS fins 310 and PMOS fins 320, the NMOS fins 310 and PMOS fins 320 of the top of ion implanted layer 131 protrude from the medium
141 surface of layer.
In the present embodiment, the technique for removing the dielectric layer 140 of segment thickness is dry etch process.Include specifically
Using containing fluoroform (CHF3), Nitrogen trifluoride (NF3) or oxygen (O2) etc. dielectric layer 140 described in the etchant of gases.
But the technique of the etching dielectric layer does not limit protection scope of the present invention, and the technique of etch media layer is applicable in this field
In the present invention.
If the thickness of the ion implanted layer 131 is too small, when injecting source and drain ion subsequently into fin to form source-drain area, source
Leakage ion still gets through the ion implanted layer 131 and enters in the fin of the lower section of ion implanted layer 131, and then is being subsequently formed
During fin formula field effect transistor use, larger amount of fixed charge can be still gathered in the intersection of fin and dielectric layer.
In the present embodiment, the thickness of the ion implanted layer 131 (i.e. the first area 130) is greater than or equal to
Described in Figure 11, the hard mask layer 211 is removed, exposes the NMOS fins 310 and PMOS fins 320 pushes up
End.
In the present embodiment, the technique for removing the hard mask layer 211 is wet-etching technology.Specifically, phosphoric acid can be used
Solution reduces the damage of semiconductor devices other structures as wet etchant, removing the hard mask layer 211 simultaneously.
Later, gate dielectric is formed in the semiconductor substrate 100, institute is developed across on the dielectric layer 141
The grid of NMOS fins 310 (or PMOS fins 320) is stated, and injects source and drain ion in the fin exposed to the grid both sides, with shape
At source-drain area, to form fin formula field effect transistor, above-mentioned grid, using the formation process of source-drain area as the ripe work of this field
Skill, details are not described herein.
In the present embodiment, the etch rate of the first area in the NMOS area I is less than the etching of the second area
Rate, in the NMOS fins being subsequently formed, the width for etching the ion implanted layer that the first area is formed is more than the ion
The width of fin above and below implanted layer；To form dielectric layer in the semiconductor substrate that the fin exposes, and described
It is described during into the fin of grid both sides exposing, injection source and drain ion is to form source-drain area after forming grid on dielectric layer
Ion implanted layer can effectively inhibit source and drain ion to spread, and so as to reduce the depth of ion in source-drain area, and then use process
The middle fixed charge amount reduced in fin and the accumulation of dielectric layer intersection, so as to improve the electrical property of fin formula field effect transistor
Energy.
In conjunction with reference to shown in figure 12, Figure 12 is for the existing fin formula field effect transistor of identical size and using the present embodiment
The electrical performance testing figure comparison diagram of fin formula field effect transistor made from the forming method of the fin formula field effect transistor of offer,
Wherein, L5 is the electric property curve of existing NMOS fin formula field effect transistors, and L6 is fin field effect provided by the embodiment
The electric property curve of the NMOS transistor of fin formula field effect transistor made from the forming method of transistor.
As shown in Figure 12, compared to existing fin formula field effect transistor, during use, in identical threshold voltage item
Under part, friendship of the NMOS transistor in fin and dielectric layer made from the forming method of fin formula field effect transistor provided in this embodiment
Fixed charge amount at boundary significantly reduces.So as to effectively reduce the breakdown probability of fin, fin formula field effect transistor is improved
Performance.
In addition, when etching the NMOS area I to form NMOS fins, ion note is formed having etched the first area
After entering layer, continue to etch the semiconductor substrate so that the ion implanted layer of formation is located at adjacent fins in the semiconductor substrate
Between channel bottom top, between the ion implanted layer and channel bottom have certain distance, later use fluidisation
Vapour deposition process filled media layer material in the groove between adjacent fins.Above-mentioned technical proposal can effectively improve between each fin
Dielectric layer material filling capacity, improve the compactness and the uniformity of the dielectric layer being subsequently formed, such as improve fin ion
The uniformity of the dielectric layer of dielectric layer and other parts at implanted layer lower corners, and then improve the fin field effect being subsequently formed
Answer the performance of transistor.
Moreover, in the forming method of the present embodiment fin formula field effect transistor, the first shape in the semiconductor substrate 100
After N traps and p-well, then etches the semiconductor substrate 100 and form PMOS fins and NMOS fins.Compared to existing fin field effect
In the forming method of transistor, first etch semiconductor substrates form fin, later with photoresist covering PMOS area (or NMOS area
Domain), implanting p-type ion (the N-type ion) into the fin of NMOS area (or PMOS area) is gone after forming p-well (or N traps) technique
PMOS fins (or NMOS fins) can be caused to damage when except photoresist.The present embodiment can effectively reduce PMOS fins and the damage of NMOS fins, with
Improve performance of semiconductor device.
In above-described embodiment, in NMOS fins, the width of the ion implanted layer be more than above the ion implanted layer and
The width of the fin of lower section, but in other embodiment in addition to the implementation, in the NMOS fins, under the ion implanted layer
The fin width of side can be more than or equal to the width of the ion implanted layer.That is, the NMOS area of etching semiconductor device with
In the NMOS fins of formation, the width of ion implanted layer only need to can realize this hair more than the width of fin above the ion implanted layer
Bright purpose.
Such as the structural representation that Figure 13 and Figure 14 is another embodiment of the forming method of fin formula field effect transistor of the present invention
Figure, technique and the forming method for the fin formula field effect transistor that upper one embodiment provides are substantially similar, difference lies in,
After injecting ion formation first area 150 into semiconductor substrate 120, the semiconductor substrate 120 is etched to form NMOS fins
When 340, half-and-half leading keeps the bottom surface of the fin 340 and the bottom surface of the ion implanted layer 151 formed in the first area 150 neat
Flat, i.e., the ion implanted layer 151 occupies the lower half of the NMOS fins 340 namely the ion implanted layer 151 extends to institute
State 340 bottom surface of fin.That is, the width of the lower semisection of the fin 340 is more than the width of 340 upper semisection of the fin；
Later, after forming dielectric layer 143 in semiconductor substrate 120, ion described in 143 exposed portion of the dielectric layer is noted
Enter layer 151；And gate dielectric is formed in the semiconductor substrate 120, and across structures such as the grids of the fin, and to
Source and drain ion is injected in the fin that the grid both sides are exposed, to form source-drain area, to form fin formula field effect transistor.
Correspondingly, the present invention also provides a kind of fin formula field effect transistors.
Figure 15 and Figure 16 is the embodiment using the forming method of fin formula field effect transistor shown in above-mentioned Fig. 5~Figure 11
The structural schematic diagram of fin formula field effect transistor obtained.But fin formula field effect transistor provided by the invention be not limited to by
The formation of the forming method of above-mentioned fin formula field effect transistor.Herein, Figure 16 be Figure 15 along A-A to diagrammatic cross-section.
In conjunction with reference to shown in figure 15 and 16, the concrete structure of fin formula field effect transistor provided in this embodiment includes：
Semiconductor substrate 400,
Fin 420 in the semiconductor substrate 400.Wherein, include ion implanted layer 421 in the fin 420, it is described
Ion implanted layer 421 doped with ion, and 420 part of fin above and below the ion implanted layer 421 undoped with have from
Son.The width of the ion implanted layer 421 is more than the width of the fin 420 of 421 top of the ion implanted layer and lower section.
Dielectric layer 410 in the semiconductor substrate 400 that the fin 420 exposes, the dielectric layer 410 expose institute
State the ion implanted layer 421 of 421 surface of ion implanted layer or exposed portion thickness rather than full depth.
On the dielectric layer 410, across the grid 430 of the fin 420, in the portion that 430 both sides of the grid are exposed
Divide doped with ion in fin 422, is the source-drain electrode of fin formula field effect transistor.
In the present embodiment, the fin formula field effect transistor is NMOS fin formula field effect transistors.It is mixed in the fin 420
It is miscellaneous to have p-type ion, to form p-well.The p-type ion includes boron (B) ion etc..
The ion adulterated in the ion implanting is carbon (C) ion, and the width of the ion implanted layer 421 than it is described from
The width of 421 top fin of sub- implanted layer is big by 5%~20%.
421 thickness of the ion implanted layer is greater than or equal to
In conjunction with reference to shown in figure 12, compared to existing fin formula field effect transistor, fin field provided in this embodiment is imitated
Answer transistor under identical threshold voltage condition, it is obviously less in the fixed charge amount of fin and the intersection of dielectric layer, to
The breakdown probability of fin can be effectively reduced, the performance of fin formula field effect transistor is improved.Its principle is as described above, no longer superfluous herein
It states.
With reference to shown in figure 17 and Figure 18, for using the formation of fin formula field effect transistor shown in above-mentioned Figure 13~Figure 14
The structural schematic diagram of fin formula field effect transistor made from the embodiment of method.But fin field effect crystal provided in this embodiment
The preparation method of pipe is not limited to the embodiment of the forming method of above-mentioned fin formula field effect transistor.
Figure 18 is diagrammatic cross-sections of the Figure 17 along B-B direction.
The present embodiment is similar to the structure of fin formula field effect transistor that above-mentioned Figure 15 and Figure 16 is provided, and difference exists
In the root of the bottom and fin 440 of the ion implanted layer 422 in the fin 440 of fin formula field effect transistor provided in this embodiment
It flushes, i.e., the ion implanted layer 422 occupies the lower semisection of the NMOS fins 440 namely the ion implanted layer 442 extends to
440 root of the fin so that the width of the lower semisection of the fin 440 is more than 440 upper semisection width of the fin.Above-mentioned simple knot
Structure change is within the scope of the invention.
Although the invention has been described by way of example and in terms of the preferred embodiments, but it is not for limiting the present invention, any this field
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this hair
Bright technical solution makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, and according to the present invention
Technical spirit to any simple modifications, equivalents, and modifications made by above example, belong to technical solution of the present invention
Protection domain.
Claims (19)
1. a kind of forming method of fin formula field effect transistor, which is characterized in that including：
Semiconductor substrate is provided；
Ion is injected into the semiconductor substrate, forms the firstth area doped with the ion in the semiconductor substrate
Other regions in domain, semiconductor substrate are second area；
First area and the second area for etching the semiconductor substrate, to form fin, the etch rate of the first area is small
In the etch rate of the second area, it includes the ion implanted layer that the etching first area is formed to make the fin, and described
The width of ion implanted layer is more than the width of fin above the ion implanted layer；
Dielectric layer is formed in the semiconductor substrate that the fin exposes, the dielectric layer exposes the ion implanted layer；
The grid of the fin is developed across on the dielectric layer；
Source-drain area is formed in the fin that the grid exposes.
2. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the semiconductor substrate
Interior injection ion, in the semiconductor substrate formed doped with the ion first area the step of include：
Carbon ion is injected into the semiconductor substrate.
3. the forming method of fin formula field effect transistor as claimed in claim 2, which is characterized in that the semiconductor substrate
The step of interior injection ion includes：The dosage for injecting carbon ion is 1.0 × 1013~1.0 × 1017/cm2, energy is 1~20eV.
4. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that etch the semiconductor lining
The first area at bottom and second area, to form fin the step of include：
Keep the width of the ion implanted layer bigger by 5%~20% than the width of fin above the ion implanted layer.
5. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the ion implanted layer
Thickness is greater than or equal to
6. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that etch the semiconductor lining
The first area at bottom and second area, the step of to form fin in, the etching is dry etching.
7. the forming method of fin formula field effect transistor as claimed in claim 6, which is characterized in that the dry etching is with four
The mixed gas of fluorocarbons, Nitrogen trifluoride and oxygen is etching gas.
8. the forming method of fin formula field effect transistor as claimed in claim 7, which is characterized in that the step of the dry etching
Suddenly include：Air pressure is 10~200mtorr, and radio-frequency power is 100~1000W, and bias power is 0~300W, the carbon tetrafluoride
Flow be 10~200sccm, the flow of Nitrogen trifluoride is 0~200sccm, the flow of the oxygen is 1~100sccm.
9. the forming method of fin formula field effect transistor as claimed in claim 7, which is characterized in that the etching gas also wraps
It includes one or more in hydrogen bromide, difluoromethane and chlorine.
10. the forming method of fin formula field effect transistor as claimed in claim 9, which is characterized in that the etching gas packet
It includes：Hydrogen bromide, difluoromethane and chlorine, the wherein flow of hydrogen bromide are 10~200sccm, the flow of difluoromethane is 10~
The flow of 200sccm, chlorine are 10~200sccm.
11. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that
First area and the second area for etching the semiconductor substrate, to form fin the step of include：
Continue the semiconductor substrate that etching is located at below the first area after etching the first area, exposes in the fin
Groove is formed in semiconductor substrate, and the bottom of the groove is located at the lower section of the ion implanted layer.
12. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that
The semiconductor substrate includes NMOS area and PMOS area；
Ion is injected into the semiconductor substrate, forms the first area doped with the ion in the semiconductor substrate
The step of include：
The ion is injected into the NMOS area, and firstth area is formed in the NMOS area of the semiconductor substrate
Domain.
13. the forming method of fin formula field effect transistor as claimed in claim 12, which is characterized in that the semiconductor
In substrate before injection ion, the forming method of the fin formula field effect transistor further includes：
To the NMOS area implanting p-type ion of the semiconductor substrate, p-well is formed；
N-type ion is injected to the PMOS area of the semiconductor substrate, forms N traps；
Ion is injected into the semiconductor substrate, forms the firstth area doped with the ion in the semiconductor substrate
Other regions in domain, semiconductor substrate include for the step of second area：To injecting ion in the NMOS area, described
The first area is formed in NMOS area；
First area and the second area for etching the semiconductor substrate, to form fin the step of include：Etch the areas PMOS
Domain and NMOS area, PMOS fins are formed in PMOS area, form NMOS fins in NMOS area, the NMOS fins include the ion
Implanted layer.
14. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that expose in the fin
The step of formation dielectric layer, includes in semiconductor substrate：Using semiconductor lining of the fluid chemistry vapour deposition process between the fin
Dielectric layer is formed on bottom.
15. a kind of fin formula field effect transistor, which is characterized in that including：
Semiconductor substrate；
Fin in the semiconductor substrate includes the ion implanted layer doped with ion, the ion implanting in the fin
The width of layer is more than the width of fin above the ion implanted layer, and the ion is carbon ion；
Dielectric layer in the semiconductor substrate that the fin exposes, the dielectric layer expose the ion implanted layer；
On the dielectric layer, and across the grid of the fin；
Source-drain area in the fin that the grid exposes.
16. fin formula field effect transistor as claimed in claim 15, which is characterized in that the width of the ion implanted layer in the fin
It spends bigger by 5%~20% than the width of fin above the ion implanted layer.
17. fin formula field effect transistor as claimed in claim 15, which is characterized in that the ion implanted layer is located at adjacent fins
Between semiconductor substrate top.
18. fin formula field effect transistor as claimed in claim 15, which is characterized in that the fin formula field effect transistor is
NMOS fin formula field effect transistors.
19. fin formula field effect transistor as claimed in claim 15, which is characterized in that the thickness of the ion implanted layer is more than
Or it is equal to
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