CN105321945A - 具有减小的栅极电荷的沟槽式mosfet - Google Patents

具有减小的栅极电荷的沟槽式mosfet Download PDF

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CN105321945A
CN105321945A CN201510282443.9A CN201510282443A CN105321945A CN 105321945 A CN105321945 A CN 105321945A CN 201510282443 A CN201510282443 A CN 201510282443A CN 105321945 A CN105321945 A CN 105321945A
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unit
groove
mosfet
equipment
grid
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CN105321945B (zh
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T·E·格雷布斯
T·拉赫曼
C·B·考肯
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Texas Instruments Inc
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Abstract

本发明涉及具有减小的栅极电荷的沟槽式MOSFET。沟槽式MOSFET设备(100)包括第一掺杂类型的半导体层(180)。MOS晶体管单元(110、120)处于半导体层内的第二掺杂类型的主体区(160)内。晶体管单元包括第一单元类型(110)，其包括提供第一栅电极(170)的第一沟槽，且第一源极区(150)形成于主体区内。第一栅电极与第一源极区电隔离。第二单元类型(120)具有提供第二栅电极(175)的第三沟槽，且第二源极区(150a)处于主体区内。导电构件(195)直接将第二栅电极、第一源极区和第二源极区连接在一起。

Description

具有减小的栅极电荷的沟槽式MOSFET
技术领域
本公开的实施例涉及沟槽式金属氧化物场效应晶体管(MOSFET)。
背景技术
自从出现了集成电路(IC)设备，缩小特征尺寸已经成为半导体设备中的趋势。总体来说，更小的特征尺寸改善设备性能。证明这种改善的示例反映在存储器设备容量的增加和微处理器的计算能力的增加。对于更高的包装密度的追求也导致三维(3D)处理，其将过去处于设备上表面的组件向内放置在设备的主体中。这种处理的示例是硅通孔(TSV)和沟槽式金属氧化物半导体场效应晶体管(MOSFET)
一种沟槽式MOSFET设计(在本文中被称为“平面栅极沟槽式MOSFET”)具有平面栅极结构、栅极叠层(gatestack)和沟槽之间的半导体表面内的源极和设备下表面上的漏极，其中所述平面栅极结构具有作为栅极叠层的两侧上的场板(有时称为“RESURF”沟槽)的多晶硅填充沟槽。为了此专利申请，术语“RESURF”参考减小相邻半导体区域内的电场的区域/材料进行理解。例如，RESURF区域可能是具有与相邻半导体区域相反的导电类型的半导体区域。RESURF结构在Appels等人的“厚层高压设备(ThinLayerHighVoltageDevices)”(PhilipsJ,Res.351-13,1980)中描述。
与平面栅极沟槽式MOSFET相比，沟槽式栅极MOSFET(有时简称为沟槽式MOSFET)包括沟槽式栅极结构，其是凹陷的且相对于半导体表面垂直取向。沟槽式栅极MOSFET的显著特征是，其缺少结型场效晶体管(JFET)效果。
在功率沟槽式MOSFET情况下，不管它是平面栅极沟槽式MOSFET还是沟槽式栅极MOSFET(统称为“沟槽式MOSFET”)，在设备区域上布置物理和电气并联放置的多个晶体管单元是很常见的。沟槽式MOSFET的每一个单元具有三个单独的电端子，即通常被短路到主体的源极、漏极和栅极。在开关应用中，沟槽式MOSFET处于接通状态或断开状态，在接通状态，电流在源极端子和漏极端子之间垂直地通过，在断开状态，在源级端子和漏极端子之间几乎无电流通过。用于包括沟槽式MOSFET的MOSFET的接通和断开的操作能够通过栅电极和主体、源极以及漏极之间的等效电容器的组合的充电和放电来模拟。用来充电和放电这些电容器的时间决定了MOSFET的开关速度。
发明内容
此概要用来以简化的形式引入公开概念的简要介绍，这些概念在下面包括附图的具体实施方式中进一步描述。此概要不旨在限制所要求的主题的范围。
公开的实施例认识到，用于沟槽式金属氧化物半导体场效应晶体管(MOSFET)的单元尺寸(cellpitch)的减小能够实现更高的单元密度和减小的导通电阻(Rdson或Ron)，因此，这导致在设备运行期间功率损耗的减小。如本文所用，术语“沟槽式MOSFET”包括沟槽式栅极MOSFET和具有在栅极叠层两侧上的有源区域沟槽或RESURF沟槽的平面栅极MOSFET(下文称为“平面栅极沟槽式MOSFET”)。此外，发明人发现，伴随着提供的Rdson的减小，由于MOSFET固有的工序公差，随着栅极和沟道区域之间的界面区域以及栅极和源极之间以及栅极和漏极之间的重叠区域的量逐渐增加，沟槽式MOSFET的电容(尤其是沟槽式栅极MOSFET的电容)增加沟道。在整个沟槽式MOSFET性能中，这种电容上的增加能够极大地抵消单元尺寸的减小得到的Rdson的减小的优势。
在这种认识的情况下，本文描述的沟槽式MOSFET包括多个单元，所述多个单元具有包括第一晶体管单元类型(第一晶体管单元)的单元以及还具有非标准第二晶体管单元类型(第二晶体管单元)的单元，所述第一晶体管单元类型起到包括常规分离的源极、漏极和栅极的常规有源晶体管单元的作用，在第二晶体管单元类型中，栅极和源极有意短接(short)在一起，连同漏极起到二极管接法晶体管的作用，当各自单元结合时，二极管接法晶体管提供增强型沟槽式MOSFET设备性能。提供的性能改善对于平面栅极沟槽式MOSFET和沟槽式栅极MOSFET是显著的，但已经发现，因为与平面栅极沟槽式MOSFET相比沟槽式栅极MOSFET具有较高栅极电荷(Qg)时，提供的性能改善对于沟槽式栅极MOSFET更显著。在给定MOSFET设计中一起利用的第一晶体管单元与第二晶体管单元(其中栅极和源极被短路)的比通常取决于具体电路应用和目标，记住当栅极被短接到源极时，对整个MOSFET设备有少量Rdson损失。
一个公开的方面涉及具有第一晶体管单元和第二晶体管单元的沟槽式MOSFET，其通过平衡设备Rdson和电容实现优越的性能。总体来说，沟槽式MOSFET设备包括源极上的多个源极接触孔和栅电极上的多个栅极接触孔，其中，对于二极管接法晶体管单元(第二晶体管单元)，栅极接触孔和源极接触孔通过连续的导电构件(诸如，掺杂多晶硅线路或金属线路)短接。剩余的与常规有源晶体管单元(第一晶体管单元)关联的栅极接触孔通过第二个连续的导电构件(诸如，掺杂多晶硅线路或金属线路)连接，并且它们的源极接触孔通过第三连续的导电构件连接。第二和第三导电构件彼此不连接。
采用这种布局，被短路到二极管接法晶体管的源极的二极管接法晶体管单元的栅极对沟槽式MOSFET的设备电容没有贡献。因此，包括这种公开的单元结构的沟槽式MOSFET设备提供电容的减小，这导致更快的开关速度。
附图说明
现参考附图，其不一定按比例绘制，其中：
图1根据一个示例实施例描述示例沟槽式栅极MOSFET的截面图，其包括多个常规晶体管单元和二极管接法晶体管单元。
图2根据一个示例实施例描述示例平面栅极沟槽式MOSFET，其包括多个常规有源晶体管单元和二极管接法晶体管单元。
图3示出源自集成电路通用模拟程序(SPICE)模型的数据表，其用于模拟通过增加公开的二极管接法晶体管单元的不同百分比到用于Ron4.5V、8.0V和10.0V的沟槽式栅极MOSFET设备得到的Rdson(示为Ron)、各种电容(C)和电荷(Q)效应。
具体实施方式
参考附图描述示例实施例，其中，相同的标记用于指定类似或等价的元件。示出的行为或事件顺序不应该当做限制性的，因为一些行为或事件可以以不同顺序发生和/或与其他行为或事件同时发生。此外，根据本公开，一些示出的行为或事件可能不是实施方法所需要的。
而且，在没有进一步限定的情况下，本文中在电学上下文中使用的术语“耦合到”或“与……结合”(和类似的术语如“连接到”)旨在描述间接或直接电气连接。因此，如果第一设备“耦合”到第二设备，则该连接能够通过直接电气连接，其中在通路中仅存在寄生现象，或通过经由包括其他设备和连接的中间项(interveningitem)间接电气连接。对于间接耦合，中间项通常不改变信号的信息，但可以调节其电流电平、电压电平和/或功率电平。
图1描述示例沟槽式栅极MOSFET设备100(沟槽式栅极MOSFET100)的截面图，沟槽式栅极MOSFET设备100被示出为包括若干MOSFET单元的n-沟道设备(NMOS)，所述MOSFET单元包括常规第一晶体管单元和提供二极管接法晶体管单元的第二晶体管单元，这体现公开的实施例。所示的5个单元包括单元110和单元120，其中单元100(其中示出四个这种单元)包括常规有源晶体管单元类型(常规有源晶体管单元110)，单元120代表二极管接法晶体管单元120(二极管接法晶体管单元120)。虽然，本文通常描述的是NMOS设备，公开的MOSFET设备也可以是PMOS。此外，在实际的设备中，可能有数百或数千的电气并联的单元，其通常重复二极管接法晶体管单元120的图案，诸如每第N个单元一个二极管接法晶体管单元120。
沟槽式栅极MOSFET100形成在衬底196(被示出为n+衬底)上，所述衬底196为具有在其上的n-外延半导体层180的设备提供漏极，所述n-外延半导体层180提供n-漏极漂移区。n+衬底196/半导体层180能够包括硅；替代地，n+衬底196/外延半导体层180可以包括其他半导体材料，如锗、碳化硅、氮化镓、砷化镓等。p-掺杂主体区160形成在半导体层180内，其中，n+掺杂源极区150形成在主体区160内的半导体层180的表面180a处。
导体填充电介质内衬(lined)栅极沟槽170/140和175/140提供用于各自的单元110、120的栅极结构。栅极沟槽壁内衬有用作栅极电介质的电介质膜140(或内衬(liner))。在此实施例中，电介质膜材料能够是二氧化硅。替代地，电介质膜材料可以包括其他电介质材料，如氮化硅或其他电介质。电介质内衬沟槽使用多晶硅或其他导电材料(如钨)填充以形成二极管接法晶体管单元120的栅电极(示为175)和常规有源晶体管单元110的栅电极170。
栅极沟槽能够从外延半导体层180的表面180a刻蚀。在此实施例中，所示的五个栅极沟槽能够使用图案化步骤同时处理以及随后同时使用刻蚀步骤处理。此实施例中的沟槽式栅极MOSFET100能够通过常规沟槽式MOSFET的工艺流程来形成，所述工艺流程诸如包括离子注入或杂质扩散以形成主体区160和源极区150。
半导体层180的表面180a被示出覆盖有电介质膜190。在此实施例中，电介质膜190能够包括二氧化硅或氮氧化硅。替代地，电介质膜190可以包括在半导体设备制造领域里已知的其他电介质材料。
如图1所示，常规有源晶体管单元110和二极管接法晶体管单元120都包括源极/主体接触孔112，其形成为通过栅极沟槽之间的半导体层180的上表面180a，所述栅极沟槽通过源极区150和主体区160。虽然在图1中示出的源极/主体接触孔112延伸到半导体层180内，但是公开的实施例还包括具有平面源极/主体接触孔的选项。源极/主体接触孔112的深度不影响短接每第N个栅极到源极以提供二极管接法晶体管单元120的公开的概念。然而，源极/主体接触孔112的深度能够改变设备性能，因为如果太浅，从源极150a到主体区160的期望的短路可能不被提供，并且如果太深，那么设备的击穿电压(BV)可能被减小且其阈值电压(Vth)也可能改变。
一旦使用电导体(被示为源极金属层195)填充，接触孔将源极区150短接到每个单元类型110和120的主体区160，并且仅针对二极管接法晶体管单元120，将栅极短接到源极。源极金属层195能够是更一般的任何导电材料(如钨或掺杂多晶硅)，其在操作中通常被接地。
所示的二极管接法晶体管单元120包括被刻蚀到其栅电极175的栅极接触孔122。栅极接触孔122的深度可以与源极/主体接触孔112的深度相同，或可以与其不同。这是因为，虽然半导体层180的台面(mesa)区在此实施例中通常是单晶材料(如硅)，但是栅电极175通常包括多晶硅或其他导电材料。除非单晶(如硅)和在沟槽中的导电栅电极170和175材料(如多晶)相对于使用的刻蚀化学成分具有相同的刻蚀率，否则栅极接触孔122的尺寸可能与台面区内的接触源极/主体孔112的尺寸不同。
图1中所示的沟槽式栅极MOSFET100的n+衬底196的背面196a覆盖有分离的金属膜197。这种金属膜197使低电阻欧姆接触到提供漏极区域的n+衬底196，其在操作中被连接到Vds。替代地，金属膜197可以省略且n+衬底196的背面196a反而可以被安装到引线框的垫板。常规有源晶体管单元110的栅电极170由连接到设备封装的栅电极端子的另一个金属或掺杂多晶元件(未示出)分别固定在一起。
当沟槽式栅极MOSFET100是增强型设备时，假定设备在栅极和源极之间适当偏置，反型沟道形成在源极区150和漏极漂移区180'之间的台面区内，邻近内衬沟槽壁的电介质膜140。当建立源极端子和漏极端子之间的合适的电位差时，电流垂直地流过沟道。如果主体区掺有更大量的n-型掺杂物(PMOS)，电流由孔被携带穿过沟道；如果主体区掺有更大量的如图1所示的p-型掺杂物(NMOS)，电流由电子携带穿过沟道。
在外部电压施加到设备端子之后，MOSFET设备需要有限的时间量达到这种操作条件。在简化的模式下，沟槽式栅极MOSFET100可能被看作电容组件的组合，在其中，有栅极到主体电容器、栅极到源极电容器和栅极到漏极电容器。
当沟槽式栅极MOSFET100用作电路中电源开关时，充电和放电每个电容组件所需要的时间量决定设备的开关速度。因为每单位面积上的单元数量由于各个沟槽式MOSFET单元的缩小特征尺寸而增加，并由此带来增加的单元尺寸，所以设备的总电容按比例增加，其中总电容大致是各个单元电容的算术和。结果，具有较大数目沟槽式栅极MOSFET单元的沟槽式栅极MOSFET设备开关更慢。
沟槽式栅极MOSFET100也具有电阻组件，在其中，存在与金属(或其他导体)引线有关的电阻，引线宽度越细，每单位长度上的电阻越高。还存在与触点相关的电阻，如与源极/主体接触孔112相关。并且存在与n+衬底196和n+衬底196上的漏极漂移区180'有关的电阻。沟槽式栅极MOSFET100的总电阻决定当设备传导电流时的功率损耗。当开关在“接通”状态时，设备电阻Rdson越高，功率损耗越多。
作为功率开关设备的沟槽式MOSFET的性能有时由Rdson和需要充分偏置设备端子的总电荷(Qg)的乘积(称为设备的优值系数(FOM))指定，其中较低的FOM反映较好的设备性能。发明人发现，当沟槽式MOSFET的电容随着每单位面积上的沟槽式MOSFET单元的数量线性增长时，总Rdson以较慢速率减小。具备了这点认识，发明人配置沟槽式MOSFET设备结构，其具有迄今未实现的FOM。
如图1所示，二极管接法晶体管单元120具有直接连接到源极金属层195和其源极区150的栅电极175，其中源极金属层195也将源极区150短接到主体区160，如常规所做的。对于二极管接法晶体管单元120，这种配置有效地迫使栅极175、源极区150和主体区160都处于相同的电势，以致二极管接法晶体管单元120在操作期间不再贡献电容到沟槽式栅极MOSFET100。因此，认识到对于设备，包括选定部分的单元(是二极管接法晶体管单元120)减小了总的沟槽式MOSFET设备电容。
例如，当沟槽式栅极MOSFET100内的每隔一个单元被配置为二极管接法晶体管单元120时，总的沟槽式MOSFET电容将大约减小50％。数学上地，如果每第N个栅极内的栅电极被短接到源极，以提供二极管接法晶体管单元120，那么沟槽式栅极MOSFET设备的电容将减小1/N。
常规有源晶体管单元110与二极管接法晶体管单元120的比通常是从3:1到10:1。对于下述平面栅极沟槽式MOSFET，常规有源晶体管单元与二极管接法晶体管单元的比通常更大，如10:1到100:1。二极管接法晶体管单元的％通常取决于具体电路应用和设计目标，记住当将栅电极短接到源极时，存在少量Rdson增加。
图2描述示例平面栅极沟槽式MOSFET设备200(平面栅极沟槽式MOSFET200)的简化截面图，其体现一些公开的方面。平面栅极沟槽式MOSFET200包括由电介质层241内衬的具有多晶填充物240的电介质内衬沟槽(240/241)，以便为常规有源晶体管单元210和二极管接法晶体管单元220提供在栅极叠层两侧上的场板(有时被称为“RESURF”沟槽)。所示的常规有源晶体管单元210具有包括栅极电介质271上的栅电极270的栅极叠层，并且所示的二极管接法晶体管单元220具有示为栅极电介质271上的栅电极275的栅极叠层。
常规有源晶体管单元210的n+掺杂源极区250和二极管接法晶体管单元220的源极区250a处于在栅极叠层和沟槽240/241之间的半导体层180上的上表面180a上，并且衬底196被示为n+衬底，其为在其上具有半导体层180的设备提供漏极，所述半导体层180提供漏极漂移区180'。虽然示出单元210、220中的每个的单个栅极，各个单元也可以具有双重栅极。此实施例中的平面栅极沟槽式MOSFET200能够通过用于常规MOSFET的工艺流程形成，所述工艺流程诸如包括离子注入或扩散以形成p-掺杂主体区260和源极区250和250a。
表面180a包括在其上的电介质层190。在此实施例中，电介质膜材料能够是二氧化硅。替代地，电介质膜190可以包括其他电介质材料，诸如氮化硅或其他电介质。和沟槽式栅极MOSFET100一样，接触孔212通过电介质层190形成在平面栅极沟槽式MOSFET200内，该电介质层190使源极金属层195能够将源极区250和250a短接到主体区260。
图2还描述，通过电介质层190的接触孔222，其到达二极管接法晶体管单元220的栅电极275的顶部。接触孔212和222使用导电材料(诸如钨或掺杂多晶硅)填充，并且导电柱共同固定到源极金属层195。
常规有源晶体管单元210的栅电极270通过通常连接到设备封装的栅极端子的另一个金属或多晶硅元件分别固定在一起。当平面栅极沟槽式MOSFET200是增强型设备时，假定设备被适当偏置，反型沟道形成在栅极270下的主体区260内。当建立源极和漏极之间的电场梯度时，电流流过沟道。如果主体区掺有更大量的n-型掺杂物(PMOS)，电流由孔携带穿过沟道；如果掺有更大量的p-型掺杂物(NMOS)，电流由电子携带穿过沟道。
在外部电压施加到设备端子之后，MOSFET需要有限的时间量达到这种操作条件。在简化的模式下，平面栅极沟槽式MOSFET200可以被看作电容器组件的组合，在其中，存在栅极到主体电容器、栅极到源极电容器和栅极到漏极电容器。
与图1所示沟槽式栅极MOSFET100相似，当平面栅极沟槽式MOSFET200用作电路中的开关时，充电每个电容组件所需要的时间量决定MOSFET的开关速度。因为每单位设备面积上的单元数量由于各个平面栅极沟槽式MOSFET单元的缩小特征尺寸而增加，所以设备的总电容成比例增加，总电容大致是各个单元电容的算术和。结果，具有较大数目元件的平面栅极沟槽式MOSFET设备开关较慢。
与沟槽式栅极MOSFET相似，平面栅极沟槽式MOSFET设备也具有电阻组件，在其中，存在与导线有关的电阻，且导线宽度越细，每单位长度的电阻越高。还存在与触点相关的电阻。且存在与衬底196和漏极漂移区180'有关的电阻。平面栅极沟槽式MOSFET200的总电阻决定当设备传导电流时的功率损耗。当开关在“接通”状态时，设备电阻Rdson越高，功率损耗越多。
作为功率开关设备的平面栅极沟槽式MOSFET的性能有时由Rdson和需要充分偏置设备端子的栅极电荷Qg(即总电荷)的乘积(通常表示为Rdson*Qg或Qgd)指定，以得到设备的FOM。偶尔，Rsp用于设备的FOM，但设备区域的Qg随后会需要归一化。综上，较低的FOM反映较好的设备性能。
发明人发现，当平面栅极沟槽式MOSFET的电容随着每单位设备面积上的MOSFET单元的数量线性增长时，总Rdson以较慢速率减小。具备了这点认识，发明人配置了设备结构并改善了迄今未实现的FOM。
如图2所示，与二极管接法晶体管单元220有关的平面栅极沟槽式MOSFET单元作为晶体管是无效的，且因此当其栅电极275由源极金属层195电连接到其源极250a和主体区260时，用作来自开关设备的二极管接法晶体管单元。这种配置有效地迫使栅电极275、源极区250和主体区260处于相同的电势，因此其不再贡献电容到设备。因此，包括是二极管接法晶体管单元220的一些单元，减小了总的MOSFET设备电容。
当设备中的每隔一个单元与二极管接法晶体管单元220一样作为晶体管无效时，总的MOSFET电容将减小50％。数学上讲，如果每第N个栅电极被短接到源极，以提供二极管接法晶体管单元，则平面栅极沟槽式MOSFET设备200的电容将减小1/N。
公开的实施例允许维持积极的(aggressive)单元尺寸以满足Rdson目标，并且不需要额外的处理步骤，仅需修改单元布局。此外，公开的实施例不需要使用TBO(厚底氧化物)减小Cgd，因为其他实施例已经用于满足Ron目标。
示例
公开实施例由下列具体示例进一步说明，其不应当理解为以任何方式限制本公开的范围或内容。
图3示出源自SPICE模型的数据表，其用于模拟增加公开的二极管接法晶体管单元的不同百分比到Ron4.5V、8.0V和10.0V的沟槽式栅极MOSFET的Rdson(至始至终示为Ron，且以下称为Ron)、各种电容和电荷(Q)的效应。从模拟参数计算CISS、CRSS和COSSVDSmax/2Qgth、Qgd、Qgs4.5V、8.0V10.0VFOM(Qgd*Ron)。常规晶体管单元在图3中表示为“有源单元”。输入电容被示为Ciss，反向传输电容被示为Crss，输出电容被示为Coss。关于充电，充电栅极到阈值电压所需要的栅极到源极的电荷被示为Qgth，到米勒台阶电压(Millerplateauvoltage,VGP)的栅极源极电荷被示为Qgs，以及栅极漏极电荷被示为从VGP到米勒台阶的末端的Qgd。
当有源单元百分比(％)减小时，Ron看作是增加；然而，Ron减小的速率不是线性的。因为Ron由漏极漂移区、衬底和FET沟道电阻组成；衬底保持与有源单元百分比相同的变化；而总FET沟道电阻随着有源单元百分比的减小而增加。CRSS看作是随着有源单元百分比的减小而线性减小。CISS＝Cgs+CRSS；Cgs和CRSS两者都随着有源单元百分比的减小而线性减小；因此，CISS跟随类似的趋势COSS＝Cds+CRSS；当源极和栅极被连接到二极管接法单元内时，那些单元的CRSS被加到Cds。因此，CRSS的减小被加到Cds，这导致恒定的COSS。Qgth、Qgd、Qgs4.5V、8.0V和10.0V全都看作随着有源单元百分比而线性变化。FOM(是Qgs和Ron的乘积)被看作由于栅极电荷以比Ron增加的速率快的速率减小而随着有源单元百分比的减小而减小。
本公开涉及的领域中的技术人员将认识到，许多其他实施例和实施例的变体可能在所要求保护的发明范围内，且在不脱离本公开范围的情况下，可以对描述的实施例进行进一步增加、删减、替换和修改。

Claims (15)

1.一种沟槽式金属氧化物半导体场效应晶体管设备，即沟槽式MOSFET设备，其包括：
衬底，其包括第一掺杂类型的半导体层，多个MOS晶体管单元形成在所述半导体层中，包括在所述半导体层内的第二掺杂类型的主体区，所述多个MOS晶体管单元还包括：
第一晶体管单元类型，即第一晶体管单元，其包括至少一个第一导体填充电介质内衬沟槽即第一沟槽以及形成在所述主体区内的所述第一掺杂类型的第一源极区，所述第一沟槽提供第一栅电极或所述第一栅电极处于所述第一沟槽和第二导体填充电介质内衬沟槽即第二沟槽之间的所述半导体层的半导体表面上，所述第一栅电极与所述第一源极区电隔离，以及
第二晶体管单元类型，即第二晶体管单元，其邻近所述第一晶体管单元，具有第三导体填充电介质内衬沟槽即第三沟槽以及形成在所述主体区内的所述第一掺杂类型的第二源极区，所述第三沟槽提供第二栅电极，或所述第二栅电极处于所述第三沟槽和第四导体填充电介质内衬沟槽即第四沟槽之间的所述半导体表面上，以及
导电构件，其直接将所述第二栅电极、所述第一源极区和所述第二源极区连接在一起。
2.根据权利要求1所述的沟槽式MOSFET设备，其中，所述衬底提供漏极，并且所述半导体层包括提供所述主体区下面的漏极漂移区的外延层。
3.根据权利要求1所述的沟槽式MOSFET设备，其中，所述第一掺杂类型包括n-型，并且所述MOSFET设备是n-沟道MOS设备即NMOS设备。
4.根据权利要求1所述的沟槽式MOSFET设备，其中，所述第一掺杂类型包括p-型，并且所述MOSFET设备是p-沟道MOS设备即PMOS设备。
5.根据权利要求1所述的沟槽式MOSFET设备，其中，所述MOSFET设备包括平面栅极沟槽式MOSFET设备，并且所述第一晶体管单元包括在所述第一沟槽和所述第二沟槽之间的所述半导体表面上的所述第一栅电极，所述第二晶体管单元包括在所述第三沟槽和所述第四沟槽之间的所述半导体表面上的所述第二栅电极，并且其中所述第一栅电极和所述第二栅电极两者都包括多晶硅。
6.根据权利要求5所述的沟槽式MOSFET设备，其中，所述第一晶体管单元包括多个第一晶体管单元，所述第二晶体管单元包括多个第二晶体管单元，并且其中，所述多个第一晶体管单元与所述多个第二晶体管单元的比是从10:1到100:1。
7.根据权利要求1所述的沟槽式MOSFET设备，其中，所述MOSFET设备包括沟槽式栅极MOSFET设备，其中所述第一沟槽提供所述第一栅电极，并且所述第三沟槽提供所述第二栅电极，并且其中，所述第一栅电极和所述第二栅电极两者都包括多晶硅。
8.根据权利要求7所述的沟槽式MOSFET设备，其中，所述第一晶体管单元包括多个第一晶体管单元，所述第二晶体管单元包括多个第二晶体管单元，并且其中，所述多个第一晶体管单元与所述多个第二晶体管单元的比是从3:1到10:1。
9.根据权利要求1所述的沟槽式MOSFET设备，其中，所述导电构件包括金属。
10.一种沟槽式栅极金属氧化物半导体场效应晶体管设备，即沟槽式栅极MOSFET设备，其包括：
衬底，其包括第一掺杂类型的半导体层，多个MOS晶体管单元形成在所述半导体层中，包括在所述半导体层的上部分中的第二掺杂类型的主体区，所述多个MOS晶体管单元还包括：
第一晶体管单元类型，即第一晶体管单元，其包括至少一个第一导体填充电介质内衬沟槽即第一沟槽以及形成在所述主体区内的所述第一掺杂类型的第一源极区，所述第一沟槽提供第一栅电极，所述第一栅电极与所述第一源极区电隔离；
第二晶体管单元类型，即第二晶体管单元，其邻近所述第一晶体管单元，具有第二导体填充电介质内衬沟槽即第二沟槽以及形成在所述主体区内的所述第一掺杂类型的第二源极区，所述第二沟槽提供第二栅电极，以及
导电构件，其直接将所述第二栅电极、所述第一源极区和所述第二源极区连接在一起。
11.根据权利要求10所述的沟槽式栅极MOSFET设备，其中，所述衬底提供漏极，并且所述半导体层包括提供所述主体区下面的漏极漂移区的外延层。
12.根据权利要求10所述的沟槽式栅极MOSFET设备，其中，所述第一掺杂类型包括n-型，并且所述MOSFET设备是n-沟道MOS设备即NMOS设备。
13.根据权利要求10所述的沟槽式栅极MOSFET设备，其中，所述第一掺杂类型包括p-型，并且所述MOSFET设备是p-沟道MOS设备即PMOS设备。
14.根据权利要求10所述的沟槽式栅极MOSFET设备，其中，所述第一晶体管单元包括多个第一晶体管单元，所述第二晶体管单元包括多个第二晶体管单元，并且其中，所述多个第一晶体管单元与所述多个第二晶体管单元的比是从4:1到10:1。
15.根据权利要求10所述的沟槽式栅极MOSFET设备，其中，所述导电构件包括金属。
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