CN105321869A - 填沟介电层及其制作方法与应用 - Google Patents
填沟介电层及其制作方法与应用 Download PDFInfo
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Abstract
本发明公开一种填沟介电层及其制作方法与应用,其中填沟介电层的制备方法包含下述步骤:首先在基材上沉积含硅介电层。然后,依序对含硅介电层进行烘烤制作工艺、原位湿式处理以及热退火制作工艺,用于在基材上形成氮含量实质小于1×1022个原子/立方厘米(atoms/cm3)的填沟介电层。
Description
技术领域
本发明涉及一种适用于半导体元件中的介电材质层及其制作方法与应用,且特别是涉及一种填沟介电层(gap-fillingdielectriclayer)及其制作方法与应用。
背景技术
随着半导体集成电路的微小化与复杂化,单一芯片上的半导体元件的密度越来越大,相对地元件之间的间距(pitch)也越来越小,这使得用来形成元件隔离结构,例如浅沟隔离(ShallowTrenchIsolation,STI)结构,的开口(gap)或沟槽(trench)随之缩小,容易影响后续介电层的填沟(gapfilling)品质。
传统用来制作填沟介电层的沉积制作工艺,可能因沟槽开口缩小而导致沟槽开口容易堵塞,造成孔洞(void)的问题。虽然目前已采用流动式化学气相沉积(FlowableChemicalVaporDeposition,FCVD)系统,以高流动性的硅-氮前驱材料(silicon-and-nitrogenprecursor),例如三硅烷胺(Trisilane,TSA),来制备填沟介电层,解决沟槽产生孔洞的问题。然而,由于流动式化学气相沉积所制备的填沟介电层,例如硅氮烷(silazane)材质层,含氮量太高质地过于松软。需进一步在含氧气体,例如臭氧,气氛中进行烘烤(curing),将填沟介电层中的Si-N键结转化成Si-O键结,使填沟介电层在后续热退火步骤之后能形成质地较致密的二氧化硅材质层。然而,目前臭氧烘烤步骤的键结转化效率仍有待提升,无法在有限的制作工艺时间和较低的热预算(thermalbudget)条件下提供与其他填沟制作工艺相同品质的填沟介电层。
因此,有需要提供一种更先进的填沟介电层及其制作方法,以改善现有技术所面临的问题。
发明内容
本发明的一个面向是有关于一种具有良好填沟能力的填沟介电层(gap-fillingdielectriclayer),其中此填沟介电层的氮含量实质小于1×1022个原子/立方厘米(atoms/cm3)。
本发明的另一个面向是有关于一种填沟介电层的制作方法,可以在有限的制作工艺时间和较低的热预算条件下,提供具有良好填沟能力和介电隔离效果的填沟介电层。此一制作方法包括下述步骤:首先于基材上沉积含硅介电层。然后,依序对含硅介电层进行烘烤制作工艺、原位(in-situ)湿式处理以及热退火制作工艺。
本发明的又一个面向是有关于一种具有良好填沟能力和介电隔离效果之填沟介电层的半导体元件,此半导体元件包括基材以及位于基材上的填沟介电层。其中,填沟介电层的氮含量实质小于1×1022个原子/立方厘米。
本发明的再一个面向是有关于一种制作半导体元件的方法,使其具有良好填沟能力和介电隔离效果的填沟介电层。此一方法包括下述步骤:首先,提供一基材,再于基材上沉积含硅介电层。之后,依序对含硅介电层进行烘烤制作工艺、原位湿式处理以及热退火制作工艺。
根据上述,本发明的实施例是先在基材上沉积含硅介电层。然后,依序对含硅介电层进行烘烤制作工艺、原位湿式处理以及热退火制作工艺。可以在有限的制作工艺时间和较低的热预算条件下,在基材上形成氮含量实质小于1×1022个原子/立方厘米的填沟介电层,大幅提高填沟能力和介电隔离效果,解决现有技术因半导体集成电路特征尺寸缩小所导致的介电层填沟品质不良的问题。
附图说明
为了对本发明的上述实施例及其他目的、特征和优点能更明显易懂,特举数个优选实施例,并配合所附的附图,作详细说明如下:
图1为本发明的一实施例所绘示的一种制作具有填沟介电层的半导体元件的方法流程图;
图2A至图2F为本发明的一实施例所绘示的一种制作具有填沟介电层的半导体元件的制作工艺结构剖视图;
图3为本发明一实施例所绘示的一种用来制作半导体元件的制作工艺机台的结构俯视图;以及
图4为本发明一实施例所绘示以椭圆偏光仪量测填沟介电层表面所得到的折射率统计分析图。
符号说明
10:半导体元件100:填沟介电层
101:基材101a:基材的表面
102:沟槽103:鳍状部
104:含硅介电层105:烘烤制作工艺
106:原位湿式处理107:热退火制作工艺
108:浅沟隔离结构109:层间介电层
110:介层插塞111:金属导线层
300:制作工艺机台301a:腔室
301b:腔室301c:腔室
301e:腔室301f:腔室
302:前开式晶片盒303:机器手臂
304:压力缓冲槽305:机器手臂
S1:提供具有开口或沟槽的图案化基材。
S2:在基材上进行一沉积制作工艺,以形成含硅介电层。
S3:对含硅介电层进行一烘烤制作工艺。
S4:对烘烤后的含硅介电层进行原位湿式处理。
S5:对湿式处理过后的含硅介电层进行一热退火制作工艺,以形成填沟介电层。
S6:在填沟介电层上进行一连串后段制作工艺,以完成半导体元件的制备。
具体实施方式
本发明是提供一种具有良好填沟能力的填沟介电层及其制作方法与应用。为了对本发明的上述实施例及其他目的、特征和优点能更明显易懂,下文特举数个优选实施例,并配合所附的附图作详细说明。但必须注意的是,这些特定的实施案例与方法,并非用以限定本发明。本发明仍可采用其他特征、元件、方法及参数来加以实施。优选实施例的提出,仅用以例示本发明的技术特征,并非用以限定本发明的权利要求。该技术领域中具有通常知识者,将可根据以下说明书的描述,在不脱离本发明的精神范围内,作均等的修饰与变化。在不同实施例与附图之中,相同的元件,将以相同的元件符号加以表示。
图1是根据本发明的一实施例所绘示的一种制作具有填沟介电层100的半导体元件10的方法流程图。图2A至图2F是绘示制作具有填沟介电层100的半导体元件10的制作工艺结构剖视图。此一方法包括下述步骤:
首先,请参照步骤S1,提供具有开口或沟槽102的图案化基材101。在本发明的一些实施例中,基材101可以是一种半导体基材。在本发明的另外一些实施例之中,基材101除了包含一半导体层外,还包括其他半导体层,例如,外延层或绝缘层。例如在本发明的一些优选实施例之中,基材101可以是包含有绝缘层的一种绝缘层上覆硅基材。在本实施例中,基材101可以是一种硅晶片。另外,基材101之中或之上可以包含多个由前段制作工艺(front-end)所形成的半导体构件(未绘示)。
基材101的图案化,可以采用包括干式或湿式蚀刻制作工艺移除表面101a上的一部分基材101,用于在基材101的表面101a形成至少一个沟槽102。在本实施例之中,是采用干式蚀刻制作工艺,例如反应离子蚀刻(ReactiveIonEtching,RIE)制作工艺,在基材101表面101a上形成多个沟槽102,以用来定义出多个鳍状部(fins)103(如图2A所绘示)。
之后请参照步骤S2,在基材101上进行一沉积制作工艺,例如化学气相沉积(ChemicalVaporDeposition,CVD)或流动式化学气相沉积,形成含硅介电层104覆盖基材表面101a,并填充沟槽102(如图2B所绘示)。在本发明的一些实施例中,优选是采用流动式化学气相沉积法,以高流动性的不含碳的硅-氮前驱物来进行沉积,形成含硅介电层104。其中,无碳的硅-氮前驱物包括三硅烷胺、H2N(SiH3)、HN(SiH3)2、N(SiH3)3或其他甲硅烷基胺聚体(silylamines)或上述的组合。另外,沉积制作工艺中还可以加入其他气体,例如氢气(H2)、氮气(N2)、氨(NH3)、联胺(N2H4)、硅甲烷(Silane,SiH4)、氦气(He)、氩气(Ar)或其任意组合。在本实施例中,是采用三硅烷胺作为硅-氮前驱物,在气体流量50sccm、反应温度实质介于150℃至500℃,反应压力50~600torr的制作工艺条件下进行沉积,在基材101的表面101a上沉积含硅介电层104。
在形成含硅介电层104之后,请参照步骤S3,对含硅介电层104进行一烘烤制作工艺105(如图2C所绘示)。在本发明的一些实施例之中,烘烤制作工艺是在温度实质介于150℃至400℃之间,制作工艺压力实质介于500torr至700torr之间的含氧气氛(Oxygencontainingatmosphere)中进行。其中,含氧气氛可以包括氧气(Oxygen,O2)、臭氧(Ozone,O3)或二者的组合。在本发明的优选实施例中,烘烤制作工艺在烘烤温度实质为150℃,制作工艺压力实质为600torr的含氧气氛中进行。其中,氧气流量实质为2000sccm、臭氧流量实质为27000sccm,另外也包含流量实质为3000sccm氮气和氦气等惰性气体。
请再参照步骤S4,对烘烤后的含硅介电层104进行原位湿式处理106。而此处所谓的原位处理(in-situtreatment),即是指湿式处理可以在不破真空而的状态下,在同一腔室(Chamber)或同一机台中完成。其中,湿式处理106的制作工艺压力,基本上与烘烤制作工艺105所采用的制作工艺压力相同。另外,在本发明的一些实施例中,湿式处理106的基材温度,也可以和烘烤制作工艺105所采用的基材温度实质相同。
请参照图3,图3根据本发明一实施例所绘示的一种用来制作半导体元件10之制作工艺机台300的结构俯视图。制作工艺机台300包含多个腔室,例如腔室301a、301b、301c、301e和301f。具有含硅介电层104的基材101(晶片)经由前开式晶片盒(frontopeningunifiedpod,FOUPs)302以机器手臂303置入制作工艺机台300的压力缓冲槽304,再经由机器手臂305送入腔室301a、301b、301c、301e或301f中进行一项预先选定的制作工艺,例如沉积制作工艺、蚀刻制作工艺、清洗制作工艺、烘烤制作工艺、湿式处理或退火制作工艺…等。待该选定制作工艺结束后,再由机器手臂305取出基材101(晶片),经由压力缓冲槽304传送至下一个腔室301a、301b、301c、301e或301f中进行另一项制作工艺。值得注意的是,虽然本实施例仅以制作工艺机台300来例示实施制作工艺步骤的方式。并非限制本发明的制作工艺步骤需在特定或单一制作工艺机台实施。其他不同的制作工艺机台仍可被采用来实施本发明实施例中的各项步骤。
在本发明的一些实施例中,烘烤制作工艺105和原位湿式处理106可以在同一腔室,例如腔室301a,中进行。其中,腔室301a内部的制作工艺压力实质维持在600torr,且基材温度维持在实质150℃。在本发明的另外一些实施例中,烘烤制作工艺105和原位湿式处理106可以在同一制作工艺机台300中的不同腔室中进行,例如可以分别在腔室301a和301b中进行烘烤制作工艺105和原位湿式处理106。当基材101(晶片)在压力缓冲区304中传送时,压力缓冲槽304内部的压力和腔室301a和301b的制作工艺压力保持恒定,例如实质维持在600torr。因此,烘烤制作工艺105和原位湿式处理106可以在不破真空的环境下连续进行。
原位湿式处理106的实施方式,包括以含水(water)处理剂与含硅介电层104直接接触。其中,含水处理剂包括温度实质介于100℃至200℃的水蒸气。在本实施例之中,烘烤制作工艺105和原位湿式处理106是在同一腔室中进行。其中,原位湿式处理106的制作工艺压力和基材温度,维持与烘烤制作工艺105的制作工艺压力和基材温度实质相同,其优选分别为600torr和150℃。并且在其他气体流量维持恒定的状态下,采用温度实质为120℃的水蒸气与烘烤后的含硅介电层104直接接触(如图2D所绘示),其中二者的接触时间实质介于2分钟至10分钟之间。
接着请参照步骤S5,对湿式处理过后的含硅介电层104进行一热退火制作工艺107,以形填沟介电层100(如图2E所绘示)。为了顾及半导体元件10的热预算,热退火制作工艺107优选是一种低温热退火制作工艺。例如,在本发明的一些实施例中,热退火制作工艺107的热退火温度实质介于150℃至400℃之间。并且在含氧气氛中进行。热退火制作工艺中的含氧气氛,可以包括,例如含有氧气、臭氧、水蒸气、过氧化氢(H2O2)或上述气体的组合的含氧气体。在本实施例之中,热退火制作工艺107是在温度实质为300℃的臭氧气氛中进行。
在热退火制作工艺107之后,使用傅里叶转换红外光谱(FourierTransformInfraredSpectrometer,FTIR)来检测经由前述制作工艺所形成的填沟介电层100,可以发现填沟介电层100包含Si-N、Si-O、S-OH和S-N键结。可推测,但不以此为限,填沟介电层100可以是由包含硅氮烷的二氧化硅材质所构成。其中,填沟介电层100的氮含量实质小于1×1022个原子/立方厘米。与现有技术所制作的填沟介电层相比,填沟介电层100中的Si-N键结明显减少,可验证前述制作工艺所提供的填沟介电层100具有较高的Si-N/Si-O键结的转换效率;填沟介电层100中的二氧化硅质地密度明显较现有技术所制作的填沟介电层更致密。在本实施例中,填沟介电层100实质由二氧化硅所构成,其氮含量实质为0.5×1022个原子/立方厘米。
另外,将覆盖有填沟介电层100的基材101(例如,硅晶片)以椭圆偏光仪(ellipsometers)量测其表面不同部位的折射率,来验证填沟介电层100的表面形貌(geometries)。请参照图4,图4根据本发明一实施例所绘示以椭圆偏光仪量测填沟介电层表面所得到的折射率统计分析图。其中横轴代表受测晶片编号,纵轴代表每一晶片表面不同部位的折射率的变异程度。对比于现有技术所制作的填沟介电层的表面折射率(以三角形折线表示),填沟介电层100所量测到的表面折射率(以方形折线表示)变异程度明显降低。显示,经由前述制作工艺所形成的填沟介电层100,具有比现有技术所制作的填沟介电层更均一、稳定的表面形貌。
后续请参照步骤S6,在填沟介电层100上进行一连串后段制作工艺(downstreamprocesses)以完成半导体元件10的制备(如图2F所绘示)。在本发明的一些实施例中,填沟介电层100可以通过后续的蚀刻或化学机械研磨(ChemicalMechanicalPolishing,CMP)制作工艺,形成半导体元件10的浅沟隔离结构108。在本发明的另一些实施例中,填沟介电层100可以作为半导体元件10的层间介电层109,并经由后续的金属内连线制作工艺(metalinterconnectionprocess),容许多个介层插塞(vias)110和金属导线层111形成于其中,用来电连接位于基材101中的半导体构件(未绘示)。
根据上述,本发明的实施例是先在基材上沉积含硅介电层。然后,依序对含硅介电层进行烘烤制作工艺、原位湿式处理以及热退火制作工艺。可以在有限的制作工艺时间和较低的热预算条件下,在基材上形成氮含量实质小于1×1022个原子/立方厘米的填沟介电层。经由傅里叶转换红外光谱检测与椭圆偏光仪量测可以验证,由本发明的实施例所提供的填沟介电层,具有比现有填沟介电层更佳的填沟能力和介电隔离效果,可解决现有技术因半导体集成电路特征尺寸缩小所导致的介电层填沟品质不良的问题。
虽然结合以上优选实施例公开了本发明,然而其并非用以限定本发明,任何该技术领域中具有通常知识者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,因此本发明的保护范围应当以附上的权利要求所界定的为准。
Claims (20)
1.一种填沟介电层(gap-fillingdielectriclayer),具有实质小于1×1022个原子/立方厘米(atoms/cm3)的一氮含量。
2.如权利要求1所述的填沟介电层,其中该填沟介电层形成于一基材之上,并填充于该基材的至少一沟槽(trench)之中。
3.如权利要求1所述的填沟介电层,还包括二氧化硅(SiliconOxide)。
4.如权利要求1所述的填沟介电层,包括一浅沟隔离(ShallowTrenchIsolation)结构、一层间介电层(InterlayerDielectric,ILD)或二者的组合。
5.一种填沟介电层的制作方法,包括:
在一基材上沉积一含硅介电层;
对该含硅介电层进行一烘烤制作工艺;
对该含硅介电层进行一原位(in-situ)湿式处理;以及
对该含硅介电层进行一热退火制作工艺。
6.如权利要求5所述的填沟介电层的制作方法,其中沉积该含硅介电层的步骤,采用包括三硅烷胺(Trisilane,TSA)的一前驱物(precursor)来进行沉积。
7.如权利要求5所述的填沟介电层的制作方法,其中该烘烤制作工艺是在一含氧气氛(Oxygencontainingatmosphere)中进行,且具有实质介于150℃至400℃之间的一烘烤温度。
8.如权利要求7所述的填沟介电层的制作方法,其中该含氧气氛包括臭氧(Ozone,O3)。
9.如权利要求5所述的填沟介电层的制作方法,其中该原位湿式处理包括使该含硅介电层与一含水(water)处理剂直接接触。
10.如权利要求9所述的填沟介电层的制作方法,其中该含水处理剂包括温度实质介于100℃至200℃的水蒸气。
11.如权利要求10所述的填沟介电层的制作方法,其中该水蒸气与该含硅介电层的接触时间实质介于2分钟至10分钟之间。
12.如权利要求5所述的填沟介电层的制作方法,其中该烘烤制作工艺和该原位湿式处理是在同一腔室中(Chamber)进行,且该腔室具有实质为600torr的一制作工艺压力。
13.如权利要求5所述的填沟介电层的制作方法,其中该热退火制作工艺包含实质介于150℃至400℃的一热退火温度。
14.如权利要求5所述的填沟介电层的制作方法,其中热退火后的该含硅介电层具有实质小于1×1022个原子/立方厘米的一氮含量。
15.一种半导体元件,包括:
基材;以及
填沟介电层,位于该基材上,且具有实质小于1×1022个原子/立方厘米的一氮含量。
16.如权利要求15所述的半导体元件,其中该基材还包括至少二沟槽用来定义至少一鳍状部(fins),且该填沟介电层填充于该些沟槽之中。
17.如权利要求15所述之半导体元件,该填沟介电层包括二氧化硅。
18.如权利要求15所述的半导体元件,其中该填沟介电层包括一浅沟隔离结构、一层间介电层或二者的组合。
19.一种半导体元件的制作方法,包括:
提供一基材;
在该基材上沉积一含硅介电层;
对该含硅介电层进行一烘烤制作工艺;
对该含硅介电层进行一原位湿式处理;以及
对该含硅介电层进行一热退火制作工艺。
20.如权利要求19所述的半导体元件的制作方法,其中该原位湿式处理和该烘烤制作工艺在同一腔室中进行,且包括使该含硅介电层与温度实质介于100℃至200℃的水蒸气直接接触。
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