CN105303008A - Analog integrated circuit optimization method and system - Google Patents
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Abstract
本发明实施例公开了一种模拟集成电路优化方法和系统,所述方法通过采用电路级模拟程序对所述新一代种群进行仿真,得到所述新一代种群中各个个体的电路性能指标的同时,所述采用SPICE模型和高斯过程回归利用SPICE仿真器对新一代种群进行蒙特卡罗分析估算得到良率估计值;使得在种群进化过程中同时将电路的性能指标和良率作为约束条件参与到进化算法当中,从而解决了现有技术中最终决策时存在良率低的问题。
The embodiment of the present invention discloses an analog integrated circuit optimization method and system. The method simulates the new-generation population by using a circuit-level simulation program to obtain the circuit performance indicators of each individual in the new-generation population. The SPICE model and Gaussian process regression are used to perform Monte Carlo analysis and estimation on the new generation of populations using SPICE simulators to obtain yield estimates; so that in the process of population evolution, the performance index and yield of the circuit are used as constraints to participate in the evolutionary algorithm at the same time Among them, the problem of low yield rate in the final decision-making in the prior art is solved.
Description
技术领域technical field
本发明涉及电子设计自动化(EDA)技术领域,更具体地说,涉及一种模拟集成电路优化方法和系统。The present invention relates to the technical field of Electronic Design Automation (EDA), more specifically, to an analog integrated circuit optimization method and system.
背景技术Background technique
随着集成电路技术不断向纳米级先进节点工艺推进,模拟集成电路设计面临的挑战也更为突出。一方面应用需求要求模拟集成电路单元具有更复杂的功能、更优越的性能、更小的面积和更小的功耗。例如,用于4G通信的射频电路单元可能需要在兼容LTE、GSM、蓝牙等多种标准的同时又要求具有较小的面积和较低的功耗。因此,设计者需要同时考虑多个带约束条件的设计目标,例如这些目标可以包括:电路性能、功耗和面积(PPA)等。并且这些目标中有的目标还有可能是互斥的。另一方面由于纳米级集成电路制造中的工艺涨落、版图依赖效应和互连寄生效应等问题,使得设计者在设计阶段除了面对晶体管的栅长(L)、栅宽(W)、偏置电压电流等设计变量外,还需要考虑工艺涨落对良率的影响以及版图依赖效应等对电路性能的影响。With the continuous advancement of integrated circuit technology to nano-scale advanced node technology, the challenges faced by analog integrated circuit design are also more prominent. On the one hand, the application requirements require that the analog integrated circuit unit has more complex functions, better performance, smaller area and lower power consumption. For example, the radio frequency circuit unit used for 4G communication may need to be compatible with various standards such as LTE, GSM, and Bluetooth, and at the same time require a smaller area and lower power consumption. Therefore, designers need to consider multiple design goals with constraints at the same time, for example, these goals may include: circuit performance, power consumption and area (PPA) and so on. And some of these goals may be mutually exclusive. On the other hand, due to the process fluctuations, layout-dependent effects and interconnection parasitic effects in the manufacture of nanoscale integrated circuits, the designer has to face the gate length (L), gate width (W) and bias of the transistor in the design stage. In addition to design variables such as voltage and current, it is also necessary to consider the impact of process fluctuations on yield and the impact of layout-dependent effects on circuit performance.
如此复杂的设计如果想要通过基于经验及大量迭代的传统设计方法找到最优设计几乎是不可能的,尤其是在小尺寸的纳米工艺中,其制造工艺(如光刻、离子注入、氧化、化学机械抛光等)精度的控制变得非常困难,在工艺涨落比较显著而且不可避免的情况下,不能正确评估工艺涨落的对电路的影响将导致良率下降,产品上市延迟等问题。上述两方面的挑战可以归纳为如何更好更快地解决基于大量的设计变量和工艺涨落的约束多目标优化(MOO)问题,即:For such a complex design, it is almost impossible to find the optimal design through the traditional design method based on experience and a large number of iterations, especially in the small-scale nanotechnology, its manufacturing process (such as photolithography, ion implantation, oxidation, Chemical mechanical polishing, etc.) precision control becomes very difficult. In the case of significant and unavoidable process fluctuations, failure to correctly evaluate the impact of process fluctuations on the circuit will lead to a decline in yield and delay in product launch. The above two challenges can be summarized as how to better and faster solve the constrained multi-objective optimization (MOO) problem based on a large number of design variables and process fluctuations, namely:
最小或最大化 min or max
约束条件
其中,和代表与电路的性能、面积、良率或功耗有关的函数。x1...xm表示设计变量。in, and Represents a function related to the performance, area, yield, or power consumption of a circuit. x 1 ... x m represent design variables.
经过对ANewApproachforCombiningYieldandPerformanceinBehaviouralModelsforAnalogueIntegratedCircuits以及AnAutomatedDesignMethodologyforYieldAwareAnalogCircuitSynthesisinSubmicronTechnology的论文进行分析,现有技术中在解决基于大量的设计变量和工艺涨落的约束多目标优化(MOO)问题过程中常用的模拟集成电路快速设计与优化方法,可归纳为步骤S101-S108,步骤101:获取初始电路网表和晶体管统计模型;步骤S102:对所述初始电路网表和晶体管统计模型分析得到设计变量、优化目标及约束条件;步骤S103:依据所述设计变量的范围随机产生初始种群;步骤S104:更改所述设计变量,依据更改后的所述设计变量生成所述初始种群中每个个体对应的电路网表,所述电路网表代表新一代种群;步骤105:通过采用电路级模拟程序(Simulationprogramwithintegratedcircuitemphasis,SPICE)对所述第一代种群进行仿真,得到所述新一代种群中各个个体的电路性能指标,如电路性能、面积、功耗等指标;步骤S106:依据所述电路性能指标采用进化算法对所述新一代种群进行进化得到下一代种群;步骤S107:根据预设的最大进化代数判断所述下一代种群进化是否结束,如果是,执行步骤S108,否则继续执行步骤S104;步骤S108:生成当前种群对应的Pareto最佳解集,对得到的Pareto最佳解集进行蒙特卡罗分析,得到良率估计值;步骤S109:依据Pareto最佳解集进行决策并验证。After analyzing the papers of ANewApproachforCombiningYieldandPerformanceinBehaviouralModelsforAnalogueIntegratedCircuits and AnAutomatedDesignMethodologyforYieldAwareAnalogCircuitSynthesisinSubmicronTechnology, the commonly used rapid design and optimization methods for analog integrated circuits in the prior art in solving constrained multi-objective optimization (MOO) problems based on a large number of design variables and process fluctuations can be summarized as Steps S101-S108, Step 101: Obtain the initial circuit netlist and transistor statistical model; Step S102: Analyze the initial circuit netlist and transistor statistical model to obtain design variables, optimization objectives and constraints; Step S103: According to the design The scope of the variable randomly generates an initial population; step S104: change the design variable, and generate a circuit netlist corresponding to each individual in the initial population according to the modified design variable, and the circuit netlist represents a new generation population; Step 105: Simulate the first-generation population by using a circuit-level simulation program (Simulation program with integrated circuit emphasis, SPICE), to obtain circuit performance indicators of each individual in the new-generation population, such as circuit performance, area, power consumption, etc.; step S106: According to the circuit performance index, the evolutionary algorithm is used to evolve the new generation population to obtain the next generation population; Step S107: According to the preset maximum evolution algebra, it is judged whether the evolution of the next generation population is over, and if so, execute step S108 , otherwise continue to execute step S104; step S108: generate the Pareto optimal solution set corresponding to the current population, perform Monte Carlo analysis on the obtained Pareto optimal solution set, and obtain the yield estimate; step S109: according to the Pareto optimal solution set Make decisions and validate.
当采用上述传统的方法在进行电路设计优化时,在上述过程中由于良率设计没有参与进化算法,所以Pareto最佳解集上的良率不一定是最优的,由此得到的决策有可能会存在良率低的问题,因此如何在优化过程中把良率作为优化约束条件或优化目标参与进化算法,成为本领域技术人员亟待解决的技术问题之一。When adopting the above-mentioned traditional method for circuit design optimization, since the yield rate design does not participate in the evolutionary algorithm in the above process, the yield rate on the Pareto optimal solution set is not necessarily optimal, and the resulting decision may be There will be a problem of low yield rate, so how to use the yield rate as an optimization constraint or optimization goal to participate in the evolutionary algorithm in the optimization process has become one of the technical problems to be solved urgently by those skilled in the art.
发明内容Contents of the invention
本发明的目的在于提供一种模拟集成电路优化方法和系统,用于使得在优化过程中把良率作为优化约束条件或优化目标参与进化算法。The purpose of the present invention is to provide an analog integrated circuit optimization method and system, which is used to make the yield rate as an optimization constraint condition or optimization goal participate in the evolutionary algorithm in the optimization process.
为实现上述目的,本发明实施例提供了如下技术方案:In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:
一种模拟集成电路优化方法,包括:A method for optimizing an analog integrated circuit, comprising:
获取初始电路网表和晶体管统计模型;Obtain initial circuit netlist and transistor statistical model;
对所述初始电路网表和晶体管统计模型分析得到设计变量、优化目标及约束条件;Analyzing the initial circuit netlist and transistor statistical model to obtain design variables, optimization objectives and constraints;
依据所述设计变量的范围随机产生初始种群;Randomly generating an initial population according to the range of the design variables;
更改所述设计变量,依据更改后的所述设计变量生成所述初始种群中每个个体对应的电路网表,所述电路网表代表新一代种群;changing the design variable, and generating a circuit netlist corresponding to each individual in the initial population according to the modified design variable, the circuit netlist representing a new generation population;
通过采用电路级模拟程序对所述新一代种群进行仿真,得到所述新一代种群中各个个体的电路性能指标,所述采用SPICE模型和高斯过程回归利用SPICE仿真器对新一代种群进行蒙特卡罗分析估算得到良率估计值,所述良率估计值包括种群中每个个体观测点上良率的待预测值;The circuit performance index of each individual in the new generation population is obtained by simulating the new generation population by using a circuit-level simulation program, and the SPICE model and Gaussian process regression are used to perform Monte Carlo on the new generation population by using a SPICE simulator. Analyzing and estimating to obtain an estimated value of the yield rate, the estimated value of the yield rate includes the value to be predicted of the yield rate at each individual observation point in the population;
依据所述电路性能指标和良率估计值采用进化算法对所述新一代种群进行进化得到下一代种群;Evolving the new-generation population by using an evolutionary algorithm according to the circuit performance index and the estimated yield value to obtain the next-generation population;
根据预设的最大进化代数判断进化是否结束,如果是,生成当前种群对应的Pareto最佳解集,依据Pareto最佳解集进行决策并验证,如果否,更改所述设计变量,依据更改后的所述设计变量生成所述初始种群中每个个体对应的第一电路网表,所述第一电路网表代表新一代种群,直至生成当前种群对应的Pareto最佳解集,并依据Pareto最佳解集进行决策并验证为止。Determine whether the evolution is over according to the preset maximum evolution algebra, if yes, generate the Pareto optimal solution set corresponding to the current population, make a decision and verify it according to the Pareto optimal solution set, if not, change the design variable, and then change it according to the changed The design variable generates the first circuit netlist corresponding to each individual in the initial population, and the first circuit netlist represents the new generation population until the Pareto optimal solution set corresponding to the current population is generated, and according to the Pareto optimal solution set The solution set is decided and verified.
优选的,上述模拟集成电路优化方法中,所述采用SPICE模型和高斯过程回归利用SPICE仿真器对新一代种群进行蒙特卡罗分析估算得到良率估计值,包括:Preferably, in the above analog integrated circuit optimization method, the SPICE model and Gaussian process regression are used to perform Monte Carlo analysis and estimation of the new generation of populations using SPICE simulators to obtain yield estimates, including:
获取当前种群的训练点集(Y,X),Y为种群中每个个体观测点的良率的观测值,X为种群中每个个体观测点;Obtain the training point set (Y, X) of the current population, Y is the observed value of the yield of each individual observation point in the population, X is each individual observation point in the population;
依据所述训练点集(Y,X)由公式(1)计算得到群中每个个体观测点的良率的待预测值y*的后验分布为
其中,所述公式(1)为:
优选的,上述模拟集成电路优化方法中,所述获取当前种群的训练点集,包括:Preferably, in the above analog integrated circuit optimization method, the acquisition of the training point set of the current population includes:
判断当前种群为第几代种群;Determine which generation population the current population is;
当所述种群为第一代种群时,在所述第一代种群的全部个体观测点上进行蒙特卡罗分析,所述第一代种群中的全部个体观测点为当第一代种群的训练点集,将所述第一代种群的训练点集作为当前种群的训练点集(Y,X);When the population is the first-generation population, Monte Carlo analysis is performed on all individual observation points of the first-generation population, and all individual observation points in the first-generation population are training Point set, using the training point set of the first generation population as the training point set (Y, X) of the current population;
当所述种群为第Z代种群时,以第Z-1代种群的全部个体观测点作为当前种群的训练点集(Y,X)。When the population is the Z generation population, all individual observation points of the Z-1 generation population are used as the training point set (Y, X) of the current population.
一种模拟集成电路优化系统,包括:An analog integrated circuit optimization system comprising:
采集模块,用于获取用户输入的初始电路网表和晶体管统计模型;The collection module is used to obtain the initial circuit netlist and transistor statistical model input by the user;
分析模块,用于对所述初始电路网表和晶体管统计模型分析得到设计变量、优化目标及约束条件;An analysis module, configured to analyze the initial circuit netlist and transistor statistical model to obtain design variables, optimization objectives and constraints;
种群生成模块,用于依据所述设计变量的范围随机产生初始种群;A population generation module, configured to randomly generate an initial population according to the range of the design variables;
第一进化模块,用于更改所述设计变量,依据更改后的所述设计变量生成所述初始种群中每个个体对应的电路网表,所述电路网表代表新一代种群;The first evolution module is used to change the design variable, and generate a circuit netlist corresponding to each individual in the initial population according to the modified design variable, and the circuit netlist represents a new generation population;
仿真模块,用于通过采用电路级模拟程序对所述新一代种群进行仿真,得到所述新一代种群中各个个体的电路性能指标,所述采用SPICE模型和高斯过程回归利用SPICE仿真器对新一代种群进行蒙特卡罗分析估算得到良率估计值,所述良率估计值包括种群中每个个体观测点上良率的待预测值;The simulation module is used to simulate the new-generation population by using a circuit-level simulation program to obtain the circuit performance index of each individual in the new-generation population. The SPICE model and Gaussian process regression are used to simulate the new-generation population by using a SPICE model and Gaussian process regression. The population is subjected to Monte Carlo analysis and estimation to obtain an estimated yield value, and the estimated yield value includes the to-be-predicted value of the yield rate at each individual observation point in the population;
第二进化模块,用于依据所述电路性能指标和良率估计值采用进化算法对所述新一代种群进行进化得到下一代种群;The second evolution module is used to evolve the new-generation population to obtain the next-generation population by using an evolutionary algorithm according to the circuit performance index and the estimated value of yield;
决策验证模块,用于根据预设的最大进化代数判断进化是否结束,如果是,生成当前种群对应的Pareto最佳解集,依据Pareto最佳解集进行决策并验证,如果否,更改所述设计变量,依据更改后的所述设计变量生成所述初始种群中每个个体对应的电路网表,所述电路网表代表新一代种群,直至生成当前种群对应的Pareto最佳解集,并依据Pareto最佳解集进行决策并验证为止。The decision verification module is used to judge whether the evolution is over according to the preset maximum evolution algebra, if yes, generate the Pareto optimal solution set corresponding to the current population, make a decision and verify it according to the Pareto optimal solution set, if not, change the design variables, according to the modified design variables to generate a circuit netlist corresponding to each individual in the initial population, the circuit netlist represents a new generation population until the Pareto optimal solution set corresponding to the current population is generated, and according to the Pareto The best solution set is used for decision-making and verification.
优选的,上述模拟集成电路优化系统中,所述仿真模块,包括:Preferably, in the above-mentioned simulation integrated circuit optimization system, the simulation module includes:
良率计算单元,用于获取当前种群的训练点集(Y,X),Y为种群中每个个体观测点的良率的观测值,X为种群中每个个体观测点;A yield calculation unit is used to obtain the training point set (Y, X) of the current population, Y is the observed value of the yield of each individual observation point in the population, and X is each individual observation point in the population;
依据所述训练点集(Y,X)由公式一计算得到良率的待预测值y*的后验分布为
其中,所述公式一为:
优选的,上述模拟集成电路优化系统中,所述仿真模块,还包括:Preferably, in the above-mentioned analog integrated circuit optimization system, the simulation module further includes:
训练点集选取模块,用于判断当前种群为第几代种群;当所述种群为第一代种群时,在所述第一代种群的全部个体上进行蒙特卡罗分析,所述第一代种群中的全部个体为当第一代种群的训练点集,将所述第一代种群的训练点集作为当前种群的训练点集(Y,X);当所述种群为第Z代种群时,以第Z-1代种群的全部个体作为当前种群的训练点集(Y,X)。The training point set selection module is used to judge which generation population the current population is; when the population is the first generation population, Monte Carlo analysis is performed on all individuals of the first generation population, and the first generation All individuals in the population are the training point set of the first generation population, and the training point set of the first generation population is used as the training point set (Y, X) of the current population; when the population is the Z generation population , taking all the individuals of the Z-1 generation population as the training point set (Y, X) of the current population.
通过以上方案可知,本发明实施例提供的模拟集成电路优化方法,在通过采用电路级模拟程序(Simulationprogramwithintegratedcircuitemphasis,SPICE)对所述新一代种群进行仿真,得到所述新一代种群中各个个体的电路性能指标的同时,所述采用SPICE模型和高斯过程回归利用SPICE仿真器对新一代种群进行蒙特卡罗分析估算得到良率估计值;使得在种群进化过程中同时将电路的性能指标和良率作为约束条件参到进化算法当中,从而解决了现有技术中解决了最终决策时存在良率低的问题。It can be seen from the above scheme that the analog integrated circuit optimization method provided by the embodiment of the present invention uses a circuit-level simulation program (Simulation program with integrated circuit emphasis, SPICE) to simulate the new generation population to obtain the circuit performance of each individual in the new generation population At the same time as the indicators, the SPICE model and Gaussian process regression are used to perform Monte Carlo analysis and estimation on the new generation of populations using SPICE simulators to obtain yield estimates; so that the circuit performance indicators and yields are used as constraints during the population evolution process. Participating in the evolutionary algorithm, thereby solving the problem of low yield in the prior art when the final decision is made.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为本发明实施例公开的一种模拟集成电路优化方法的流程图;FIG. 1 is a flow chart of an analog integrated circuit optimization method disclosed in an embodiment of the present invention;
图2为本发明实施例公开的一种模拟集成电路优化系统的结构示意图。FIG. 2 is a schematic structural diagram of an analog integrated circuit optimization system disclosed in an embodiment of the present invention.
具体实施方式detailed description
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
在传统的模拟集成电路快速设计与优化方法中,优化过程中把良率作为优化约束条件或优化目标还比较困难。主要原因在于,准确的电路良率估计值是将由芯片代工厂提供的带工艺统计信息的SPICE模型(主要是CMOS晶体管的BSIM模型)采用SPICE仿真器进行蒙特卡罗分析得到。蒙特卡罗分析本身需要大量抽样,而进化算法需要对每一代种群中的每个个体进行蒙特卡罗分析,这就大大增加了实验测量的计算代价,使得将良率指标加入简化算法几乎不可能实现。因此,只能在得到Pareto最佳解集后进行蒙特卡罗分析来验证良率。In the traditional rapid design and optimization methods of analog integrated circuits, it is still difficult to use the yield rate as an optimization constraint or optimization goal in the optimization process. The main reason is that the accurate estimation of the circuit yield rate is obtained by Monte Carlo analysis of the SPICE model (mainly the BSIM model of CMOS transistors) provided by the chip foundry with process statistics information. Monte Carlo analysis itself requires a large number of samples, while evolutionary algorithms need to perform Monte Carlo analysis on each individual in each generation of the population, which greatly increases the computational cost of experimental measurements, making it almost impossible to add yield indicators to the simplified algorithm accomplish. Therefore, Monte Carlo analysis can only be performed to verify the yield after obtaining the Pareto optimal solution set.
针对于此,本申请实施例公开了一种兼顾良率和性能的模拟集成电路优化方法,参见图1,包括:In view of this, the embodiment of the present application discloses an analog integrated circuit optimization method that takes both yield and performance into consideration, see Figure 1, including:
步骤S101:获取初始电路网表和晶体管统计模型;Step S101: Obtain an initial circuit netlist and transistor statistical model;
步骤S102:对所述初始电路网表和晶体管统计模型分析得到设计变量、优化目标及约束条件;Step S102: analyzing the initial circuit netlist and transistor statistical model to obtain design variables, optimization objectives and constraints;
步骤S103:依据所述设计变量的范围随机产生初始种群;Step S103: Randomly generate an initial population according to the range of the design variable;
步骤S104:更改所述设计变量,依据更改后的所述设计变量生成所述初始种群中每个个体对应的电路网表,所述电路网表代表新一代种群,记为第一代种群;Step S104: changing the design variable, and generating a circuit netlist corresponding to each individual in the initial population according to the modified design variable, the circuit netlist represents a new generation population, which is recorded as the first generation population;
步骤105:通过采用电路级模拟程序(Simulationprogramwithintegratedcircuitemphasis,SPICE)对所述新一代种群进行仿真,得到所述新一代种群中各个个体的电路性能指标,例如面积、功耗等指标,所述采用SPICE模型和高斯过程回归利用SPICE仿真器对新一代种群进行蒙特卡罗分析估算得到良率估计值;Step 105: Simulate the new-generation population by using a circuit-level simulation program (Simulation program with integrated circuit emphasis, SPICE), to obtain the circuit performance indicators of each individual in the new-generation population, such as area, power consumption and other indicators, and the SPICE model is used And Gaussian process regression using SPICE simulator to perform Monte Carlo analysis and estimation on the new generation population to obtain the yield estimate;
步骤S106:依据所述电路性能指标和良率估计值采用进化算法对所述新一代种群进行进化得到下一代种群,记为第二代种群,其中每进化一次,种群的代数加1,;Step S106: Evolutionary algorithm is used to evolve the new-generation population according to the circuit performance index and the estimated value of yield rate to obtain the next-generation population, which is recorded as the second-generation population, where the generation number of the population is increased by 1 for each evolution;
步骤S107:根据预设的最大进化代数判断所述下一代种群进化是否结束,如果是,执行步骤S108,否则执行步骤S104;Step S107: judge whether the evolution of the next-generation population is over according to the preset maximum evolutionary number, if yes, execute step S108, otherwise execute step S104;
步骤S108:生成当前种群对应的Pareto最佳解集,依据Pareto最佳解集进行决策并验证。Step S108: Generate a Pareto optimal solution set corresponding to the current population, make a decision and verify it based on the Pareto optimal solution set.
在本申请上述实施例公开的上述方法中对电路进行优化的过程中,除了考虑传统的优化目标外,还把良率也作为优化目标之一,所以Pareto最佳解集上的良率也能够满足预设要求。同时,在优化过程中采用蒙特卡罗与高斯过程回归(GPR)相结合,加快良率的评估。In the process of optimizing the circuit in the above-mentioned method disclosed in the above-mentioned embodiments of the present application, in addition to considering the traditional optimization objectives, the yield rate is also taken as one of the optimization objectives, so the yield rate on the Pareto optimal solution set can also be Meet preset requirements. At the same time, the combination of Monte Carlo and Gaussian Process Regression (GPR) is used in the optimization process to speed up the evaluation of yield.
可以理解的是,在本申请上述实施例公开的方法中,步骤S105中“所述采用SPICE模型和高斯过程回归利用SPICE仿真器对新一代种群进行蒙特卡罗分析估算得到良率估计值”具体可以包括:It can be understood that, in the method disclosed in the above-mentioned embodiments of the present application, in step S105, "using the SPICE model and Gaussian process regression to use the SPICE simulator to perform Monte Carlo analysis and estimation on the new generation population to obtain the estimated yield" specifically Can include:
获取当前种群的训练点集(Y,X),Y为种群中每个个体观测点的良率的观测值,X为种群中每个个体观测点;Obtain the training point set (Y, X) of the current population, Y is the observed value of the yield of each individual observation point in the population, X is each individual observation point in the population;
依据所述训练点集(Y,X)由公式(1)计算得到种群中每个个体的良率的待预测值y*的后验分布为
其中,所述公式(1)为:
上述实施例中利用蒙特卡罗结合GPR估计良率的推理过程可以描述如下:The reasoning process of using Monte Carlo in combination with GPR to estimate the yield in the above embodiment can be described as follows:
其中,为设计变量,y为良率的观测值,设良率观测值的先验分布为高斯分布为:Y~N(0,K(X,X))(3)in, is the design variable, y is the observed value of the yield rate, and the prior distribution of the observed value of the yield rate is Gaussian distribution: Y~N(0, K(X, X))(3)
其中Y=(y1,y2,…yn)T为种群中多个个体观测点上良率的观测值,良率的观测值Y和良率的待预测值y*的联合先验分布为:Where Y=(y 1 ,y 2 ,…y n ) T is multiple individual observation points in the population The observed value of the yield rate, the joint prior distribution of the observed value Y of the yield rate and the expected value y* of the yield rate is:
其中,K(X,X)为对称正定协方差矩阵,为种群中待预测个体的设计变量,矩阵元为种群中不同的待预测个体的设计变量之间的相关性。由(4)得到良率的待测值y*的后验分布为:
参见本申请上述实施例公开的模拟集成电路优化方法中,在种群进化过程中每一代中个体数是定值,由于训练点集(Y,X)中不断有新的个体加入,使得进化代数越大,需要加入的新训练点越少,因此需要进行蒙特卡罗分析的个体越少,进而预测的良率值越准确,这一过程使得进化到一定代后,几乎不需要新的训练点加入,也即不需要再进行蒙特卡罗分析,因而会加快进化算法。Referring to the analog integrated circuit optimization method disclosed in the above-mentioned embodiments of the present application, the number of individuals in each generation is a fixed value during the population evolution process, and since new individuals are constantly added to the training point set (Y, X), the evolutionary algebra is getting higher and higher. Larger, the fewer new training points need to be added, so the fewer individuals need to perform Monte Carlo analysis, and the more accurate the predicted yield value is, this process makes it almost unnecessary to add new training points after evolution to a certain generation , that is, there is no need for Monte Carlo analysis, which will speed up the evolutionary algorithm.
可以理解的是,针对于上述方法,本申请还公开了一种模拟集成电路优化系统,两者可相互借鉴。参见图2,本申请实施例公开的所述模拟集成电路优化系统,包括:It can be understood that, for the above method, the present application also discloses an analog integrated circuit optimization system, and the two can be used for reference. Referring to Fig. 2, the analog integrated circuit optimization system disclosed in the embodiment of the present application includes:
采集模块10,用于获取用户输入的初始电路网表和晶体管统计模型;The collection module 10 is used to obtain the initial circuit netlist and transistor statistical model input by the user;
分析模块20,用于依据所述初始电路网表和晶体管统计模型分析得到设计变量、优化目标及约束条件;The analysis module 20 is used to analyze and obtain design variables, optimization objectives and constraints according to the initial circuit netlist and transistor statistical model;
种群生成模块30,用于依据所述设计变量的范围随机产生初始种群;A population generation module 30, configured to randomly generate an initial population according to the scope of the design variables;
第一进化模块40,用于更改所述设计变量,依据更改后的所述设计变量生成所述初始种群中每个个体对应的电路网表,所述电路网表代表新一代种群;The first evolution module 40 is configured to change the design variable, and generate a circuit netlist corresponding to each individual in the initial population according to the modified design variable, and the circuit netlist represents a new generation population;
仿真模块50,用于通过采用电路级模拟程序对所述新一代种群进行仿真,得到所述新一代种群中各个个体的电路性能指标,所述采用SPICE模型和高斯过程回归利用SPICE仿真器对新一代种群进行蒙特卡罗分析估算得到良率估计值,所述良率估计值包括种群中每个个体观测点上良率的待预测值;The simulation module 50 is used to simulate the new-generation population by using a circuit-level simulation program to obtain the circuit performance index of each individual in the new-generation population, and the SPICE model and Gaussian process regression are used to simulate the new generation population using a SPICE simulator. Performing Monte Carlo analysis and estimation on the first-generation population to obtain an estimated yield value, the estimated yield rate includes the expected value of the yield rate at each individual observation point in the population;
第二进化模块60,用于依据所述电路性能指标和良率估计值采用进化算法对所述新一代种群进行进化得到下一代种群;The second evolution module 60 is used to evolve the new-generation population by using an evolutionary algorithm according to the circuit performance index and the estimated yield value to obtain the next-generation population;
验证决策模块70,用于根据预设的最大进化代数判断进化是否结束,如果是,生成当前种群对应的Pareto最佳解集,依据Pareto最佳解集进行决策并验证,如果否,更改所述设计变量,依据更改后的所述设计变量生成所述初始种群中每个个体对应的电路网表,所述电路网表代表新一代种群,直至生成当前种群对应的Pareto最佳解集,并依据Pareto最佳解集进行决策并验证为止。The verification decision module 70 is used to judge whether the evolution is over according to the preset maximum evolution algebra, if yes, generate the Pareto optimal solution set corresponding to the current population, make a decision and verify it according to the Pareto optimal solution set, if not, change the Design variables, generate a circuit netlist corresponding to each individual in the initial population according to the modified design variables, the circuit netlist represents a new generation of population, until the Pareto optimal solution set corresponding to the current population is generated, and according to The Pareto optimal solution set is used for decision-making and verification.
与上述方法相对应,所述仿真模块50包括:Corresponding to the above method, the simulation module 50 includes:
良率计算单元51,所述良率计算单元51用于获取当前种群的训练点集(Y,X),Y为种群中每个个体观测点的良率的观测值,X为种群中每个个体观测点;Yield calculation unit 51, the yield calculation unit 51 is used to obtain the training point set (Y, X) of the current population, Y is the observed value of the yield of each individual observation point in the population, and X is the observation value of each individual observation point in the population. individual observation points;
依据所述训练点集(Y,X)由公式一计算得到良率的待预测值y*的后验分布为
其中,所述公式一为:
与上述方法相对应,所述仿真模块50还可以包括:Corresponding to the above method, the simulation module 50 may also include:
训练点集选取模块52,所述训练点集选取模块52用于判断当前种群为第几代种群;当所述种群为第一代种群时,在所述第一代种群的全部个体上进行蒙特卡罗分析,所述第一代种群中的全部个体为当第一代种群的训练点集,将所述第一代种群的训练点集作为当前种群的训练点集(Y,X);当所述种群为第Z代种群时,以第Z-1代种群的全部个体作为当前种群的训练点集(Y,X)。Training point set selection module 52, the training point set selection module 52 is used to judge which generation population the current population is; when the population is the first generation population, perform Monte Carlo on all individuals of the first generation population Caro analysis, all individuals in the first-generation population are the training point sets of the first-generation population, and the training point sets of the first-generation population are used as the training point sets (Y, X) of the current population; when When the population is the Z generation population, all the individuals of the Z-1 generation population are used as the training point set (Y, X) of the current population.
本说明书中各个实施例采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似部分互相参见即可。Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.
对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下,在其它实施例中实现。因此,本发明将不会被限制于本文所示的这些实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
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Effective date of registration: 20190116 Address after: 266101 Songling Road 169, Laoshan District, Qingdao City, Shandong Province Applicant after: Zhongke Xinyun Microelectronics Technology Co.,Ltd. Address before: 100029 Microelectronics Institute, Chinese Academy of Sciences, 3 north earth road, Chaoyang District, Beijing Applicant before: Institute of Microelectronics of the Chinese Academy of Sciences |