CN109657364A - A method of circuit optimization is realized using quick monte carlo method - Google Patents
A method of circuit optimization is realized using quick monte carlo method Download PDFInfo
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- CN109657364A CN109657364A CN201811580206.0A CN201811580206A CN109657364A CN 109657364 A CN109657364 A CN 109657364A CN 201811580206 A CN201811580206 A CN 201811580206A CN 109657364 A CN109657364 A CN 109657364A
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- monte carlo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
A method of realizing circuit optimization using quick monte carlo method, comprising the following steps: 1) circuit design specification is set；2) circuit optimization list is set；3) quick Monte Carlo analysis option is set and is analyzed；4) display optimization result.The present invention relies on quick Monte Carlo analysis, optimizes according to qualifications to circuit design, realizes circuit optimization while improving and verifying coverage rate.
Description
Technical field
The present invention relates to circuit design fields in eda tool, in particular to a kind of to be realized using quick monte carlo method
The method of circuit optimization to realize that the fast reliability of circuit emulates, and provides circuit optimization scheme.
Background technique
With technique evolution, process deviation (process variation) becomes more significant, has seriously affected chip and has set
The quality and yield rate of meter.For the yield for guaranteeing design, Monte Carlo (Monte Carlo) analysis is had become in design verification
It must link.However, traditional Monte Carlo analysis method needs a large amount of emulation sampling to statistically analyze, but emulate
Process it is too slow, if it is desired to achieve the effect that optimize circuit, it will consumption longer time, iteration cycle is longer, and designer is often
Can't wait, can only fetching portion as a result, verifying coverage rate do not reach requirement, be less able to achieve better optimization.
In the design for being similar to operational amplifier, generally require to roll over these parameters of gain, bandwidth, phase margin and power consumption
Middle optimization.In traditional design verification, often due to verifying can not cover and take and sacrifice some power consumption indexs to expire comprehensively
The gain of sufficient operational amplifier, bandwidth, the demand of PM can at least guarantee that the performance of operational amplifier is to meet system need in this way
It asks.But for some characteristic occasions, for example IoT is applied, and power consumption requirements are just more stringent, the increase of power consumption be equally system without
Method receives.
Based on the above circumstances, the present invention comes into being, and quick Monte Carlo (Fast Monte Carlo) is relied on to analyze, according to
Circuit design is optimized according to qualifications, realizes circuit optimization while improving and verifying coverage rate.
Summary of the invention
In order to solve the shortcomings of the prior art, quick Monte Carlo side is utilized the purpose of the present invention is to provide a kind of
The method that method realizes circuit optimization, iteration generate the device of one group of quick Monte Carlo analysis result, coincident circuit design specification
Parameter realizes circuit optimization while improving verifying coverage rate, improves the quality and yield rate of chip design.
To achieve the above object, the method provided by the invention for realizing circuit optimization using quick monte carlo method, packet
Include following steps:
1) circuit design specification is set；
2) circuit optimization list is set；
3) quick Monte Carlo analysis option is set and is analyzed；
4) display optimization result.
Further, the circuit design specification includes bandwidth, gain, phase margin and the metal-oxide-semiconductor in operational amplifier
Electric current.
Further, circuit optimization list is set described in step 2, is the influence degree according to device to circuit performance, if
Circuits optimize list.
Further, the step of quick Monte Carlo analysis option is set described in step 3), including, 3 sigma of setting are marked
It is quasi-；Calculate process and mismatch probability-distribution function.
Further, the step 3) carries out quick Monte Carlo analysis, includes the following steps,
Carry out Trend judgement, and the relationship of the Monte Carlo factor in analysis model and the trend；
Judge that the Monte Carlo factor is biased to some direction and design can be made to more tend to circuit design specification or further off circuit design
Specification；
The specific factor is selected by eda tool and carries out circuit analysis, to accelerate entire optimization process.
To achieve the above object, the present invention also provides a kind of computer readable storage mediums, are stored thereon with computer and refer to
It enables, the computer instruction executes the step of the above-mentioned method that circuit optimization is realized using quick monte carlo method when running
Suddenly.
The present invention provides the option of setting circuit design specification, circuit optimization device list, and quick Monte Carlo analysis is set
Option is set, Monte Carlo simulation is carried out to design according to quick monte carlo method, and analyze simulation result and circuit design rule
Relationship between lattice, optimizes the device of circuit optimization device list, and iteration generates one group of quick Monte Carlo analysis result and meets
The device parameters of circuit design specification realize circuit optimization while improving verifying coverage rate, improve the matter of chip design
Amount and yield rate.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, and with it is of the invention
Embodiment together, is used to explain the present invention, and is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the flow chart of the method according to the present invention that circuit optimization is realized using quick monte carlo method；
Fig. 2 is the operation amplifier circuit schematic diagram according to embodiments of the present invention；
Fig. 3 is the optimization function interface schematic diagram according to embodiments of the present invention；
Fig. 4 is the optimum results schematic diagram according to embodiments of the present invention.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, it should be understood that preferred reality described herein
Apply example only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.
Fig. 1 is the flow chart of the method according to the present invention that circuit optimization is realized using quick monte carlo method, below
Fig. 1 will be referred to, the method for the invention for realizing circuit optimization using quick monte carlo method will be described in detail.
Firstly, according to the type of circuit, circuit design specification is arranged in step 101.By taking operation amplifier circuit as an example,
Fig. 2 is the operation amplifier circuit schematic diagram according to embodiments of the present invention, is carried out to operation amplifier circuit shown in Fig. 2
AC is analyzed, bandwidth, gain, phase margin in available operational amplifier.Fig. 3 is according to the excellent of embodiments of the present invention
Change function interface schematic diagram, these circuit design specifications can be set in the region specification shown in Fig. 3, while
It can detecte such as the electric current on M5 pipe and given threshold.
From figure 3, it can be seen that the region specification is circuit design specification setting area, successively set
Bandwidth, gain, phase margin and M5 tube current design specification.
Circuit optimization list is set according to device to circuit performance influence degree in step 102.
Influencing significant device for each performance of operational amplifier in Fig. 2 is this 4 metal-oxide-semiconductors of M1, M2, M3, M4, then
Only these devices can be optimized, other devices, which can not be done, to be optimized, and the benefit set in this way is the meter for reducing eda tool
Calculate complexity.As shown in figure 3, the region Optimization Device List is setting circuit optimization device list region,
Being set optimised devices list is M1, M2, M3, M4.
Quick Monte Carlo analysis option is set, quick Monte Carlo analysis is carried out according to circuit technology in step 103.
Quick Monte Carlo analysis is foundation front ten several times or tens times is analyzed, carries out a Trend judgement, and divide
Analyse model (model) in the Monte Carlo factor and these trend relationship, so as to judge the Monte Carlo factor toward some
Direction can make design be biased to more tend to circuit design specification or further off circuit design specification, then pass through eda tool partially
Some specific factors can be selected and carry out circuit analysis, to accelerate entire optimization process.
The region Fast Monte Carlo is exactly quick Monte Carlo analysis setting regions, as shown in figure 3, setting 3
The standard of sigma, while calculating process and mismatch probability-distribution function (distribution function is present in technique information).
In step 104, display optimization result.
After the completion of entire optimization process operation, circuit can provide the circuit devcie size after an optimization.Fig. 4 is according to this
The optimum results schematic diagram of the embodiment of invention, as shown in figure 4, in Optimization Device List
The column of optimized value mono- are exactly according to the device size after this analysis optimization.
User can start the function of method of the invention according to demand in eda tool: setting circuit design specification
Option is arranged circuit optimization device list, quick Monte Carlo analysis option is arranged, runs quick Monte Carlo analysis, and according to
The circuit devcie size after optimization is provided according to circuit design specification.
The present invention also provides a kind of computer readable storage mediums, are stored thereon with computer instruction, the computer
The step of a kind of above-mentioned method that circuit optimization is realized using quick monte carlo method is executed when instruction operation, described one kind
Using the method that quick monte carlo method realizes circuit optimization referring to the introduction of preceding sections, repeat no more.
Those of ordinary skill in the art will appreciate that: the foregoing is only a preferred embodiment of the present invention, and does not have to
In the limitation present invention, although the present invention is described in detail referring to the foregoing embodiments, for those skilled in the art
For, still can to foregoing embodiments record technical solution modify, or to part of technical characteristic into
Row equivalent replacement.All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should all include
Within protection scope of the present invention.
Claims (6)
1. a kind of method for realizing circuit optimization using quick monte carlo method, which comprises the following steps:
1) circuit design specification is set；
2) circuit optimization list is set；
3) quick Monte Carlo analysis option is set and is analyzed；
4) display optimization result.
2. the method according to claim 1 for realizing circuit optimization using quick monte carlo method, which is characterized in that institute
Circuit design specification is stated, including, bandwidth, gain, phase margin and metal-oxide-semiconductor electric current in operational amplifier.
3. the method according to claim 1 for realizing circuit optimization using quick monte carlo method, which is characterized in that step
Rapid 2) the described setting circuit optimization list, is the influence degree according to device to circuit performance, and circuit optimization list is arranged.
4. the method according to claim 1 for realizing circuit optimization using quick monte carlo method, which is characterized in that step
The step of rapid 3) setting quick Monte Carlo analysis option, including, 3 sigma standards are set；Calculate process and
Mismatch probability-distribution function.
5. the method according to claim 1 for realizing circuit optimization using quick monte carlo method, which is characterized in that institute
It states step 3) and carries out quick Monte Carlo analysis, include the following steps,
Carry out Trend judgement, and the relationship of the Monte Carlo factor in analysis model and the trend；
Judge that the Monte Carlo factor is biased to some direction and design can be made to more tend to circuit design specification or further off circuit design
Specification；
The specific factor is selected by eda tool and carries out circuit analysis, to accelerate entire optimization process.
6. a kind of computer readable storage medium, is stored thereon with computer instruction, which is characterized in that the computer instruction fortune
Perform claim requires the step of 1 to 5 described in any item methods that circuit optimization is realized using quick monte carlo method when row.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111767672A (en) * | 2020-06-29 | 2020-10-13 | 重庆邮电大学 | Lithium battery abnormal working condition data self-organizing enhancement method based on Monte Carlo method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103559369A (en) * | 2013-09-14 | 2014-02-05 | 西安电子科技大学 | Circuit yield estimation method based on CAD (computer aided design) Monte Carlo analysis |
| CN103955579A (en) * | 2014-04-28 | 2014-07-30 | 天津大学仁爱学院 | Simulation/radio frequency integrated circuit design method based on SPICE software |
| US8954910B1 (en) * | 2013-03-14 | 2015-02-10 | Cadence Design Systems, Inc. | Device mismatch contribution computation with nonlinear effects |
| US8954908B1 (en) * | 2013-07-10 | 2015-02-10 | Cadence Design Systems, Inc. | Fast monte carlo statistical analysis using threshold voltage modeling |
| CN105303008A (en) * | 2015-12-03 | 2016-02-03 | 中国科学院微电子研究所 | Method and system for optimizing analogue integrated circuit |
-
2018
- 2018-12-24 CN CN201811580206.0A patent/CN109657364A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8954910B1 (en) * | 2013-03-14 | 2015-02-10 | Cadence Design Systems, Inc. | Device mismatch contribution computation with nonlinear effects |
| US8954908B1 (en) * | 2013-07-10 | 2015-02-10 | Cadence Design Systems, Inc. | Fast monte carlo statistical analysis using threshold voltage modeling |
| CN103559369A (en) * | 2013-09-14 | 2014-02-05 | 西安电子科技大学 | Circuit yield estimation method based on CAD (computer aided design) Monte Carlo analysis |
| CN103955579A (en) * | 2014-04-28 | 2014-07-30 | 天津大学仁爱学院 | Simulation/radio frequency integrated circuit design method based on SPICE software |
| CN105303008A (en) * | 2015-12-03 | 2016-02-03 | 中国科学院微电子研究所 | Method and system for optimizing analogue integrated circuit |
Non-Patent Citations (3)
| Title |
|---|
| MARITIME2: "全定制模拟基础电路设计流程", 《HTTP://WWW.DOC88.COM/P-1406364794633.HTML》 * |
| 严文娟 等: "《基于OrCAD的电子电路分析与实践教程》", 30 September 2011 * |
| 谭阳红: "《基于OrCAD16.3的电子电路分析与设计》", 31 October 2011 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111767672A (en) * | 2020-06-29 | 2020-10-13 | 重庆邮电大学 | Lithium battery abnormal working condition data self-organizing enhancement method based on Monte Carlo method |
| CN111767672B (en) * | 2020-06-29 | 2023-10-20 | 重庆邮电大学 | Monte Carlo method-based lithium battery abnormal working condition data self-organizing enhancement method |
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Application publication date: 20190419 |