CN110738014B - Method for determining key process fluctuation in time sequence circuit statistical analysis - Google Patents
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Abstract
The invention discloses a key process fluctuation determining method in time sequence circuit statistical analysis, which comprises the steps of firstly defining reference working conditions, and solving reference weights of all process fluctuations of all units under the reference working conditions on the basis of multiple linear regression, wherein the working conditions at least comprise voltage, temperature, input conversion time and output capacitance, and the weights are defined as the influence degree of the process fluctuations on unit/circuit delay; constructing a second-order model among the process fluctuation weight, the reference weight and the working condition deviation by utilizing a plurality of groups of randomly generated process fluctuation weights under different working conditions and various conditions; and working conditions of each unit are obtained through single circuit simulation, and corresponding process fluctuation weights are obtained through a second-order model. And the rapid dimension reduction of the process fluctuation parameters of the circuit can be realized by taking the process fluctuation corresponding to the larger weight as a key parameter.
Description
Technical Field
The invention belongs to the field of integrated circuit design automation (EDA), and particularly relates to a method for determining key process fluctuation in time sequence circuit statistical analysis.
Background
As the size of CMOS devices in nanoscale technology nodes decreases, process fluctuations in the design become increasingly difficult to control. Process fluctuations are divided into local fluctuations and global fluctuations, which refer to changes in operating conditions, such as supply voltage and temperature changes. Local fluctuations refer to device process variations, such as threshold voltage (V) th ) And gate length (L) d ) And so on, the presence of these fluctuations significantly increases the uncertainty in circuit performance, increasing the difficulty of accurate analysis. Although the deterministic static timing analysis method based on process corners may capture global fluctuations well, the method does not adequately account for the effects of local fluctuations. Therefore, researchers usually define the process fluctuation as a random variable, and analyze the delay distribution of the circuit under the influence of the process fluctuation through SPICE combined with Monte Carlo (MC) simulation, so as to obtain the circuit delay value under the yield driving. Although the simulation method sufficiently considers global fluctuation as well as local fluctuation, the simulation time of the method is too long. Many researches establishModels of the relationship between circuit delay and process fluctuations are used instead of time-consuming SPICE simulations, or importance sampling is used to accelerate MC analysis. However, taking the NMOS of the SMIC 28nm process library as an example, there are 8 local fluctuations, which are respectively threshold voltage, channel length, channel width, oxide layer thickness, carrier mobility, barrier lowering factor, carrier saturation velocity and threshold voltage bias, for any one circuit, the modeling parameters of the required process fluctuation will be up to thousands, and then considering the nonlinear relationship between the process fluctuation and the circuit delay, the modeling complexity will be further increased. Therefore, dimensionality reduction of process fluctuations is one of the effective methods to reduce computational complexity.
The current mainstream dimension reduction methods mainly include Principal Component Analysis (PCA) and Independent Component Analysis (ICA). PCA uses an orthogonal transform to convert a set of observations that may be correlated variables into a set of values for linearly uncorrelated variables called principal components. ICA converts non-Gaussian associated process fluctuation parameters into a series of statistically independent parameters through linear conversion, unlike PCA, ICA is mainly used for processing non-Gaussian distributed parameters, but PCA and ICA only consider the relation between input parameters when performing parameter screening, and ignore the relation between the input parameters and output results. Hotelling proposes a Classical Correlation Analysis (CCA) that considers the relationship between input and output, i.e. between input parameters and circuit delays, but the data set used for training and fitting is still obtained by SPICE and MC simulation analysis. Because the timing diagram of the circuit is iterated step by step to transmit the delay value, the value of the critical process fluctuation is changed after the unit composing the circuit is changed, and the time-consuming training and fitting processes need to be repeated, so that the dimensionality reduction is meaningless.
Disclosure of Invention
The invention aims to: the energy efficiency advantage of the near-threshold circuit design is widely concerned, however, with the reduction of the circuit size, the number of local fluctuations in the circuit timing analysis is sharply increased along with the increase of the circuit depth, so that the result of the delay analysis is more and more inaccurate, and the traditional timing analysis method based on-chip fluctuations is not applicable any more. Despite the large number of fluctuating parameters, the process fluctuations that actually have a large impact on the circuit delay output are very limited. The current dimension reduction method does not study the relation between the working condition and the time delay of each specific standard unit. Since the circuit is designed iteratively, any circuit adjustment will result in the change of the working condition of the unit in the circuit, and these time-consuming training and analysis fitting needs to be repeated, which makes the dimensionality reduction meaningless. The invention provides a method for determining key process fluctuation in time sequence circuit statistical analysis, which aims to solve the technical problem.
The technical scheme is as follows: in order to realize the purpose of the invention, the technical scheme adopted by the invention is as follows: a method for determining key process fluctuation in time sequence circuit statistical analysis comprises the following steps:
(1) The invention firstly establishes a process fluctuation set X = { X } through linear regression 1 ，x 2 ，...，x p With a reference delay T ref The first order linear functional relationship between them is expressed as formula (1).
The formula (1) is described as follows: setting reference operating conditions S 0 ，L 0 ，V 0 ，T 0 Extraction of the delay profiles T of all standard cells under reference working conditions by SPICE and Monte Carlo (MC) simulations ref Obtaining the process fluctuation x of each unit through multivariate linear regression i Influencing the cell delay weight w i，ref W from the formula i，ref And (3) calculating a reference value of the influence weight of the process fluctuation of each unit on the unit under any working condition based on the weight obtained under the reference condition in the step (2).
Taking the SMIC 28nm process library as an example, the process fluctuation set x of each transistor includes 8 process fluctuations in total, including threshold voltage, channel length, channel width, oxide layer thickness, carrier mobility, barrier lowering factor, carrier saturation velocity, and threshold voltage bias. There are thus 16 process fluctuations for an inverter cell with 2 transistors, and 32 process fluctuations for an and/or cell with 4 transistors. For ease of description, the subsequent analysis assumes that there are p process fluctuations for the standard cell. MC simulation will be to the process waveMultiple times of sampling are carried out, each time of sampling obtains a group of process fluctuations X, and a standard unit delay value T under the process fluctuations is obtained through SPICE simulation ref . If the MC simulation sampling times are set to 10000 times, 10000 sets of process fluctuation and unit delay exist, and the standard unit delay finally presents a distribution form. Through a regress command of MATLAB, all process fluctuations of MC sampling are taken as input, and standard unit delays T corresponding to all process fluctuations are taken as input ref For output, performing multiple linear regression to obtain fluctuation x i Coefficient w of i,ref I =1,2.., p. Due to w i,ref The larger the process fluctuation x i The greater the effect on the delay, and therefore w i，ref As reference operating condition S 0 ，L 0 ，V 0 ，T 0 The process fluctuation weight value under }, called the reference weight, ε is the random error with mean value of zero:
T ref ＝∑w i,ref x i +ε (1)
(2) Setting N working conditions (S, L, V, T) j J =1, 2.. N, S is the input conversion time, L is the output load, V is the operating voltage, and T is the temperature. According to the method for calculating the process fluctuation weight in the step (1), a functional relation between the standard unit delay and the process fluctuation is constructed according to a formula (2), and the process fluctuation x under the j group of working conditions is obtained through multiple linear regression i Weight w to standard cell delay distribution i,j 。
Setting N random working condition scenes, calculating the process fluctuation weight of each standard unit under each working condition, and changing the working conditions { S, L, V, T } of each unit j And is combined with { S 0 ，L 0 ，V 0 ，T 0 Calculating deviation values of operating conditions, { Δ S, Δ L, Δ V, Δ T }, in comparison with the calculated deviation values j Wherein j =1, 2.. And N is the j-th group of working conditions. Through simulation of SPICE and MC, the working conditions (S, L, V, T) of the standard unit are obtained j Delay profile of lower, noted as T j . The relationship between the process fluctuation and the unit delay is shown in formula (2), and the calculation method of the reference weight in the step (1) is compared with the calculation method of the reference weight in the step (1), and N groups of working strips are processedPerforming multiple linear regression on the workpiece to obtain process fluctuation x under each working condition i Delay distribution T to unit j Influence weight w of i,j 。
T j ＝∑w i,j x i +ε (2)
(3) Setting the deviation values [ Delta S, delta L, delta V, delta T of the working conditions in the step (2) for each process fluctuation of the standard cells] j Sum deviation value squared [ Delta S [ ] 2 ，ΔL 2 ，ΔV 2 ，ΔT 2 ] j As independent variable, with the process fluctuation weight w under the corresponding working condition i，j Performing multiple regression to obtain influence coefficient vector P of working condition deviation on weight i And Q i . And (4) forming a second-order model of the fluctuation weight of each process caused by the working condition change of each standard unit, as shown in the formula (3).
Specifically, for each process fluctuation x i Constructing its reference weight w i，ref With weights w under different operating conditions i，j The quadratic function relation between them, i.e. the second order model, is shown in equation (3). The formula (3) is specifically described as follows: [ Delta S, [ Delta L, [ Delta V, [ Delta T ]] j And [ Delta S ] 2 ，ΔL 2 ，ΔV 2 ，ΔT 2 ] j Primary and secondary terms, respectively, of the deviation of the operating conditions, vector P i And Q i For deviation of operating conditions to weight w i，j The influence coefficient of (c). Taking the primary term and the secondary term of the deviation value of the N groups of working conditions as independent variables, and taking the weight w under the N groups of working conditions i，j As a dependent variable, the formula (3) is subjected to multivariate regression by MATLAB to obtain a vector P i And Q i . It is noted that P i 、Q i Is a weighted regression for each process fluctuation in each standard cell, so for an inverter cell with 16 process fluctuations, 16 different sets of P are calculated i And Q i I =1,2, ·,16; for an OR gate with 32 process fluctuations, 32 different sets of P need to be calculated i And Q i I =1, 2. FIG. 2 is a graph of process fluctuation weights built for a given standard cell libraryObtaining P of all standard cells by using an algorithm flow chart in relation to deviation of working conditions i 、Q i And then, carrying out process fluctuation weight analysis on the standard unit under any working condition.
(4) And (4) extracting the working condition deviation value of each standard cell in the circuit through SPICE simulation, and obtaining the weight of each process fluctuation of the standard cells to the cell delay through the second-order model constructed in the step (3).
For a circuit with M standard cells, the deviation values { Δ S, Δ L, Δ V, Δ T } of the operating conditions of each standard cell can be obtained by SPICE simulation m . Using the first and second terms of the deviation of the operating conditions of each standard cell and the coefficient vector P of each standard cell obtained in step S03 i And Q i The weight w of each process fluctuation in each unit can be found by the formula (4) m，i M denotes the mth standard cell in the circuit, and i denotes the ith process fluctuation of the standard cell m. Thus, for any circuit, P for all standard cells is already available i And Q i Therefore, the deviation of the working conditions of each standard cell is extracted by only one SPICE simulation, the process fluctuation weights in all the standard cells in the circuit can be obtained through the formula (4), and the steps (1) to (3) are not required to be repeated:
however, the weight w m,i The effect of this process fluctuation on circuit delay cannot be directly represented. If the delay fluctuation of a standard unit is smaller than the delay fluctuation of other standard units, even if the weight of a process fluctuation obtained by independently analyzing the unit is larger, the influence of the process fluctuation on the circuit delay is smaller for the whole circuit. Therefore, in order to characterize the effect of standard cell process fluctuations on circuit delay fluctuations, it is necessary toThe cell delay profile and the circuit delay profile are analyzed.
(5) Calculating the standard deviation sigma of each unit delay distribution m And (4) obtaining the weight of the unit-level process fluctuation to the unit delay according to the step (4), and multiplying the weight of the unit-level process fluctuation and the weight of the circuit delay to the circuit process fluctuation.
First, a standard cell delay profile is analyzed, assuming that the circuit includes M cells, wherein the M-th cell is taken as an example, the cell delay profile is T m ，μ m And σ m Respectively representing the mean value and the standard deviation of the cell delay distribution, as shown in formula (5), wherein Samples is the simulation number of the MC, t m,n Is the delay value obtained by the mth unit in the nth MC simulation:
if there are p process fluctuations in the m-th unit, w m,i Represents the process fluctuation x of the m-th cell m,i I =1,2, p, delay t for cell m m Normalizing to obtain y m As shown in equation (6):
for the delay profile of the whole circuit, t is the delay profile of the circuit sum Equal to the sum of the standard cell delay distributions:
in combination with equation (6), the relationship between the normalized circuit delay and the process fluctuation of each unit can be obtained, as shown in equation (7). Each process fluctuation x of standard cell m in the circuit m,i Weight of influence on delay distribution of whole circuit and weight w of unit process fluctuation m,i Standard deviation sigma of unit delay distribution m And the standard deviation sigma of the circuit delay profile sum It is related. Due to the standard deviation sigma of the circuit delay sum All process fluctuation weights in the circuit are acted on simultaneously, so that the influence weight of each process fluctuation on the circuit delay does not need to be considered sum But can be determined by the weight w m,i And standard deviation σ m Is characterized by the product of (a), i.e. σ m *w m,i And thus, the quantification work of the fluctuation weight of each process in the circuit is completed:
obtaining the weight [ sigma ] of the influence of each process fluctuation on the whole circuit delay m *w m，i And sorting product results from large to small after M, and then according to a screening threshold defined by a user, only if the product result of the process fluctuation is higher than the screening threshold, reserving the process fluctuation corresponding to the reserved weight, wherein the process fluctuation is the key process fluctuation after final screening.
Has the beneficial effects that: compared with the prior art, the technical scheme of the invention has the following beneficial technical effects:
(1) A second-order process fluctuation weight model is provided, which takes into account the influence of different working conditions on the process fluctuation weight value.
(2) A mapping method is provided, for a sequential circuit, the weight of the process fluctuation of each unit forming the circuit can be adjusted and corrected, so that the weight value of each process fluctuation is in accordance with the actual condition of the circuit.
(3) The parameter dimension reduction method can be applied to different dimensional scenes. In the invention, the weight value of each process fluctuation under different working conditions can be calculated only by quantizing the reference weight of each standard unit process fluctuation under the reference working condition. And then, quickly and effectively solving the weight value of the process fluctuation of the whole circuit according to the unit-level weight through a second-order model. And finally, selecting the process fluctuation corresponding to the weight higher than the threshold value as the finally selected key process fluctuation according to the screening threshold value.
(4) The method is composed of a unit-level weight model and a circuit-level weight mapping method. The method realizes the quantification of the influence degree of circuit-level process fluctuation of the time sequence circuit on the time delay, and avoids repeated training and fitting processes. The proposed method of the present invention was validated under the ISCAS85 and ISCAS89 reference circuits. If the screening threshold is set to be 20%, local process fluctuation with the weight value of the first 20% is selected as a key process fluctuation parameter, and compared with the key process fluctuation parameter screened out by directly carrying out SPICE simulation experiments on the whole circuit, the method only causes 0.06% of average error and 0.56% of delay distribution standard deviation error.
Drawings
FIG. 1 is an overview of the algorithm as a whole;
FIG. 2 is a flow chart of an algorithm for establishing the relationship between the fluctuation parameters and the operating conditions for a given standard cell library build;
FIG. 3 is an overall flow chart of timing analysis of a timing circuit using the dimension reduction algorithm of the present invention.
Detailed Description
The invention will be further explained with reference to the drawings. Fig. 1 is an overall overview of the entire algorithm.
Since all circuits are composed of cells, the present invention first analyzes the standard cells constituting the circuits. The delay of a standard cell is determined by the following aspects: operating voltage, input switching time, output load capacitance and temperature, so that first a reference operating condition is set, for example the input switching time S 0 10ps, output load L 0 0.4fF, operating voltage V 0 0.8V, temperature T 0 At 25 deg.c, the reference operating conditions can be freely set as desired.
(1) The invention firstly establishes a process fluctuation set X = { X } through linear regression 1 ，x 2 ，...，x p With a reference delay T ref The first order linear function relationship between them, expressed as formula (1).
The formula (1) is described as follows: setting reference operating conditions S 0 ，L 0 ，V 0 ，T 0 Is obtained bySPICE and Monte Carlo (MC) simulations extract the delay profiles T of all standard cells under reference working conditions ref Obtaining the process fluctuation x of each unit through multivariate linear regression i Influence weight w on cell delay i,ref W from the formula i，ref And (3) calculating a reference value of the influence weight of the process fluctuation of each unit on the unit under any working condition based on the weight obtained under the reference condition in the step (2).
Taking the SMIC 28nm process library as an example, the process fluctuation set X of each transistor includes 8 process fluctuations in total, including threshold voltage, channel length, channel width, oxide layer thickness, carrier mobility, barrier lowering factor, carrier saturation velocity, and threshold voltage bias. There are thus 16 process fluctuations for an inverter cell with 2 transistors, and 32 process fluctuations for an and/or cell with 4 transistors. For ease of description, the subsequent analysis assumes that there are p process fluctuations for the standard cell. The MC simulation carries out multiple sampling on the process fluctuation, each sampling obtains a group of process fluctuation X, and the standard unit delay value T under the process fluctuation is obtained through SPICE simulation ref . If the MC simulation sampling frequency is set to 10000 times, 10000 sets of process fluctuation and unit delay exist, and the standard unit delay finally presents a distribution form. Taking all process fluctuations of MC sampling as input and standard unit delay T corresponding to all process fluctuations through a regression command of MATLAB ref For output, performing multiple linear regression to obtain fluctuation x i Coefficient w of i,ref I =1,2.., p. Due to w i,ref The larger the process fluctuation x i The greater the impact on the delay, and therefore w will be i,ref As reference operating condition S 0 ，L 0 ，V 0 ，T 0 The process fluctuation weight value under (c), called the reference weight,. Epsilon. Is the random error with mean value of zero:
T ref ＝∑w i,ref x i +ε (1)
(2) Setting N working conditions (S, L, V, T) j J =1, 2.. N, S is the input conversion time, L is the output load, V isThe working voltage, T is the temperature. According to the method for calculating the process fluctuation weight in the step (1), a functional relation between the standard unit delay and the process fluctuation is constructed according to a formula (2), and the process fluctuation x under the j group of working conditions is obtained through multiple linear regression i Weight w to standard cell delay distribution i,j 。
Setting N random working condition scenes, calculating the process fluctuation weight of each standard unit under each working condition, and changing the working conditions { S, L, V, T } of each unit j And is combined with { S 0 ，L 0 ，V 0 ，T 0 In contrast, deviation values { Δ S, Δ L, Δ V, Δ T } of operating conditions are calculated j Wherein j =1, 2.. And N is the j-th group of working conditions. Through simulation of SPICE and MC, the working conditions (S, L, V, T) of the standard unit are obtained j Delay profile of lower, noted as T j . The relation between the process fluctuation and the unit delay is shown in a formula (2), and the process fluctuation x under each working condition is obtained by performing multiple linear regression on N groups of working conditions by analogy with the calculation method of the reference weight in the step (1) i Delay distribution T of pair units j Influence weight w of i，j 。
T j ＝∑w i，j x i +ε (2)
(3) Setting the deviation values [ Delta S, delta L, delta V, delta T of the working conditions in the step (2) for each process fluctuation of the standard cells] j Sum deviation value squared [ Delta S [ ] 2 ，ΔL 2 ，ΔV 2 ，ΔT 2 ] j As independent variable, with the process fluctuation weight w under the corresponding working condition i，j Performing multiple regression to obtain influence coefficient vector P of working condition deviation on weight i And Q i And forming a second-order model of the fluctuation weight of each standard unit working condition change to each process, as shown in formula (3).
Specifically, for each process fluctuation x i Constructing its reference weight w i，ref With weights w under different operating conditions i，j The quadratic function relation between them, i.e. the second order model, is shown in equation (3). The formula (3) is specifically described asThe following: [ Delta S, [ Delta L, [ Delta V, [ Delta T ]] j And [ Delta S ] 2 ，ΔL 2 ，ΔV 2 ，ΔT 2 ] j Primary and secondary terms, respectively, of deviation from operating conditions, vector P i And Q i For deviation of operating conditions to weight w i，j The influence coefficient of (c). Taking the primary term and the secondary term of the deviation values of the N groups of working conditions as independent variables, and taking the weight w under the N groups of working conditions i，j Performing multiple regression on formula (3) through MATLAB as dependent variable to obtain vector P i And Q i . It is noted that P i 、Q i Is a weighted regression for each process fluctuation in each standard cell, so for an inverter cell with 16 process fluctuations, 16 different sets of P are calculated i And Q i I =1,2, ·,16; for an OR gate with 32 process fluctuations, 32 different sets of P need to be calculated i And Q i I =1, 2. FIG. 2 is a flow chart of an algorithm for constructing a relationship between process fluctuation weight and deviation from operating conditions for a given standard cell library, where P is the number of all standard cells i 、Q i And then, carrying out process fluctuation weight analysis on the standard unit under any working condition.
(4) And (4) extracting the working condition deviation value of each standard cell in the circuit through SPICE simulation, and obtaining the weight of each process fluctuation of the standard cell to the cell delay through the second-order model constructed in the step (3).
For a circuit with M standard cells, the deviation values { Δ S, Δ L, Δ V, Δ T } of the operating conditions of each standard cell can be obtained by SPICE simulation m . Using the first and second terms of the deviation of the operating condition of each standard cell and the coefficient vector P of each standard cell obtained in step S03 i And Q i The weight w of each process fluctuation in each unit can be found by the formula (4) m，i M represents the mth standard cell in the circuit, i represents the standardThe ith process fluctuation of unit m. Thus, for any circuit, P for all standard cells is already available i And Q i Therefore, the working conditions of each standard cell are extracted by SPICE simulation only once, the process fluctuation weights in all the standard cells in the circuit can be obtained through the formula (4), and the steps (1) to (3) are not required to be repeated.
However, the weight w m，i The effect of this process fluctuation on circuit delay cannot be directly represented. If the delay fluctuation of a standard unit is smaller than the delay fluctuation of other standard units, even if the weight of a certain process fluctuation obtained by independently analyzing the unit is large, the influence of the process fluctuation on the circuit delay is small for the whole circuit. Therefore, in order to characterize the influence of standard cell process fluctuations on circuit delay fluctuations, analysis of cell delay profiles and circuit delay profiles is required.
(5) Calculating the standard deviation sigma of each unit delay distribution m And (5) obtaining the weight of the unit-level process fluctuation to the unit delay according to the step (4), and multiplying the weight of the unit-level process fluctuation to the weight of the circuit delay.
First, a standard cell delay profile is analyzed, assuming that the circuit includes M cells, wherein the M-th cell is taken as an example, the cell delay profile is T m ，μ m And σ m Respectively representing the mean value and the standard deviation of the cell delay distribution, as shown in formula (5), wherein Samples is the simulation number of the MC, t m,n Is the delay value obtained by the mth unit in the nth MC simulation:
if there are p process fluctuations in the m-th unit, w mm,i Represents the process fluctuation x of the m-th unit m,i I =1,2, p, the delay t for the unit m m Normalizing to obtain y m As shown in equation (6):
for the delay profile of the whole circuit, t is the delay profile of the circuit sum Equal to the sum of the standard cell delay distributions:
in combination with equation (6), the relationship between the normalized circuit delay and the process fluctuation of each unit can be obtained, as shown in equation (7). Each process fluctuation x of standard cell m in the circuit m,i Weight of influence on delay distribution of whole circuit and weight w of unit process fluctuation mn,i Standard deviation sigma of unit delay distribution m And the standard deviation sigma of the circuit delay profile sum It is related. Due to the standard deviation sigma of the circuit delay sum All process fluctuation weights in the circuit are acted at the same time, so that the influence weight of each process fluctuation on the circuit delay does not need to be considered sum But can be influenced by the weight w m,i Sum standard deviation σ m Is characterized by the product of (a), i.e. σ m *w m,i . Thus, the quantification work of the fluctuation weight of each process in the circuit is completed.
Obtaining the weight [ sigma ] of the influence of each process fluctuation on the whole circuit delay m *w m,i And sorting the product results from large to small after M, and then reserving the product results of the process fluctuation only when the product results are higher than the screening threshold according to the screening threshold defined by a user. The process fluctuation corresponding to these retained weights is the key process fluctuation after the final screening. FIG. 3 depicts the whole process of the process fluctuation parameter dimension reduction method proposed by the present invention.
Throughout the process, ISCAS85 and ISCAS89 benchmark test circuits were tested using the SMIC 28nm library. In order to simplify the modeling process and reduce the computational complexity, the invention only verifies a standard cell library consisting of 12 basic standard cells, and all test circuits are synthesized by the simplified standard cell library through a Synopsys design compiler tool to obtain a complete gate-level netlist of the test circuit. Generating a critical path netlist file of the test circuit through Synopsys PrimeTime, and simulating the critical circuit netlist through SPICE to obtain the working conditions of each standard unit in the netlist: input swing and output load.
Claims (4)
1. A method for determining critical process fluctuations in statistical analysis of sequential circuits, the method comprising the steps of:
s01: setting a reference working condition of a circuit standard unit and establishing a process fluctuation set, extracting delay distribution of all standard units under the reference working condition through simulation, calculating the relation between the delay distribution of the standard unit and each process fluctuation through multiple linear regression, obtaining the influence of each process fluctuation on the unit delay, and marking as a reference weight w i，ref ；
S02: setting N working conditions, wherein j =1, 2.. And N, and obtaining the process fluctuation x under the j set of working conditions through multiple linear regression according to the method for calculating the process fluctuation weight in the step S01 i Weight w to standard cell delay distribution i，j ；
S03: calculating the deviation of each working condition in the step S02 from the reference condition in the step S01, taking the working condition deviation value set in the step (2) as an independent variable, and taking the process fluctuation weight w under the corresponding working condition i，j Performing multiple regression as dependent variable to obtain w i，j And w i，ref A relation model of the working condition deviation value;
s04: obtaining the weight of each process fluctuation of the standard unit to the unit delay through the working condition deviation of each standard unit in the simulation extraction circuit and the relation model constructed by S03;
s05: calculating the standard deviation of the delay distribution of each unit, obtaining the weight of the process fluctuation to the unit delay according to S04, and multiplying the weight of the process fluctuation to the unit delay to obtain the weight of the circuit process fluctuation relative to the circuit delay;
s06: and (5) sequencing the weights of all the circuit process fluctuations calculated in the step (S05), setting a threshold value, and determining the key process fluctuations according to the threshold value.
2. The method of claim 1, wherein the operating conditions in steps S01 and S02 include voltage, temperature, input transition time, and output load capacitance.
3. The method of claim 1 or 2, wherein the method for determining the critical process variation in the statistical analysis of the sequential circuit comprises the following steps: when the product of the process fluctuation is higher than the threshold value, the process fluctuation is regarded as a critical process fluctuation.
4. The method of claim 1 or 2, wherein the set of process fluctuations comprises one or more of: threshold voltage, channel length, channel width, oxide layer thickness, carrier mobility, barrier lowering factor, carrier saturation velocity and threshold voltage bias.
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| CN106066919A (en) * | 2016-06-13 | 2016-11-02 | 中国科学院微电子研究所 | It is applied to the SSTA method of near/subthreshold value digital circuit |
| US10073934B1 (en) * | 2016-10-11 | 2018-09-11 | Cadence Design Systems, Inc. | Systems and methods for statistical static timing analysis |
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| CN101964003A (en) * | 2009-07-24 | 2011-02-02 | 复旦大学 | Method and device for analyzing reliability of integrated circuit |
| CN106066919A (en) * | 2016-06-13 | 2016-11-02 | 中国科学院微电子研究所 | It is applied to the SSTA method of near/subthreshold value digital circuit |
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