CN102289549A - Optimization method for analog integrated circuit - Google Patents

Optimization method for analog integrated circuit Download PDF

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Publication number
CN102289549A
CN102289549A CN201110229280XA CN201110229280A CN102289549A CN 102289549 A CN102289549 A CN 102289549A CN 201110229280X A CN201110229280X A CN 201110229280XA CN 201110229280 A CN201110229280 A CN 201110229280A CN 102289549 A CN102289549 A CN 102289549A
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posynomial
design
circuit
optimization
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李�亨
刘毅
曾真
董传盛
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Fudan University
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Fudan University
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Abstract

The invention belongs to the technical field of an integrated circuit design and particularly relates to an optimization method for an analog integrated circuit. The optimization method provided by the invention combines an optimization method based on formulas and an optimization method based on simulation; the performance parameters of the analog integrated circuit are expressed into positive term models about design variables, and an optimization design is carried out on the circuit by utilizing a geometric programming method; and furthermore, the positive term models in geometric programming problems are alternately corrected by utilizing an SPICE (simulation Program with Integrated Circuit) simulation result of a transistor level, thereby overcoming the defect of insufficient accuracy of the positive term models. In the method provided by the invention, the analog integrated circuit is optimized; the optimization accuracy of an SPICE level can be achieved in less computation time; and the problem that an existing method cannot give consideration to the optimization efficiency and the optimization accuracy is solved.

Description

A kind of Analogous Integrated Electronic Circuits optimization method
Technical field
The invention belongs to integrated circuit (IC) design or Computer-aided Design Technology field, be specifically related to a kind of Analogous Integrated Electronic Circuits optimization method.
Background technology
Along with integrated circuit (Integrated Circuit IC) the enters the SoC(SOC (system on a chip)) epoch, the market demand of composite signal integrated circuits is increasing.The numerical portion of mixed-signal IC can be by mature C AD(computer-aided design (CAD)) instrument and and design methodology realize efficiently; Yet the simulation part is still main by manual design, makes it become the bottleneck of SoC design.Therefore, the IC design field presses for the CAD software that exploitation is applicable to the Analogous Integrated Electronic Circuits design, wherein the most important thing is synthesis tool.
Since late 1980s, the comprehensive main flow approach of Analogous Integrated Electronic Circuits is based on the method for optimization, promptly with design objective as constraint condition, adopt numerical optimization technique (mathematical programming etc.) to come the performance of optimized circuit.This integrated approach based on optimization generally includes two main modular: circuit performance assessment models and mathematical optimization engine.The former measured the circuit performance of current design point in each step of optimizing process; The latter adjusts design parameter according to the circuit performance knowledge that obtains, to optimize the performance of circuit.
According to the difference of the circuit performance assessment models that is adopted, can be divided into two big classes based on the integrated approach of optimizing: based on the method (1) (2) of formula, and based on method of emulation (3) (4).Adopt simple formula model to come the performance of evaluation circuits based on equation, shape as
Figure 196575DEST_PATH_IMAGE001
(here
Figure 181848DEST_PATH_IMAGE002
The expression phase margin,
Figure 429290DEST_PATH_IMAGE003
,
Figure 936232DEST_PATH_IMAGE004
,
Figure 927322DEST_PATH_IMAGE005
Design variables such as the expression transistor is wide, long, bias current).Because the Performance Evaluation model is simple, and this explicit expression is easy to by the mathematical optimization programmed control, so these class methods have very high efficient.In recent years, some achievements in research find that the design object function of a large amount of Analogous Integrated Electronic Circuits and constraint condition can be expressed as (perhaps approximate representation is) posynomial (Posynomial) function about design parameter, therefore can adopt geometric programming (Geometric programming, GP) method comes circuit is optimized, and it has, and execution efficient is high, the characteristics (1) (2) of global optimization.Yet because simple formula model is difficult to accurately describe the circuit behavior of physics complexity, therefore the shortcoming based on the optimization method maximum of formula is the precision deficiency.
Corresponding with it, come the performance of evaluation circuits by the SPICE emulation (a kind of integrated circuit simulating instrument of industrial standard) of transistor level based on the optimization method of emulation.These class methods have the SPICE class precision as industrial standard, but owing to need carry out a large amount of SPICE emulation, they can bring great Computing burden.Typical case's representative of these class methods is DELIGHT.SPICE (3), and it is embedded into a SPICE emulator among the general optimum engine DELIGHT, carries out complete SPICE emulation in each step of optimizing iteration.DELIGHT.SPICE can only find the local optimum point, therefore is applicable to the circuit design that initial designs point is provided is carried out the part fine setting.Another one example based on emulation mode is ANACONDA (4), the behavior that it comes acquisition cuicuit with accurate SPICE emulation, and adopt evolution algorithm to seek optimum solution.ANACONDA can find globally optimal solution (being difficult to control in the reality) in theory, and supports parallel processing.Yet 50000-100000 SPICE emulation still can bring heavy computation burden altogether.
List of references
(1)?Hershenson?M,?Boyd?S,?Lee?T.?Optimal?design?of?a?cmos?op-amp?via?geometric?programming.?IEEE?Transactions?on?Computer-Aided?Design?of?Integrated?Circuits?and?Systems,?2001,?20(1):?1-21
(2)?Mandal?P,?Visvanathan?V.?CMOS?op-amp?sizing?using?a?geometric?programming?formulation.?IEEE?Transactions?on?Computer-Aided?Design?of?Integrated?Circuits?and?Systems,?2001,?20(1):?22-38
(3)?Nye?W,?Riley?D,?Sangiovanni-Vincentelli?A,?Tits?A.?Delight.spice:?an?optimization-based?system?for?the?design?of?integrated?circuits.?IEEE?Transactions?on?Computer-Aided?Design?of?Integrated?Circuits?and?Systems,?1988,?7(4):?501-519
(4)?Phelps?R,?Krasnicki?M,?Rutenbar?R?A,?et?al.?Anaconda:?Simulation-based?synthesis?of?analog?circuits?via?stochastic?patter?search.?IEEE?Transactions?on?Computer-Aided?Design?of?Integrated?Circuits?and?Systems,?2000,?19(6):?703-717.。
Summary of the invention
The objective of the invention is to overcome the problem that existing optimization method can't be taken into account precision and efficient simultaneously, proposing a kind of existing very high precision has very high efficiency Analogous Integrated Electronic Circuits optimization method again.
The Analogous Integrated Electronic Circuits optimization method that the present invention proposes combines based on equation and advantage based on simulation method: with the SPICE simulation result formula model of correcting circuit performance iteratively, to improve the precision based on equation.Use this method Analogous Integrated Electronic Circuits is optimized design, can in computing time seldom, reach the optimization precision of SPICE level.
The present invention is a kind of in conjunction with geometric programming (Geometric Programming GP) with the Analogous Integrated Electronic Circuits optimization method of model tuning (Model Modification), abbreviates MMGP(Model Modified Geometric Programming as).The framed structure of MMGP as shown in Figure 1, it realizes concrete steps following (as shown in Figure 2):
Step 1 is expressed as posynomial form about design parameter, i.e. initialization posynomial model with the objective function of circuit design and constraint condition;
Step 2 uses the method for geometric programming that circuit is optimized, and obtains the substandard optimal design parameters of posynomial model evaluation
Figure 767102DEST_PATH_IMAGE006
Step 3 utilizes posynomial model and SPICE emulator to remove to assess design parameter
Figure 185445DEST_PATH_IMAGE006
The performance of following circuit promptly obtains respectively
Figure 415569DEST_PATH_IMAGE007
And
Figure 272667DEST_PATH_IMAGE008
The former represents posynomial model evaluation result, and the latter represents the SPICE simulation result;
Step 4 is according to the Different Results of two kinds of assessment modes
Figure 406101DEST_PATH_IMAGE007
And , remove to proofread and correct initial posynomial model, to improve model accuracy.
By repeating step 2-4, MMGP carries out the process of " model tuning-optimal design " iteratively, finally converges on an optimal design point with SPICE class precision.
Below from three aspects realization details of the present invention is described respectively: the foundation of posynomial model, based on the correction of the circuit optimization and the posynomial model of geometric programming.
1, the foundation of posynomial model:
In the present invention, initial posynomial model is derived by the experimental formula of Analogous Integrated Electronic Circuits design and is obtained.Experimental formula is commonly used to calculate initial designs point and provides reference intuitively for deviser's debug circuit.Yet these experimental formulas are expressed as the performance of circuit the function of small-signal variable usually, and for example (phase margin PM) is typically expressed as the phase margin of operational amplifier
Figure 40662DEST_PATH_IMAGE009
(wherein
Figure 373554DEST_PATH_IMAGE010
,
Figure 860031DEST_PATH_IMAGE011
,
Figure 384291DEST_PATH_IMAGE012
Represent transistorized mutual conductance, output resistance and grid source electric capacity) form.Therefore, at first need to convert these experimental formulas to direct function, for example about design parameter
Figure 651324DEST_PATH_IMAGE013
Form.Then, with original design object (for example: ) and design constraint is (for example
Figure 128890DEST_PATH_IMAGE015
, here
Figure 387833DEST_PATH_IMAGE016
Represent corresponding design objective) be converted to GP(geometric programming) compatible form (
Figure 814266DEST_PATH_IMAGE017
,
Figure 250146DEST_PATH_IMAGE018
), require here corresponding expression (
Figure 773531DEST_PATH_IMAGE019
,
Figure 875479DEST_PATH_IMAGE020
) be posynomial.Subordinate list 1 has provided various design constraint or how design object converts the form of GP compatibility to, and has listed corresponding posynomial requirement.
Fortunately, the design object function of a large amount of Analogous Integrated Electronic Circuits and constraint function can natural surface be shown as the posynomial form into design parameter, perhaps can take some approximation methods to be converted to the posynomial function.
2, based on the circuit optimization of geometric programming:
After design object function and design constraint function table be shown as the posynomial form, can become the initial optimization problem description of circuit the form of geometric programming easily:
Figure 117105DEST_PATH_IMAGE021
(1)
Wherein Be optimization variable, the design parameter of indication circuit here, promptly
Figure 911065DEST_PATH_IMAGE022
, here
Figure 511811DEST_PATH_IMAGE003
,
Figure 411372DEST_PATH_IMAGE004
,
Figure 693448DEST_PATH_IMAGE005
, ,
Figure 635177DEST_PATH_IMAGE024
Represent transistorized wide, long, bias current, resistance, and electric capacity respectively;
Figure 851394DEST_PATH_IMAGE025
Expression design object function has the form of posynomial;
Figure 671583DEST_PATH_IMAGE026
(
Figure 463215DEST_PATH_IMAGE027
) expression Performance Constraints condition (design objective), have the form of posynomial;
Figure 140184DEST_PATH_IMAGE028
(
Figure 515801DEST_PATH_IMAGE029
) and (
Figure 346671DEST_PATH_IMAGE031
) representative biasing constraint condition (between transistor operationg region, pipe coupling require etc.):
Figure 397804DEST_PATH_IMAGE028
Be posynomial,
Figure 759253DEST_PATH_IMAGE030
Be single posynomial (having and have only one posynomial); The expression technology is to the restriction of the size of circuit devcie, and wherein, the former is a lower limit, and the latter is the upper limit; ,
Figure 470354DEST_PATH_IMAGE034
,
Figure 554984DEST_PATH_IMAGE035
The number of representing corresponding constraint condition respectively.Geometric programming problem (1) can be converted to a protruding optimization problem, therefore can try to achieve globally optimal solution with high efficient.
3, posynomial model tuning:
MMGP proofreaies and correct the posynomial model by a kind of mode very intuitively: multiply by correction factor and (annotate: in the iterative process on initial posynomial model based, it all is to multiply by correction factor on initial posynomial model based that each step proofreaies and correct), and the ratio of the performance parameter that circuit performance parameters that correction factor is obtained by SPICE emulation and posynomial model evaluation obtain obtains.In this way, each step iterative process only needs to carry out a SPICE emulation, so just the time cost of model tuning can be dropped to minimum.And the posynomial model multiply by the form that positive correction factor can't change posynomial, still can optimize apace with original geometric programming method.After the model tuning, geometric programming problem (1) originally is corrected for following form:
Figure 582983DEST_PATH_IMAGE036
(2)
Wherein
Figure 33792DEST_PATH_IMAGE037
Expression is at
Figure 426727DEST_PATH_IMAGE038
The correction factor of item performance parameter is calculated as follows:
(3)
Wherein
Figure 830344DEST_PATH_IMAGE040
The optimal design point that expression previous step iteration obtains;
Figure 804116DEST_PATH_IMAGE041
With
Figure 430269DEST_PATH_IMAGE042
The expression design parameter is
Figure 988027DEST_PATH_IMAGE040
The time circuit
Figure 295512DEST_PATH_IMAGE043
The item performance parameter: the former is the SPICE simulation result, and the latter is posynomial model evaluation result.
Last item constraint condition of geometric programming problem (2)
Figure 451687DEST_PATH_IMAGE044
Meaning be hunting zone with geometric programming be restricted to previous step iteration gained optimization result (
Figure 186425DEST_PATH_IMAGE040
) a neighborhood in (
Figure 732944DEST_PATH_IMAGE045
), here
Figure 640857DEST_PATH_IMAGE046
Be called compressibility factor.And along with the carrying out of iteration, the hunting zone that MMGP can reduce geometric programming gradually (promptly reduces compressibility factor gradually
Figure 201110229280X100002DEST_PATH_IMAGE047
).The precision of model tuning can be progressively improved like this, also convergence of algorithm can be guaranteed.The value of compressibility factor and the mode that reduces are determined on a case-by-case basis, in the specific embodiment of this paper, and compressibility factor
Figure 28369DEST_PATH_IMAGE046
Initial value be
Figure 996325DEST_PATH_IMAGE048
, whenever carry out single-step iteration, Value reduce by half.
Compare with existing Analogous Integrated Electronic Circuits optimization method, MMGP has taken into account precision and efficient well.Compare based on the circuit optimization method of formula with tradition, MMGP has the precision of SPICE level, and the cost of for this reason paying is the overhead that a small amount of SPICE emulation of operation brings.Compare with the optimization method method based on emulation that has the SPICE class precision equally, MMGP has absolute advantage on efficient.Subordinate list 2 is for two-stage miller compensation amplifier, the comparison sheet of the circuit performance that MMGP method of the present invention and the optimization of conventional geometric planing method obtain.
Description of drawings
Fig. 1 is the structural representation of Analogous Integrated Electronic Circuits optimization method of the present invention.
Fig. 2 is the algorithm flow chart of Analogous Integrated Electronic Circuits optimization method of the present invention.
Fig. 3 is the circuit structure diagram of the specific embodiment (two-stage miller compensation amplifier) of Analogous Integrated Electronic Circuits optimization method of the present invention.
Fig. 4 is for two-stage miller compensation amplifier, and MMGP method of the present invention is at the convergence process figure in circuit performance space.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, further specify the present invention below by a concrete example.
One embodiment of the present of invention are that the two-stage miller compensation operation amplifier circuit shown in the accompanying drawing 3 is optimized.This circuit is made up of biasing circuit, differential input stage and common source amplifier stage; Resistance
Figure 679427DEST_PATH_IMAGE049
And electric capacity
Figure 246413DEST_PATH_IMAGE050
Be used for phase compensation.Two-stage miller compensation amplifier shown in the accompanying drawing 3 has 18 design parameters: 8 transistorized length and widths (
Figure 385270DEST_PATH_IMAGE051
), bias current , and building-out capacitor Compensating resistance
Figure 79054DEST_PATH_IMAGE049
Value by the decision of other design parameters, promptly
Figure 326495DEST_PATH_IMAGE053
, here The expression transistor Mutual conductance.
The design adopts
Figure 395799DEST_PATH_IMAGE056
The CMOS(complementary metal oxide semiconductor (CMOS)) technology; We are with supply voltage ,
Figure 372162DEST_PATH_IMAGE058
Be fixed as respectively
Figure 901363DEST_PATH_IMAGE059
,
Figure 861229DEST_PATH_IMAGE060
Load capacitance is fixed as Design object is in the unity gain bandwidth that satisfies maximization amplifier under the condition of design constraint.Initial geometric programming problem description is as follows:
Optimization aim(unity gain bandwidth GBW):
Figure 666429DEST_PATH_IMAGE063
Optimize constraint:
A. (index is maximum output voltage
Figure 61638DEST_PATH_IMAGE064
)
Figure 813693DEST_PATH_IMAGE065
B. (index is minimum output voltage
Figure 573839DEST_PATH_IMAGE067
)
Figure 840872DEST_PATH_IMAGE068
C. (index is quiescent dissipation
Figure 478920DEST_PATH_IMAGE069
)
Figure 147799DEST_PATH_IMAGE070
D. (index is open-loop gain )
Figure 770859DEST_PATH_IMAGE073
E. (index is phase margin
Figure 147351DEST_PATH_IMAGE074
)
F. (index is switching rate
Figure 648051DEST_PATH_IMAGE076
)
Figure 322965DEST_PATH_IMAGE077
G. (index is common-mode rejection ratio
Figure 739034DEST_PATH_IMAGE078
)
Figure 116925DEST_PATH_IMAGE080
H. (index is the negative supply rejection ratio
Figure 655354DEST_PATH_IMAGE081
)
I. (index is equivalent input noise
Figure 836992DEST_PATH_IMAGE084
)
Figure 69390DEST_PATH_IMAGE085
J. biasing constraint
Figure 841037DEST_PATH_IMAGE086
；
Figure 791675DEST_PATH_IMAGE087
；
Figure 611864DEST_PATH_IMAGE088
；
Figure 964348DEST_PATH_IMAGE089
；
Figure 844579DEST_PATH_IMAGE090
；
Figure 282513DEST_PATH_IMAGE091
；
Figure 407858DEST_PATH_IMAGE092
；
Figure 614848DEST_PATH_IMAGE093
K. the process technology limit of design parameter
Figure 665981DEST_PATH_IMAGE094
In above optimization problem,
Figure 591211DEST_PATH_IMAGE095
, wherein
Figure 753202DEST_PATH_IMAGE096
, The gate oxide electric capacity of representing hole mobility, unit area respectively;
Figure 36733DEST_PATH_IMAGE098
, wherein
Figure 885478DEST_PATH_IMAGE099
The expression hole mobility;
Figure 913477DEST_PATH_IMAGE100
,
Figure 32743DEST_PATH_IMAGE101
The threshold voltage of representing PMOS pipe (P-type mos transistor) and NMOS pipe (N type metal oxide semiconductor transistor) respectively;
Figure 487995DEST_PATH_IMAGE102
,
Figure 201110229280X100002DEST_PATH_IMAGE103
The channel length modulation coefficient of representing PMOS pipe and NMOS pipe respectively;
Figure 59922DEST_PATH_IMAGE104
,
Figure 563715DEST_PATH_IMAGE105
The noise figure of representing PMOS pipe and NMOS pipe respectively;
Figure 298672DEST_PATH_IMAGE106
The expression Boltzmann constant;
Figure 924826DEST_PATH_IMAGE107
The expression kelvin degree;
Figure 984049DEST_PATH_IMAGE108
The indication circuit frequency of operation is got here
Figure 353850DEST_PATH_IMAGE109
Here adopt the emulated data of HSPICE emulation tool Level 1 model the posynomial model in the above-mentioned geometric programming problem to be proofreaied and correct in each step of algorithm iteration.(annotate: HSPICE is one of current most popular SPICE emulation tool for the commercial SPICE emulation tool of Synopsys company exploitation.）
Subordinate list 2 has been listed the performance parameter that adopts conventional geometric planing method and MMGP gained optimal design.The performance parameter (HSPICE emulated data) of the circuit that the data representation that is labeled as " GP " in the table is obtained by the optimization of conventional geometric planing method.This optimal design has 3 responsive constraints: phase margin, quiescent dissipation, equivalent input noise.Optimize the result as can be seen from traditional GP method, quiescent dissipation (
Figure 447708DEST_PATH_IMAGE110
) in fact run counter to corresponding design constraint (
Figure 182446DEST_PATH_IMAGE111
), cause " failure design "; Though and phase margin, equivalent input noise satisfy design constraint,, sacrificed the optimization aim function owing to leave excessive design margin (causing " crossing design ").In a word, because the error of posynomial model, adopt the optimal design of traditional GP method to have the shortcoming of precision deficiency.
The data that are labeled as " MMGP " in the subordinate list 2 have been listed the performance parameter of the optimal design that is obtained by the MMGP method (HSPICE emulated data).In the present example, the MMGP algorithm has carried out iteration altogether 10 times, that is to say that whole optimizing process only need move 10 HSPICE emulation.From the optimization result of MMGP method as can be seen, all properties parameter of this design all satisfies design objective; In addition, the performance parameter and the design objective of responsive bound term (phase margin, quiescent dissipation, equivalent input noise) accurately mate, and have avoided crossing design.Therefore, MMGP has improved the precision (reached the optimization precision of HSPICE level) of tradition based on the circuit optimization method of GP greatly, and the cost of for this reason paying is to carry out expense extra time that small amount of H SPICE emulation brings.
Accompanying drawing 4 has write down the iterative process of MMGP method optimization two stage amplifer from performance space by some examples (quiescent dissipation, phase margin, equivalent input noise, unity gain bandwidth).As can be seen from the figure MMGP method speed of convergence is exceedingly fast, and has verified its efficient.
Subordinate list 1
Former design constraint (target) GP design constraint (target) The posynomial requirement
Figure 227500DEST_PATH_IMAGE112
Figure 135413DEST_PATH_IMAGE112
Figure 83778DEST_PATH_IMAGE113
Be posynomial
Figure 989417DEST_PATH_IMAGE114
 Be posynomial
Figure 976855DEST_PATH_IMAGE117
Figure 53395DEST_PATH_IMAGE118
 Be posynomial
Figure 89801DEST_PATH_IMAGE120
 Be posynomial
Figure 563880DEST_PATH_IMAGE123
Figure 554970DEST_PATH_IMAGE124
Figure 394750DEST_PATH_IMAGE125
Be single posynomial
(annotate: go up in the table
Figure 813093DEST_PATH_IMAGE108
(comprise
Figure 371113DEST_PATH_IMAGE126
,
Figure 419357DEST_PATH_IMAGE127
) objective function or the constraint function of indication circuit design,
Figure 51327DEST_PATH_IMAGE128
Represent corresponding design objective).
Subordinate list 2
Circuit performance Design objective GP MMGP
Unity gain bandwidth Maximization
Figure 968467DEST_PATH_IMAGE129
Figure 685888DEST_PATH_IMAGE130
Maximum output voltage
Figure 833152DEST_PATH_IMAGE132
Figure 655615DEST_PATH_IMAGE133
Minimum output voltage
Figure 557766DEST_PATH_IMAGE135
Figure 164328DEST_PATH_IMAGE136
Quiescent dissipation
Figure 95375DEST_PATH_IMAGE137
Figure 849705DEST_PATH_IMAGE138
Figure 524400DEST_PATH_IMAGE139
Open-loop gain
Figure 47785DEST_PATH_IMAGE140
Figure 916777DEST_PATH_IMAGE141
Figure 158403DEST_PATH_IMAGE142
Phase margin
Figure 371209DEST_PATH_IMAGE143
Figure 952363DEST_PATH_IMAGE144
Figure 287530DEST_PATH_IMAGE145
Switching rate
Figure 954134DEST_PATH_IMAGE146
Figure 32949DEST_PATH_IMAGE147
Figure 967144DEST_PATH_IMAGE148
Common-mode rejection ratio
Figure 738791DEST_PATH_IMAGE149
Figure 627113DEST_PATH_IMAGE150
Figure 509618DEST_PATH_IMAGE151
The negative supply rejection ratio
Figure 799785DEST_PATH_IMAGE140
Figure 117951DEST_PATH_IMAGE153
Equivalent input noise
Figure 538568DEST_PATH_IMAGE154

Claims (3)

1. an Analogous Integrated Electronic Circuits optimization method is characterized in that abbreviating MMGP as in conjunction with geometric programming and model tuning, and concrete steps are as follows:
Step 1 is expressed as posynomial form about design parameter, i.e. initialization posynomial model with the objective function of circuit design and constraint condition;
Step 2 uses the method for geometric programming that circuit is optimized, and obtains the substandard optimum circuit design parameter of posynomial model evaluation
Figure 201110229280X100001DEST_PATH_IMAGE002
Step 3 utilizes posynomial model and SPICE emulator to remove to assess design parameter
Figure 120938DEST_PATH_IMAGE002
The performance of following circuit obtains respectively
Figure 201110229280X100001DEST_PATH_IMAGE004
And
Figure 201110229280X100001DEST_PATH_IMAGE006
, the former represents posynomial model evaluation result, the latter represents the SPICE simulation result;
Step 4 is according to the Different Results of two kinds of assessment modes
Figure 411979DEST_PATH_IMAGE004
And
Figure 254033DEST_PATH_IMAGE006
, remove to proofread and correct initial posynomial model, to improve model accuracy;
By repeating step 2-4, carry out the process of " model tuning-optimal design " iteratively, finally converge on an optimal design point with SPICE class precision.
2. Analogous Integrated Electronic Circuits optimization method according to claim 1, after it is characterized in that circuit design objective function and design constraint function table be shown as the posynomial form, the initial optimization problem description of circuit becomes the form of geometric programming as follows:
Figure 201110229280X100001DEST_PATH_IMAGE008
(1)
Wherein
Figure 462292DEST_PATH_IMAGE002
Be optimization variable, the design parameter of indication circuit here, promptly
Figure 201110229280X100001DEST_PATH_IMAGE010
, here
Figure 201110229280X100001DEST_PATH_IMAGE012
,
Figure 201110229280X100001DEST_PATH_IMAGE014
,
Figure 201110229280X100001DEST_PATH_IMAGE016
,
Figure 201110229280X100001DEST_PATH_IMAGE018
, Represent transistorized wide, long, bias current, resistance, and electric capacity respectively;
Figure 201110229280X100001DEST_PATH_IMAGE022
Expression design object function has the form of posynomial;
Figure 201110229280X100001DEST_PATH_IMAGE024
Expression Performance Constraints condition has the form of posynomial,
Figure 201110229280X100001DEST_PATH_IMAGE026
Figure 201110229280X100001DEST_PATH_IMAGE028
And Representative biasing constraint condition,
Figure 965080DEST_PATH_IMAGE028
Be posynomial, Be single posynomial, J=1 ..., n,
Figure 201110229280X100001DEST_PATH_IMAGE032
Figure 201110229280X100001DEST_PATH_IMAGE034
The expression technology is to the restriction of the size of circuit devcie, and wherein, the former is a lower limit, and the latter is the upper limit;
Figure 201110229280X100001DEST_PATH_IMAGE036
,
Figure 201110229280X100001DEST_PATH_IMAGE038
,
Figure 201110229280X100001DEST_PATH_IMAGE040
The number of representing corresponding constraint condition respectively.
3. Analogous Integrated Electronic Circuits optimization method according to claim 2 is characterized in that after the model tuning, and geometric programming problem (1) originally is corrected for following form:
Figure 201110229280X100001DEST_PATH_IMAGE042
(2)
Wherein,
Figure 201110229280X100001DEST_PATH_IMAGE044
Expression is at The correction factor of item performance parameter is calculated as follows:
Figure 201110229280X100001DEST_PATH_IMAGE048
(3)
In the formula, The optimal design point that expression previous step iteration obtains; With
Figure 201110229280X100001DEST_PATH_IMAGE054
The expression design parameter is
Figure 386668DEST_PATH_IMAGE050
The time circuit
Figure 201110229280X100001DEST_PATH_IMAGE056
The item performance parameter: the former is the SPICE simulation result, and the latter is posynomial model evaluation result, in the formula (2)
Figure 201110229280X100001DEST_PATH_IMAGE058
The expression compressibility factor.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105303008A (en) * 2015-12-03 2016-02-03 中国科学院微电子研究所 Method and system for optimizing analogue integrated circuit
CN110245436A (en) * 2019-06-19 2019-09-17 山东大学 A kind of Parallel Simulation circuit optimization method based on genetic algorithm and machine learning
CN112417803A (en) * 2020-12-02 2021-02-26 苏州复鹄电子科技有限公司 Artificial intelligence algorithm-based automatic optimization scheme for design parameters of analog integrated circuit

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