JP2008181377A - System and method for designing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device design system shortening a design period. <P>SOLUTION: The semiconductor device design system is provided with a circuit simulator part SIM for calculating the electric characteristics of an analog circuit including transistors and an optimization control part OPT for operating the SIM while changing a circuit constant of each transistor and automatically searching a circuit constant satisfying previously determined design specifications SPEC. The OPT calculates the circuit constants of respective transistors while sequentially changing the values of respective parameters on the basis of a restriction expression composed of a plurality of previously determined parameters and reflects the calculated circuit constants to the SIM. One of the plurality of parameters shows a rate to a current flowing into a certain reference transistor, and the parameter is obtained by reflecting a Kirchhoff's current rule based on circuit topology between the parameter and the reference transistor. Thus, a search range can be refined by calculating the circuit constant of another transistor by the restriction expression related to the reference transistor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device design system and design method, and more particularly to a technology useful when applied to a circuit constant design system and design method for a semiconductor device including an analog circuit.

For example, Non-Patent Document 1 and Non-Patent Document 2 show a method for designing an operational amplifier circuit using geometric optimization programming (GP). In GP, the characteristics of a target circuit are described by a plurality of inequalities including a posynominal function and a monominal function, and a circuit constant and the like are determined by obtaining an optimal solution by a computer. By using this GP design method, a global optimum solution can be obtained.
P. Mandal, V. Visvanathan, “CMOS Op-Amp Sizing Using a Geometric Programming Formulation”, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, January 2001, VOL.20, NO.1, p.22 -38 Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee, “Optimal Design of a CMOS Op-Amp via Geometric Programming”, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, January 2001, VOL.20 , NO.1, p.1-21

  2. Description of the Related Art In recent years, semiconductor devices in which analog circuits and digital circuits are mixed are widely used, such as SOC (System On Chip), ASIC (Application Specific Integrated Circuit), and microcomputers. When developing such a semiconductor device, not only its performance but also how it can be developed in a short period of time is important. With regard to digital circuits, automation from functional design to layout design is progressing, and it has become possible to complete the design in a short period of time. Analog circuits, on the other hand, are much more automated than digital circuits because of the greater degree of design freedom and the complicated requirements that must be met, including margins for manufacturing process fluctuations. Not. Therefore, in such a semiconductor device, the design of the analog circuit has a great influence on the product development period.

  FIG. 12 is a flowchart showing an example of an analog circuit design procedure studied as a premise of the present invention. This design flow is a general flow when determining circuit constants mainly based on manpower. For example, taking the design of a CMOS (Complementary Metal Oxide Semiconductor) operational amplifier circuit as an example, first, a circuit constant (gate length L) that allows a designer to satisfy a prescribed design specification for a CMOS operational amplifier circuit created in advance. And the gate width W) are set (S121). Examples of design specifications include various items such as gain, unity gain frequency, phase margin, and slew rate.

  Next, a circuit simulation using a computer is executed for the CMOS operational amplifier circuit in which the circuit constants are set (S122). Thereafter, a designer or a circuit simulator calculates numerical values of circuit characteristics such as a gain and a unity gain frequency from the simulation result (S123), and determines whether or not the specified design specifications are satisfied (S124). If the design specification is satisfied, the circuit constant is determined (S125), but if not, the process proceeds to S121, and the designer re-sets the circuit constant and confirms again using the circuit simulation. Thereafter, such an operation is repeated many times until the design specification can be satisfied. Normally, circuit constants are not easily determined by taking process fluctuations, temperature fluctuations, etc. into consideration. Advanced design know-how and abundant experience such as how to deal with the case where the constant can be set or the design specification is not satisfied are required.

  Therefore, for example, by utilizing the processing capability of the computer, the loop processing of FIG. 12 can be automatically performed by trial and error. That is, a function is provided on the computer so that the loop processing of FIG. 12 is automatically performed by setting the initial value, the variable range, the step size, etc. by the designer using the circuit constants (L, W) as variables. Just implement it. However, a CMOS operational amplifier circuit usually includes many MOS transistors. Then, when the circuit constants (L, W) of each MOS transistor are varied as independent variables, the number of operations by the loop processing becomes enormous due to the large number of variables, and a solution cannot be obtained in reality. Things can happen. Therefore, also in this case, depending on the skill of the designer, it is important how appropriate initial values and variable ranges can be set.

  On the other hand, there is a design method as shown in Non-Patent Documents 1 and 2 as a different method from the design method utilizing such circuit simulation. This design method conceptually expresses the target CMOS operational amplifier circuit with a small signal equivalent circuit, creates an evaluation expression (inequality) obtained from the equivalent circuit for each item of the design specification described above, In this method, the circuit constants are determined in consideration of the area and the like while analyzing the evaluation formula by a computer. In this case, in order for the solution to converge, the evaluation formula must be a posynominal function or a monominal function. When the solution is obtained, circuit simulation is performed on the CMOS operational amplifier circuit reflecting the solution. In this case, the circuit simulation is used to evaluate the validity of the created evaluation formula.

  However, in this case, since it is necessary to create an equivalent circuit and an evaluation formula for each circuit to be evaluated, a highly specialized knowledge of the designer is required. In particular, in the evaluation formula, in addition to the designer having to make the evaluation formula a posynominal function or monominal function, an evaluation formula for each so-called corner condition for ensuring a margin for process, power supply voltage, and temperature dependence. It is also necessary to adjust the coefficient. Therefore, it takes time and effort to create a reasonable evaluation formula, and it is difficult to say that it is an easy design method because advanced technical knowledge is required.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device design system and design method capable of reducing the design period. Another object of the present invention is to provide a semiconductor device design system and a design method capable of facilitating design. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  A semiconductor device design system according to an embodiment of the present invention calculates a circuit constant of a plurality of transistors in a circuit diagram based on a predetermined constraint equation, and executes a circuit simulation using the circuit constant. By automatically repeating this process, circuit constants that can satisfy design specifications such as predetermined electrical characteristics are automatically searched. At this time, the constraint equation includes a plurality of parameters that are variables or constants, one of which is a reference transistor that is one of the plurality of transistors, and the current ratio is compared with Kirchhoff's current law. This is characterized by the first parameter expressed while reflecting the above. Thus, by making it possible to calculate the circuit constants of other transistors using the constraint equation associated with the reference transistor, the search range of circuit constants can be narrowed, and the design period can be shortened.

As a specific example, for example, a constraint equation for determining a gate width W _i and a gate length L _i which are circuit constants of the MOS transistor (Mi) is:
W _i / L _i = kr ′ · kc _i · kb _i · (W ₁ / L ₁ )
It becomes. kr ′ is a parameter representing a difference in conductivity type of P-type or N-type between the reference MOS transistor (M1) and the MOS transistor (Mi), and kb _i is a gate bias voltage between M1 and Mi. it is a parameter representing the ratio, kc _i is the source between the M1 and Mi - a first parameter described above represents the ratio of the drain current. W ₁ / L ₁ is a parameter representing the gate width / gate length that is the circuit constant of M1. In this way, the design can be facilitated by defining the circuit constants with a simple constraint equation. In addition, if the circuit constant is expressed by a strict expression, a term that reflects the dependency of the power supply voltage, temperature, etc. is required, but in the design system of the present embodiment, the constraint expression plays a role of narrowing the search range, Dependencies such as power supply voltage and temperature are secured by circuit simulation.

  By using the semiconductor device design system according to one embodiment of the present invention, the automatic search range of circuit constants can be narrowed to some extent, and the design period can be shortened or the design can be facilitated.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a schematic diagram showing an example of the configuration of a semiconductor device design system according to Embodiment 1 of the present invention. The design system SYS of FIG. 1 is realized by program processing by a computer system including a CPU, a RAM, and the like, and includes, for example, a circuit simulator unit SIM and an optimization control unit (optimizer) OPT. The circuit simulator unit SIM has a function of calculating electrical characteristics of a circuit described in a circuit diagram (net list) CIT under various given conditions. For example, a SPICE (Simulation Program with Integrated Circuit Emphasis) system and What is called is widely known. As an outline of the function, the optimization control unit OPT has circuit constants (gate length L and gate width W in the case of a MOS transistor) of each element in the circuit diagram CIT until the simulation result by the SIM satisfies a predetermined specification. Is automatically changed to automatically design circuit constants.

  The optimization control unit OPT includes an input control unit ICTL, an output control unit OCTL, and a simulator control unit SCTL. The input control unit ICTL determines various constraint conditions CST predetermined by the designer and input signals to be given to the circuit diagram CIT based on the control from the simulator control unit SCTL, and sets these information in the circuit simulator unit SIM To do. The output control unit OCTL includes a determination processing unit JGE, and determines whether a simulation result in the SIM satisfies a design specification SPEC determined in advance by a designer.

  The simulator control unit SCTL includes a loop control unit LP and the like. Based on the determination result from the output control unit OCTL, new simulation conditions and circuit constant conditions are formulated, and these conditions are set in the SIM. Controls the input control unit ICTL. That is, a loop process for repeatedly changing the condition of the circuit constant is performed until the simulation result under the predetermined simulation condition satisfies the design specification SPEC. The simulation conditions include a combination of process condition (P) / voltage condition (V) / temperature condition (T) / detailed transistor model (Model) called corner condition CND, and the above-described circuit diagram CIT. Includes input signal conditions.

  In such a configuration, the main feature of the design system of FIG. 1 is a constraint condition CST for restricting the constant setting range for the circuit constants of each circuit element included in the circuit diagram CIT. CST includes constraint expressions corresponding to circuit elements such as transistors (TR), capacitors (capacitance) (C), and resistances (R). Among them, the constraint expression of TR is particularly characteristic. That is, although details will be described later, by using the TR constraint equation to optimize the setting range of the TR circuit constants (for example, L and W in the case of MOS transistors), for example, by the optimization controller OPT Enable automatic design of circuit constants in a short period of time.

  Next, the principle of the constraint equation of the transistor TR will be described. In the first embodiment, a MOS transistor is taken as an example of the transistor TR. For example, in an analog circuit such as an operational amplifier circuit, a MOS transistor is operated in a saturation region. In the saturation region of the MOS transistor, the relations of the expressions (1) and (2) are established.

V _DS > V _GS −V _T (1)
I _D = k ′ · (W / L) · (V _GS −V _T ) ² (2)
Here, V _DS is a source-drain voltage, V _GS is a source-gate voltage, V _T is a threshold voltage, _ID is a source-drain current, W is a gate width, and L is a gate length. Further, k ′ is given by Equation (3) using the mobility μ of electrons or holes and the capacitance C _O per unit area of the gate oxide film.

k ′ = (1/2) · μ · C _O (3)
Strictly speaking, the expression (2) adds terms such as a channel length modulation effect and a substrate bias effect. However, in the design system of the first embodiment, it is not necessary to use a strict mathematical expression. Since it is desirable that the mathematical formula is simple, these terms are omitted. Here, the current ratio between the source-drain current I _D1 in the MOS transistor M1 as a reference and I _Di in the MOS transistor Mi of _interest is set as kc _i (= I _Di / I _D1 ), and the equation (2) The circuit constant of Mi (gate width W _i / gate length L _i ) is expressed by equation (4).

W _i / L _i = kr ′ · kc _i · kb _i · (W ₁ / L ₁ ) (4)
In Equation (4), kr ′ means the ratio of k ′ between Mi and M1, and kb _i means the ratio of the gate bias voltage between Mi and M1, respectively. Is described by equation (5). The terms such as the square characteristic (non-linearity) and the omitted substrate bias effect in the equation (2) are obtained by repeating fine adjustment (loop processing) of the coefficient corresponding to the determination result based on the simplified line format. Effectively expressed and designed in a state. A similar example is a numerical calculation method called Newton's method.

In the design system according to the first embodiment, the equation (4) is used as a constraint equation for the MOS transistor, so that the circuit constant (W _i / L _i ) of each MOS transistor Mi included in the circuit diagram CIT is used as a reference. The MOS transistor M1 is characterized by the circuit constant (W ₁ / L ₁ ) and three types of parameters (kr ′, kc _i , kb _i ). In other words, the circuit constants of M1 and Mi are not treated as independent variables, but the circuit constant of Mi is compared with the circuit constant of M1 by the ratio of k ′ (kr ′), current ratio (kc _i ), and bias. They are handled in association with the ratio (kb _i ). In this association, Kirchhoff's law is used as described below.

  FIG. 2 is a circuit diagram showing an example of a folded cascode CMOS operational amplifier circuit as an example of a circuit that performs automatic design using the design system of FIG. FIG. 3 is a circuit diagram showing an example of a basic CMOS operational amplifier circuit as a circuit example different from FIG. 2 includes PMOS transistors M1, M1_2, M2 (_1, 2), M5 (_1, 2), M6 (_1 to 3), M8 (_1 to 3), NMOS transistors M3 (_1, 2), M4 (_1, 2), M7 (_1, 2), a phase compensation capacitor Cc, bias current sources (bias current) Ib1, Ib6, Ib8, and a common mode feedback circuit CMFB.

  M2_1 and M2_2 constitute a differential input stage in which the input signal Vin is applied to the gate, and a bias current (tail current) is commonly supplied from M1 to the source. A bias voltage Vb1 is applied to the gate of M1 by forming a current mirror with M1_2, and Ib1 is connected to M1_2. The drain outputs of M2_1 and M2_2 are M6 (_1, 2), M5 (_1, 2), M4 (_1, 2), M3 (_1, 2) connected in series in order from the power supply voltage VDD to the ground voltage GND. Differentially amplified by a folded cascode stage consisting of The common gate of M6 (_1, 2) forms a current mirror with M6_3, so that a bias voltage Vb6 is applied, and Ib6 is connected to M6_3. Bias voltages Vb5 and Vb4 are respectively applied to the common gate of M5 (_1,2) and the common gate of M4 (_1,2) by a circuit (not shown).

  The signal differentially amplified by the folded cascode stage is further amplified by an output stage composed of M8_1 that supplies M7_1 and its bias current (load current), and M8_2 that supplies M7_2 and its load current. It becomes the output signal Vout. A bias voltage Vb8 is applied to the common gate of M8 (_1, 2) by forming a current mirror with M8_3, and Ib8 is connected to M8_3. The CMFB controls the bias voltage Vb3 to the common gate of M3 (_1, 2) while monitoring the output signal Vout.

  On the other hand, the circuit of FIG. 3 includes PMOS transistors M1, M1_2, M2 (_1, 2), M8 (_1 to 3), NMOS transistors M3 (_1, 2), M7 (_1, 2), and a phase compensation capacitor Cc. And bias current sources Ib1 and Ib8 and a common mode feedback circuit CMFB. This circuit has a configuration in which the folded cascode stage is omitted from the circuit of FIG. That is, the drain outputs of M2_1 and M2_2 receiving the input signal Vin at the gate are differentially amplified by the bias current (load current) of M3 (_1, 2), and this differentially amplified signal is output from the output stage described above. Further output provides an output signal Vout.

  Taking these two circuits as an example, when the circuit constants in each circuit are automatically designed by the design system of FIG. 1, the designer first formulas each circuit element in the circuit diagram as follows: The constraint equation shown in (4) is created. In the circuit of FIG. 2, the source-drain current I of each MOS transistor in the differential input stage, the folded cascode stage, and the output stage is expressed by the equations (6), (7), and (5) according to Kirchoff's current law, respectively. The relationship (8) is established.

Differential input stage:
I ₁ = I _{2_1} + I _{2_2} ,
I _{2_2} = I _{2_1} (6)
Folded cascode stage:
_{I 6_2 = I 6_1 = I 5_2} = I 5_1 = I 4_2 = I 4_1,
I _{3_2} = I _{3_1} = I _{2_1} + I _{4_1} (7)
Output stage:
I _{8_2} = I _{8_1} = I _{7_2} = I _{7_1} (8)
In the formulas (6) to (8), the subscript of the current I corresponds to the subscript of the MOS transistor, for example, the current I _{2_1} corresponds to the MOS transistor M _{2_1} . Further, in FIG. 2, those values of index i of the MOS transistor _{M I_j} are equal using the same circuit constant in terms of the circuit configuration, for example, circuit constants of _{M 2_1} and _{M 2_2} are equal. Here, Equation (6) based on the relationship to (8), the current ratio of _{I 6} relative to _{I 1} current ratio _(I 6 / _{I 1)} the _kc 6, _{I 8 (I} 8 _{/ I} 1) the putting and kc _8, constraints of the MOS transistors is determined by the equation (9) to (11).

Differential input stage:
_{W 2_2 / L 2_2 = W 2_1} / L 2_1 = (1/2) · kb 2 · (W 1 / L 1) (9)
Folded cascode stage:
_{W 6_2 / L 6_2 = W 6_1} / L 6_1 = kc 6 · kb 6 · (W 1 / L 1),
W _{5_2} / L _{5_2} = W _{5_1} / L _{5_1} = kc ₆ · kb ₅ · (W ₁ / L ₁ ),
_{W 4_2 / L 4_2 = W 4_1} / L 4_1 = kr '· kc 6 · kb 4 · (W 1 / L 1),
_{W 3_2 / L 3_2 = W 3_1} / L 3_1 = kr '· (1/2 + kc 6) · kb 3 · (W 1 / L 1) (10)
Output stage:
W _{8_2} / L _{8_2} = W _{8_1} / L _{8_1} = kc ₈ · kb ₈ · (W ₁ / L ₁ ),
_{W 7_2 / L 7_2 = W 7_1} / L 7_1 = kr '· kc 8 · kb 7 · (W 1 / L 1) (11)
In the formula (9) to Formula (11), kb is M1 is a bias voltage ratio between the gate bias voltage Vb1, such kb ₆ becomes Vb1 / Vb6. In addition, kr ′ is the ratio of k ′ (Equation (3)) between the PMOS transistor M1 and the capacitance _CO of the PMOS transistor and the NMOS transistor are normally designed to be equal. In this case, kr ′ is “1”, and in the case of an NMOS transistor, kr ′ is μ _P / μ _N.

  On the other hand, in the circuit of FIG. 3, as in the circuit of FIG. 2, the source-drain currents I of the MOS transistors in the differential input stage and the output stage are respectively expressed by the equations (12) and (12) according to Kirchoff's current law. (13)

Differential input stage:
I ₁ = I _{2_1} + I _{2_2} ,
I _{3_2} = I _{3_1} = I _{2_2} = I _{2_1} (12)
Output stage:
I _{8_2} = I _{8_1} = I _{7_2} = I _{7_1} (13)
Therefore, based on the relationship between Expression (12) and Expression (13), the constraint expression of each MOS transistor is determined as Expression (14) and Expression (15).

Differential input stage:
_{W 2_2 / L 2_2 = W 2_1} / L 2_1 = (1/2) · kb 2 · (W 1 / L 1),
_{W 3_2 / L 3_2 = W 3_1} / L 3_1 = kr '· (1/2) · kb 3 · (W 1 / L 1) (14)
Output stage:
W _{8_2} / L _{8_2} = W _{8_1} / L _{8_1} = kc ₈ · kb ₈ · (W ₁ / L ₁ ),
_{W 7_2 / L 7_2 = W 7_1} / L 7_1 = kr '· kc 8 · kb 7 · (W 1 / L 1) (15)
In Expressions (9) to (11), for example, the gate width of the MOS transistor M _{i_j} is set to W _i and the gate length is set to W ₂ = W _{2_2} = W _{2_1} , L ₂ = L _{2_2} = L _{2_1.} putting a L _i, the formula (9) to (11) becomes equation (16).
W ₂ = (1/2) · kb ₂ · (L ₂ / L ₁ ) · W ₁ ,
W ₃ = kr ′ · (1/2 + kc ₆ ) · kb ₃ · (L ₃ / L ₁ ) · W ₁ ,
W ₄ = kr ′ · kc ₆ · kb ₄ · (L ₄ / L ₁ ) · W ₁ ,
W ₅ = kc ₆ · kb ₅ · (L ₅ / L ₁ ) · W ₁ ,
W ₆ = kc ₆ · kb ₆ · (L ₆ / L ₁ ) · W ₁ ,
W ₇ = kr ′ · kc ₈ · kb ₇ · (L ₇ / L ₁ ) · W ₁ ,
W ₈ = kc ₈ · kb ₈ · (L ₈ / L ₁ ) · W ₁ (16)
On the other hand, in the same manner, Expressions (14) and (15) become Expression (17).
W ₂ = (1/2) · kb ₂ · (L ₂ / L ₁ ) · W ₁ ,
W ₃ = kr ′ · (1/2) · kb ₃ · (L ₃ / L ₁ ) · W ₁ ,
W ₇ = kr ′ · kc ₈ · kb ₇ · (L ₇ / L ₁ ) · W ₁ ,
W ₈ = kc ₈ · kb ₈ · (L ₈ / L ₁ ) · W ₁ (17)
As can be seen from the above constraint equation, the circuit constants (L _i , W _i ) of each MOS transistor Mi are the circuit constants (L ₁ , W ₁ ) of the reference MOS transistor M1 and the transistor polarity (P-type or N-type), source-drain current, and bias voltage, and the respective parameters kr ′, kc _i , kb _i representing the ratio of Mi. At this time, the number of kc as an independent variable is reduced by applying Kirchhoff's current law based on a circuit topology such as parallel connection or series connection.

Specifically, for example, in the differential input stages M2_1 and M2_2, ½ times the current of M1 flows, and in the case of series connection such as M4_1 to M6_1, each of the currents of M1 is kc ₆ times. Shall flow equally. Further, in the case of a parallel connection with a branch point, a sum current (1/2 + kc ₆ ) of a current flowing through M2_1 (corresponding to 1/2) and a current flowing through M5_1 (corresponding to kc ₆ ) flows like M3_1. Shall.

By applying Kirchhoff's current law in this way, for example, in FIG. 2, when the current ratio of M2 to M8 is expressed based on M1, seven independent variables of kc ₂ to kc ₈ are usually required. However, it can be reduced to two independent variables kc ₆ and kc ₈ . As for the bias voltage ratio, the number of independent variables is reduced by assigning a common bias voltage ratio to the transistors whose gates are commonly connected, such as M3_1 and M3_2. In the design system shown in FIG. 1, the circuit constants are automatically designed in the procedure shown in FIG. 4, for example, while such independent variables are sequentially changed.

  FIG. 4 is a flowchart showing an example of processing contents of automatic design using the design system of FIG. First, in S401, the designer creates a circuit diagram as described in FIG. 2 and FIG. 3 and a constraint equation for each MOS transistor and the like included in the circuit diagram, and further includes the constraint equation and the circuit diagram. Set the variable range for each independent variable. Here, the constraint equation may include a constraint equation for the capacitor C and the resistor R in addition to the constraint equation for TR (MOS transistor), as indicated by the constraint condition CST in FIG. For example, when the capacitor C is formed using a MOS transistor, or when the resistor R is formed by a diffusion layer or the like, the size (circuit constant) is used as an independent variable, and a capacitance value or a resistance value is incorporated as a constraint equation. Is possible.

The variable range of each independent variable is set to the following range, for example, taking the circuits of FIGS. 2 and 3 as an example.
(1) Gate length: Lmin ≦ L ₁ , L ₂ , L ₃ , L ₄ , L ₅ , L ₆ , L ₇ , L ₈ ≦ Lmax
(2) Gate width: Wmin ≦ W ₁ ≦ Wmax
(3) Current ratio: 0.1 ≦ kc ₆ ≦ 5, 1 ≦ kc ₈ ≦ 10
(4) Bias voltage ratio: 0.1 ≦ kb ₂ , kb ₃ , kb ₄ , kb ₅ , kb ₆ , kb ₇ , kb ₈ ≦ 5-10
(5) k ′ ratio: 1/6 ≦ kr ′ ≦ 1/2
(6) Bias current: Imin ≦ Ib1, Ib6, Ib8 ≦ Imax
(7) Phase compensation capacity: CLmin ≦ Cc ≦ CLmax
Lmin, Lmax and Wmin, Wmax are determined by lithography limitations of the manufacturing process, layout rules, circuit area limitations, and the like. The current ratio and the bias voltage ratio are determined by empirical factors and trial and error. Imin and Imax are determined based on power consumption specifications and the like. CLmin is determined in consideration of the limitation of the circuit area and the drain capacity of the MOS transistors (M7 and M8). CLmax is determined in consideration of the load capacitance CL, the capacitance value of CLmin, and the like.

Next, in S402, the optimization control unit OPT in FIG. 1 sets initial circuit constants for each circuit element included in FIGS. 2 and 3 based on the constraint equation defined in S401 and the variable range of each independent variable. Set. At this time, for each MOS transistor, the initial value in the variable range described above is assigned to each independent variable (kr ′, kc, kb, W ₁ , L _{1 to} L ₈ ) in the constraint equation. Is used to calculate L and W for each MOS transistor.

  Subsequently, in S403, the optimization control unit OPT sets simulation conditions. The simulation conditions include an input signal condition, a corner condition CND composed of a combination of process condition (P) / voltage condition (V) / temperature condition (T) / detailed transistor model (Model). Thereafter, the OPT sets the circuit diagram CIT in which the circuit constants are determined in S402 and the simulation conditions defined in S403 for the circuit simulator SIM, and operates the SIM (S404).

  When the simulation result by the SIM is obtained, the OPT calculates the circuit characteristics based on the evaluation items set in advance by the designer (S405). The evaluation items include various items such as gain, unity gain frequency (UGF), and phase margin as representatives. For example, when the SIM is a SPICE system, the gain is obtained by observing the output signal (Vout in FIGS. 2 and 3) of the circuit diagram CIT by the SIM function and the input signal (in FIGS. 2 and 3). It is obtained by calculating the ratio with (Vin).

Further, the evaluation item includes an item for confirming that each MOS transistor operates in the saturation region. The circuits as shown in FIGS. 2 and 3 are based on the premise that each MOS transistor operates in the saturation region, and the constraint equations for each MOS transistor described above are also premised on the assumption that they operate in the saturation region. In order to confirm the validity of the circuit simulation result, an evaluation item for this saturation condition is required. Therefore, for example, the drain-source voltage margin ΔV _DS and the gate-source voltage margin ΔV _GS for the operating power supply voltage and the like are determined in advance in the design specification SPEC of FIG. Then, the gate, drain and source voltages of each MOS transistor are observed by the SIM function, and it is confirmed whether or not each MOS transistor satisfies the condition of Expression (18). In Expression (18), V _DSAT is a saturation drain voltage (= | V _GS −V _T |).
| V _DS −V _DSAT | ≧ ΔV _DS ,
| V _GS −V _T | ≧ ΔV _GS (18)
The optimization control unit OPT performs the processes of S403 to S405 while sequentially changing simulation conditions (corner conditions). When the evaluation under the predetermined simulation conditions is completed, in step S406, the OPT determines the circuit characteristics calculated in step S405. That is, when each corner condition is applied to the circuit, it is determined whether the evaluation items such as the gain described above satisfy a predetermined SPEC value and whether each MOS transistor satisfies the saturation condition of Expression (18). Is done.

  If all the determination results in S406 are satisfied, the circuit constants of the circuit elements determined in S402 are determined as final solutions in S407, and the automatic design is completed. On the other hand, if there is an unsatisfactory evaluation item in the determination result, the process proceeds to S402, the circuit constant is changed, and the processes of S403 to S405 are performed again. That is, the loop processing of S402 to S406 is performed until a circuit constant that satisfies a predetermined design specification SPEC is found. In this loop processing, for example, if a circuit constant is changed using a known gene algorithm or the like, a solution can be found in a shorter period of time.

  As described above, for example, the following effects can be obtained by executing the processing flow as shown in FIG.

First, it is possible to automatically design circuit constants in a short period of time. This is because the variable range of the circuit constants in the loop processing of FIG. 4 can be optimized by applying Kirchhoff's law to the constraint expression as described above. This will be described with reference to FIG. FIG. 5 is an explanatory diagram for conceptually showing an example of the effect in the design system of FIG. First, the variable range of the circuit constant when the constraint equation as described above as Comparative Example 1 is not used is as follows when the circuit of FIG. 2 is taken as an example.
(1) Gate length: Lmin ≦ L ₁ , L ₂ , L ₃ , L ₄ , L ₅ , L ₆ , L ₇ , L ₈ ≦ Lmax
(2) Gate width: Wmin ≦ W ₁ , W ₂ , W ₃ , W ₄ , W ₅ , W ₆ , W ₇ , W ₈ ≦ Wmax
(3) Bias current: Imin ≦ Ib1, Ib6, Ib8 ≦ Imax
(4) Phase compensation capacity: CLmin ≦ Cc ≦ CLmax
Here, as an example, focusing on the relationship between W ₁ and W ₂ , in Comparative Example 1, W ₂ is also searched in a variable range of Wmin to Wmax with respect to W ₁ consisting of Wmin to Wmax in FIG. Become. Therefore, the search range by the loop processing is the entire square area as indicated by the area W2_SAc in FIG. Although not shown, also in the other gate width _W i (i = _3~8), with respect to _{W 1} consisting Wmin~Wmax, _{W i} to be searched in the variable range of Wmin～Wmax Become.

On the other hand, a guide in the design system 1, the constraint equation, with respect to _{W 1} consisting Wmin~Wmax in FIG 5, _{W 2,} as seen from equation (16), the _W 1/2 that reflects the current ratio The variable range is set to. Therefore, the search range of the loop, as shown in FIG. 5, W _1/2 the area W2_SA that reflects the variable range according kb ₂ etc. in the back and forth relative to the. Although not shown, a specific search range based on a constraint equation is similarly determined for W ₁ in other gate widths W _i (i = 3 to 8). Therefore, since the search range is significantly narrower than that in Comparative Example 1, it is possible to automatically design circuit constants in a short period of time.

  Second, automatic design of circuit constants can be easily performed. This is because the constraint equation is simplified as much as possible, and matters not guaranteed by the constraint equation are guaranteed by the circuit simulator. That is, in the geometric optimization programming (GP) method as described above as the comparative example 2, the circuit constant is determined only by the constraint equation, so the constraint equation itself is, for example, the process (P) / power source. It must be strict including voltage (V) / temperature (T) dependence, channel length modulation effect, substrate bias effect, and the like.

  On the other hand, in the design system of FIG. 1, the constraint equation plays a role of narrowing the search range of circuit constants, and within that range, the circuit simulator incorporates P / V / T dependence, channel length modulation effect, substrate bias effect, and the like. Thus, a strict optimum solution is calculated. Therefore, the constraint expression does not need to be strict and may be any expression that can set an appropriate search range. In this sense, the influence of the channel length modulation effect and the substrate bias effect is considered to be small, and an appropriate search range can be set even if these terms are omitted. This simplifies the constraint equation and improves the ease of design. If the constraint equation changes depending on the P / V / T dependency, the constraint equation must be changed for each corner condition, and an easy design cannot be performed. In this sense, the constraint equation of Equation (4) is invariant because Kirchhoff's law does not have P / V / T dependency, and can be commonly applied regardless of various conditions.

  Thirdly, it is possible to improve design efficiency by performing loop processing with the bias current Ib as an independent variable. That is, in a general design method based on circuit simulation, first, a procedure is adopted in which a bias current is set, and circuit constants that satisfy the design specifications at the bias current are found. This is largely due to artificial reasons that it is difficult to design circuit constants without providing a reference for fixing the bias current. However, in this method, when a circuit constant cannot be found with a certain bias current, all circuit constants are searched again from the beginning after changing the bias current.

  Therefore, in the processing flow of FIG. 4, the bias current Ib and the circuit constant are each changed as independent variables without being caught by the above-described procedure (time-series concept). In other words, for example, when a circuit constant cannot be found, a process for searching for a bias current that satisfies the design specifications with the circuit constant fixed, or a process for searching for the bias current and the circuit constant simultaneously using a genetic algorithm And so on. As a result, a more efficient design can be performed, and the possibility that an optimal solution can be found in a short period of time increases. When the loop process is performed with the bias current as an independent variable, the search range is widened accordingly, but this is realistic by drastically reducing the search range by the constraint equation as described in FIG. Realizability is ensured.

  Next, an embodiment in which circuit constants are actually designed using the design system of FIG. 1 and the processing flow of FIG. 4 will be described. Here, it is assumed that a 0.15 μm CMOS process is used for each of the circuits in FIGS. 2 and 3, and the circuit constant when the power supply voltage VDD is 1.5 V and the circuit constant when 3.3 V are used. Designed.

FIG. 6 is an explanatory diagram showing an example of design specifications used in the design system of FIG. As shown in FIG. 6, in the present embodiment, the design specification SPEC includes gain (A0), unity gain frequency (ft), phase margin (PM), power supply current, saturation condition (see equation (18)), and load. It was set circuit characteristic evaluation items such as capacitance C _L. Here, the saturation condition is individually set for each power supply voltage specification (1.5 V, 3.3 V), and the other evaluation items are commonly set for each power supply voltage specification.

  Then, using the design system of FIG. 1 and the processing flow of FIG. 4, a circuit constant that satisfies such a design specification SPEC was searched. In this case, the variable range of each independent variable in the constraint equation of the MOS transistor and the circuit element is set as an example in the description of FIG. Since the constraint equation of the MOS transistor does not depend on the P / V / T condition as described above, it can be commonly used in the 1.5V specification and the 3.3V specification.

  The corner condition CND of FIG. 1 includes five types of MOS transistor model conditions, two types of CR delay conditions (large delay and small delay) consisting of capacitance and resistance, two types of temperature conditions (high temperature and low temperature), power supply A total of 41 types were set by adding the cases where the conditions were typical to the combination conditions consisting of two types of voltage conditions (high voltage and low voltage). The five types of MOS transistor models are “SMOS”, “SF”, “FS”, which indicate that “PMOS transistor, NMOS transistor” becomes slow (S) or fast (F) depending on process variations, respectively. ”Condition,“ FF ”condition, and“ Typ ”condition indicating that both become typical.

  When searching for a solution satisfying the above-mentioned design specification SPEC with the design system of FIG. 1 under all such corner conditions CND, results as shown in FIGS. 7 to 10 were obtained. FIG. 7 shows the circuit characteristic evaluation result in the 3.3V specification in the circuits of FIG. 2 and FIG. 3, and FIG. 8 shows the circuit characteristic evaluation result in the 1.5V specification similarly. FIG. 9 shows a circuit constant search result of each circuit element corresponding to FIG. 7, and FIG. 10 shows a circuit constant search result of each circuit element corresponding to FIG.

  As shown in FIGS. 7 and 8, the folded cascode CMOS operational amplifier circuit (Cascode) in FIG. 2 and the basic CMOS operational amplifier circuit (Basic) in FIG. The optimum solution satisfying the design specification SPEC of 6 was obtained. This optimum solution could be obtained without requiring one day by the arithmetic processing by the design system of FIG. On the other hand, as a comparative example 1 described with reference to FIGS. 4 and 5, the method of searching for the gate length L and the gate width W of each MOS transistor as an independent variable without using the constraint equation of the MOS transistor takes 10 days. The result was that the optimal solution could not be obtained.

Further, as shown in FIGS. 9 and 10, it can be seen that reasonable results are obtained by observing the circuit constants of the circuit of FIG. 2 and the circuit of FIG. For example, a skilled designer often does not design the gate lengths L ₂ and L ₃ of the differential input stage MOS transistors M 2 and M ₃ so small in order to obtain a high gain. Conversely, in order to obtain a high slew rate, the gate lengths L ₇ and L ₈ of the MOS transistors M 7 and M ₈ in the output stage are often designed to be small and the gate widths W ₇ and W ₈ are designed to be large. Such a tendency is seen in the results shown in FIG. 9 and FIG.

  As described above, by using the design system and the design method of the first embodiment, circuit constant design of a semiconductor device including an analog circuit can be realized in a short period of time. In addition, circuit constant design of a semiconductor device including an analog circuit can be easily realized.

  In addition, although the case where the SPICE system simulator widely known as the circuit simulator part SIM of FIG. 1 is used is taken as an example here, the simulator is not limited to such a simulator. For example, in a simulator that searches for circuit characteristics and circuit constants based on a small signal equivalent circuit, the mutual conductance gm of each MOS transistor in the small signal equivalent circuit is treated as an independent variable to search for an optimal solution. Is done. Therefore, if the above-described constraint equation is reflected on gm which is a function of the gate length L and the gate width W, it is possible to give the relevance based on Kirchhoff's law to each independent gm. Therefore, the search range can be reduced.

(Embodiment 2)
In the first embodiment described above, an example in which a constraint equation is used for a circuit composed of MOS transistors has been described. However, the basic concept of the constraint equation based on Kirchhoff's law described above is not limited to a MOS transistor but also to a bipolar transistor or the like. Applicable. Therefore, in the second embodiment, an outline of creating a constraint equation for a bipolar transistor will be described.

  FIG. 11 is a circuit diagram for illustrating a constraint equation of a bipolar transistor in the semiconductor device design system according to the second embodiment of the present invention. In FIG. 11, as a part of the amplifier circuit or the like, bipolar transistors Q2_1 and Q2_2 serving as a differential input stage, a bipolar transistor Q1 for supplying a tail current thereof, a bipolar transistor Q1_2 for setting a bias current of Q1, and a bias current source Ib is shown.

In creating the constraint equation, the difference from the circuit composed of the MOS transistor shown in the first embodiment is that it can be assumed that no current flows through the gate of the MOS transistor, whereas the base of the bipolar transistor is slightly different. Current is flowing. Therefore, it is necessary to pay attention to the relationship of the current ratio based on Kirchhoff's law. Therefore, in the bipolar transistor, for example, a direct current amplification factor _hFE or the like may be introduced as an independent variable in the constraint equation. Then, the emitter current I _E and the collector current I _C are given by the equation (18) with respect to the base current I _B of the bipolar transistor.
I _C = h _FE · I _B ,
I _E = (h _FE +1) · I _B (18)
In FIG. 11, when the emitter currents of Q2_1 and Q2_2 are I _E21 and I _E22 , respectively, and the collector current of Q1 is I _C1 , the relationship of Expression (19) is established.
I _C1 = I _E21 + I _E22 ,
I _E21 = I _E22 (19)
Further, the emitter currents I _E21 and I _E22 of Q2_1 and Q2_2 can be expressed by Expression (20) using I _B21 and I _B22 from Expression (18).
I _E21 = (h _FE2 +1) · I _B21 ,
I _E22 = (h _FE2 +1) · I _B22 (20)
Here, if the current ratios of I _B21 , I _B22 and I _{B1 of} Q2_1 and Q2_2 are defined as kc ₂₁ (= I _B21 / I _B1 ) and kc ₂₂ (= I _B22 / I _B1 ), respectively, Equation (20) Becomes Equation (21).
I _E21 = (h _FE2 +1) · kc ₂₁ · I _B1 ,
I _E22 = (h _FE2 +1) · kc ₂₂ · I _B1 (21)
Therefore, the design system of FIG. 1 determines I _B21 and I _B22 according to the variable ranges of h _FE2 and kc ₂₁ and kc _{22 which} are independent variables with respect to I _B1 , and accordingly, Q1 and Q2_1 and Q2_2. Processing to set each circuit constant is performed. Then, the circuit simulation is executed for the circuit in which the circuit constant is set, and if the result does not satisfy the design specification, the final loop processing is executed by repeating the circuit simulation while changing the independent variable. Search for circuit constants.

Since kc ₂₁ and kc ₂₂ are halved from the equation (19), respectively, a constraint equation based on I _E1 with respect to I _E21 and I _E22 of Q2_1 and Q2_2 is the equation (22). Therefore, Q2_1, in _{Q2_2,} by varying the _{h FE1, h FE2} reference to the _{I B1,} so that the circuit constant is set.
I _E21 = I _E22 = (1/2) · (h _FE2 +1) · I _B21 (22)
Substituting I _B21 / I _B1 = kc ₂₁ into equation (22), equation (23) is obtained.
I _E21 = I _E22 = (1/2) · (h _FE2 +1) · kc ₂₁ · I _B1 (23)
As described above, by using the design system of the second embodiment, the circuit constant design of the semiconductor device including the analog circuit can be realized in a short period of time as in the first embodiment. In addition, circuit constant design of a semiconductor device including an analog circuit can be easily realized.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. For example, in the first embodiment, a specific constraint equation for the MOS transistor is shown, but it goes without saying that the same constraint equation is applicable to any transistor of the MIS (Metal Insulator Semiconductor) type without being limited to the MOS transistor. Of course, the circuit to be designed is not limited to the operational amplifier circuit, and may be various analog circuits such as a power supply circuit and an ADC (Analog Digital Converter) circuit.

  The semiconductor device design system according to the present invention is particularly useful when applied to a design system and a design method for designing circuit constants using circuit simulation for a semiconductor device including an analog circuit formed of MOS transistors. The technology is not limited to this, and can be widely applied to all semiconductor device design systems.

1 is a schematic diagram showing an example of the configuration of a semiconductor device design system according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a folded cascode CMOS operational amplifier circuit as an example of a circuit that performs automatic design using the design system of FIG. 1. FIG. 3 is a circuit diagram showing an example of a basic CMOS operational amplifier circuit as a circuit example different from FIG. 2. It is a flowchart which shows an example of the processing content of the automatic design using the design system of FIG. In the design system of FIG. 1, it is explanatory drawing for showing an example of the effect notionally. It is explanatory drawing which shows an example of the design specification used with the design system of FIG. FIG. 4 is a diagram illustrating an example of a result of automatic design performed by the design system of FIG. 1, and is an explanatory diagram illustrating a circuit characteristic evaluation result with 3.3 V specifications in the circuits of FIGS. 2 and 3. FIG. 4 is a diagram illustrating an example of a result of automatic design performed by the design system of FIG. 1, and is an explanatory diagram illustrating a result of circuit characteristic evaluation with 1.5 V specifications in the circuits of FIGS. It is explanatory drawing which shows the circuit constant search result of each circuit element corresponding to FIG. It is explanatory drawing which shows the circuit constant search result of each circuit element corresponding to FIG. FIG. 7 is a circuit diagram for explaining a constraint equation of a bipolar transistor in a semiconductor device design system according to a second embodiment of the present invention. It is a flowchart which shows an example of the design procedure of the analog circuit examined as a premise of this invention.

Explanation of symbols

CND corner condition SYS design system SCTL simulator control unit OPT optimization control unit SPEC design specification LP loop control unit CST constraint condition ICTL input control unit SIM circuit simulator unit CIT circuit diagram OCTL output control unit JGE judgment processing unit M MOS transistor Ib Bias current Source CL Load capacitance Cc Phase compensation capacitance CMFB Common mode feedback circuit Q Bipolar transistor

Claims (11)

A semiconductor device design system using a computer system,
The computer system includes:
A first function for calculating circuit constants of a plurality of transistors included in a circuit diagram based on a constraint equation including a plurality of parameters;
A second function for calculating electrical characteristics with respect to the circuit diagram in a state in which the circuit constants calculated by the first function are reflected;
Processing in the first function and the second function while changing the substitution values for the plurality of parameters until the calculation result of the electrical characteristics in the second function satisfies a predetermined design specification. With a third function to loop
The plurality of parameters include a first parameter representing a current ratio with a reference transistor that is one of the plurality of transistors as a comparison target,
The semiconductor device design system, wherein the first parameter reflects Kirchhoff's current law based on a connection relationship between the plurality of transistors. The semiconductor device design system according to claim 1,
The plurality of transistors are MOS transistors;
The constraint equation for calculating the gate width W _i / gate length L _i as the circuit constant of the i-th MOS transistor (Mi) is:
W _i / L _i = kr ′ · kc _i · kb _i · (W ₁ / L ₁ )
And
kr ′ is a parameter representing a difference in conductivity type of P-type or N-type between the MOS transistor (M1) serving as the reference transistor and the MOS transistor (Mi),
kb _i is a parameter representing the ratio of the gate bias voltage between the MOS transistor (M1) and the MOS transistor (Mi),
kc _i is the first parameter representing the ratio of the source-drain current between the MOS transistor (M1) and the MOS transistor (Mi),
W ₁ / L ₁ is a parameter representing a gate width / a gate length that is a circuit constant of the MOS transistor (M 1). The semiconductor device design system according to claim 2,
If kc _j to be the first parameter for the j-th MOS transistor (Mj) is set, kc _k to be the first parameter for the k-th MOS transistor (Mk) is set,
When the MOS transistor (Mi) is connected in series with the MOS transistor (Mj), kc _i = kc _j ,
A design system for a semiconductor device, characterized in that kc _i = kc _j + kc _k when branching from the MOS transistor (Mi) and the MOS transistor (Mj) and the MOS transistor (Mk) are connected. The semiconductor device design system according to claim 2,
The design specification for the third function includes an item for confirming that all the MOS transistors serving as the plurality of transistors operate in a saturation region. The semiconductor device design system according to claim 1,
The circuit diagram includes a CMOS operational amplifier circuit, and a semiconductor device design system. The semiconductor device design system according to claim 1,
The circuit diagram includes an amplifier circuit and a current source or a voltage source for setting a bias of the amplifier circuit,
In addition to calculating the circuit constant, the first function selects a value of the current source or the voltage source,
The second function calculates an electrical characteristic with respect to the circuit diagram in a state where the circuit constant and the value of the current source or the voltage source in the first function are reflected,
The third function includes the first function and the second function while changing a value of the current source or the voltage source when a calculation result of electrical characteristics in the second function does not satisfy the design specification. A semiconductor device design system characterized by looping the processing in the semiconductor device. The semiconductor device design system according to claim 1,
Furthermore, a corner condition that is a combination of various conditions including a power supply voltage condition and a temperature condition is set for the circuit diagram, and the electrical characteristics of the circuit diagram in which the corner condition is set are set in the second function. A semiconductor device design system comprising a fourth function for performing calculation. The semiconductor device design system according to claim 7,
The semiconductor device design system, wherein the second function is realized by a SPICE circuit simulator. A circuit diagram including a plurality of transistors, a constraint expression expressing circuit constants for each of the plurality of transistors as a function of a plurality of parameters, a variable range of the plurality of parameters, and values of electrical characteristics to be satisfied by the circuit diagram Based on design specifications including
Computer system
A first process of calculating a circuit constant for each of the plurality of transistors by selecting any value from the variable range of the plurality of parameters and substituting the selected value into the constraint equation;
A second process for calculating electrical characteristics for the circuit diagram in a state in which the circuit constants calculated in the first process are reflected;
A third process for looping the first process and the second process while reselecting the values of the plurality of parameters until the calculation result of the electrical characteristics in the second process satisfies the design specification; Run
The plurality of parameters include a first parameter representing a current ratio with a reference transistor that is one of the plurality of transistors as a comparison target,
The design method of a semiconductor device, wherein the first parameter reflects Kirchhoff's current law based on a connection relation between the plurality of transistors. The method for designing a semiconductor device according to claim 9, wherein
The plurality of transistors are MOS transistors;
The constraint equation for calculating the gate width W _i / gate length L _i as the circuit constant of the i-th MOS transistor (Mi) is:
W _i / L _i = kr ′ · kc _i · kb _i · (W ₁ / L ₁ )
And
kr ′ is a parameter representing a difference in conductivity type of P-type or N-type between the MOS transistor (M1) serving as the reference transistor and the MOS transistor (Mi),
kb _i is a parameter representing the ratio of the gate bias voltage between the MOS transistor (M1) and the MOS transistor (Mi),
kc _i is the first parameter representing the ratio of the source-drain current between the MOS transistor (M1) and the MOS transistor (Mi),
W ₁ / L ₁ is a parameter representing a gate width / gate length which is a circuit constant of the MOS transistor (M 1), and a method for designing a semiconductor device, The method for designing a semiconductor device according to claim 10,
If kc _j to be the first parameter for the j-th MOS transistor (Mj) is set, kc _k to be the first parameter for the k-th MOS transistor (Mk) is set,
When the MOS transistor (Mi) is connected in series with the MOS transistor (Mj), kc _i = kc _j ,
A method for designing a semiconductor device, characterized in that kc _i = kc _j + kc _k when branching from the MOS transistor (Mi) and the MOS transistor (Mj) and the MOS transistor (Mk) are connected.

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