CN113779915A - Integrated circuit performance analysis method and device, simulation equipment and storage medium - Google Patents
Integrated circuit performance analysis method and device, simulation equipment and storage medium Download PDFInfo
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Abstract
The application is applicable to the technical field of integrated circuits, and provides an integrated circuit performance analysis method, an integrated circuit performance analysis device, simulation equipment and a storage medium, wherein a target circuit is subjected to Monte Carlo simulation for a few times to obtain a simulation result of the target circuit; then carrying out variation analysis on the simulation result of the target circuit to obtain a variation analysis result of the target circuit; then, determining a key device in the target circuit according to the variation analysis result of the target circuit, and carrying out Monte Carlo simulation meeting the high yield requirement on the key device according to a preset random table to obtain a random combination in the preset random table corresponding to the worst simulation result of the key device; and finally, carrying out Monte Carlo simulation on the target circuit according to the random number combination to obtain the worst simulation result of the target circuit, and obtaining the yield analysis result of the target circuit according to the worst simulation result of the target circuit, so that the resources consumed during industrial verification of the target circuit can be effectively saved, and the cost is reduced.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for analyzing performance of an integrated circuit, a simulation device, and a storage medium.
Background
An IP core (internet protocol) core in an integrated circuit design generally refers to a reusable circuit module with a specific function, which is applied in a System on Chip (SoC), and has standardization and accessibility. An IP core that passes industrial verification (sign off) may be implanted directly into an integrated circuit by a system design engineer. Currently, industrial verification of an IP core requires millions of Monte Carlo simulations with high yield (high sigma) to ensure that the yield of the IP core meets the requirement, a large amount of resources are consumed, and the cost is high.
Disclosure of Invention
In view of this, embodiments of the present application provide an integrated circuit performance analysis method, an apparatus, a simulation device, and a storage medium, so as to solve the problem that currently, in an industrial verification of an IP core, millions of high-yield montgocarlo simulations are required to ensure that the yield of the IP core meets requirements, a large amount of resources are required to be consumed, and the cost is high.
A first aspect of an embodiment of the present application provides an integrated circuit performance analysis method, including:
carrying out Monte Carlo simulation on a target circuit for a preset number of times to obtain a simulation result of the target circuit, wherein the preset number of times is far less than the Monte Carlo simulation number of times meeting the high yield requirement;
carrying out variance analysis on the simulation result of the target circuit to obtain a variance analysis result of the target circuit;
determining a key device in the target circuit according to the variation analysis result of the target circuit;
performing Monte Carlo simulation meeting the high yield requirement on the key device according to a preset random number table to obtain a random number combination in the preset random number table corresponding to the worst simulation result of the key device;
carrying out Monte Carlo simulation on the target circuit according to the random number combination to obtain a worst simulation result of the target circuit;
and obtaining a yield analysis result of the target circuit according to the worst simulation result of the target circuit.
A second aspect of an embodiment of the present application provides an integrated circuit performance analysis apparatus, including:
the first simulation unit is used for carrying out Monte Carlo simulation on a target circuit for a preset number of times to obtain a simulation result of the target circuit, wherein the preset number of times is far less than the Monte Carlo simulation number of times meeting the requirement of high yield;
the first analysis unit is used for carrying out variance analysis on the simulation result of the target circuit to obtain a variance analysis result of the target circuit;
the determining unit is used for determining a key device in the target circuit according to the variation analysis result of the target circuit;
the second simulation unit is used for carrying out Monte Carlo simulation meeting the high yield requirement on the key device according to a preset random number table to obtain a random number combination in the preset random number table corresponding to the worst simulation result of the key device;
the third simulation unit is used for carrying out Monte Carlo simulation on the target circuit according to the random number combination to obtain the worst simulation result of the target circuit;
and the second analysis unit is used for obtaining a yield analysis result of the target circuit according to the worst simulation result of the target circuit.
A third aspect of an embodiment of the present application provides an emulation apparatus, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the integrated circuit performance analysis method provided in the first aspect of the embodiment of the present application when executing the computer program.
A fourth aspect of embodiments of the present application provides a computer-readable storage medium, which stores a computer program, and the computer program, when executed by at least one processor, implements the steps of the method for analyzing performance of an integrated circuit provided by the first aspect of embodiments of the present application.
A first aspect of an embodiment of the present application provides an integrated circuit performance analysis method, in which a simulation result of a target circuit is obtained by performing monte carlo simulation on the target circuit for a preset number of times, where the preset number of times is much smaller than the number of monte carlo simulation times meeting a high yield requirement; carrying out variance analysis on the simulation result of the target circuit to obtain a variance analysis result of the target circuit; determining a key device in the target circuit according to the variation analysis result of the target circuit; carrying out Monte Carlo simulation which meets the high yield requirement on the key device according to a preset random number table to obtain a random number combination in the preset random number table corresponding to the worst simulation result of the key device; carrying out Monte Carlo simulation on the target circuit according to the random number combination to obtain the worst simulation result of the target circuit; and obtaining a yield analysis result of the target circuit according to the worst simulation result of the target circuit, thereby effectively saving resources consumed during industrial verification of the target circuit and reducing the cost.
It is understood that the beneficial effects of the second to fourth aspects can be seen from the description of the first aspect, and are not described herein again.
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In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic flow chart diagram illustrating a method for analyzing performance of an integrated circuit according to an embodiment of the present disclosure;
FIG. 2 is a circuit diagram of an IP core of an SRAM provided in an embodiment of the present application;
FIG. 3 is a table of parameters for Monte Carlo simulation of read current for an IP core of an SRAM provided in an embodiment of the present application;
FIG. 4 is a schematic structural diagram of an apparatus for analyzing performance of an integrated circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of an emulation apparatus provided in an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
The embodiment of the application provides an integrated circuit performance analysis method, which can be applied to any simulation computing equipment which has a data processing function and can simulate an integrated circuit to realize performance analysis. The simulation device may be a tablet computer, a notebook computer, a personal computer, a netbook, a server, and the like, and the specific type of the simulation device is not limited in any way in the embodiments of the present application.
As shown in fig. 1, the method for analyzing performance of an integrated circuit according to the embodiment of the present application includes the following steps S101 to S106:
step S101, Monte Carlo simulation is carried out on a target circuit for preset times to obtain a simulation result of the target circuit, wherein the preset times are far smaller than the Monte Carlo simulation times meeting the high yield requirement.
In application, the target circuit may be any integrated circuit that needs to be analyzed, for example, an IP core of a Static Random-Access Memory (SRAM). The preset times can be set by a user according to actual needs in a self-defining way or by default. The number of Monte Carlo simulations meeting the high yield requirement is usually several million, and the preset number should be set to be much less than several million, so as to reduce the calculation resources consumed when Monte Carlo simulations are performed on the target circuit. The preset number of times may be set to thousands of times, for example, any value from 2000 times to 5000 times, and may specifically be 3000 times.
In application, the simulation device may include at least one human-computer interaction device of an entity key, a touch sensor, a gesture recognition sensor, and a voice recognition unit, so that a user may input an analog number setting instruction in a corresponding touch manner, gesture control manner, or voice control manner, for setting a preset number. The physical keys and the touch sensor can be arranged at any position of the simulation equipment, such as a control panel. The touch manner of the physical key may be pressing or toggling. The touch manner of the touch sensor may be pressing or touching. The gesture recognition sensor may be disposed at any location outside of the housing of the emulation device. The gesture for controlling the simulation device can be set by a user according to actual needs in a user-defined mode or default setting of the user in factory. The voice recognition unit may include a microphone and a voice recognition chip, or may include only a microphone and implement a voice recognition function by a processor of the simulation device. The voice for controlling the simulation equipment can be set by the user according to actual needs in a self-defining way or by default when the user leaves a factory.
In one embodiment, before step S101, the method includes:
receiving an analog frequency setting instruction;
and setting preset times according to the simulation time setting instruction.
Step S102, carrying out variance analysis on the simulation result of the target circuit to obtain a variance analysis result of the target circuit;
and S103, determining a key device in the target circuit according to the variation analysis result of the target circuit.
In application, after Monte Carlo simulation is carried out on a target circuit for a few times, Variance Analysis (ANOVA) is carried out on the target circuit according to a simulation result to obtain a corresponding Variance Analysis result, and then a key device which has a large influence on the Variance of the target circuit in the target circuit is determined according to the Variance Analysis result.
In one embodiment, step S103 includes:
and determining a key device in the target circuit, which enables the variance not to be within the variance threshold range, according to the variance of the target circuit in the variance analysis result.
In application, a target circuit is subjected to Monte Carlo simulation for a preset number of times, so that a simulation value equal to the preset number of times can be obtained, and simultaneously, samples equal to the preset number of times are adopted to perform Monte Carlo simulation on the target circuit, each sample comprises simulation parameters of all devices in the target circuit, the simulation parameters of the devices are random numbers, and a table formed by all the simulation parameters can be called a random number table or a random number table. The variance in the variance analysis result of the target circuit refers to the variance (i.e., variance) obtained from the analog value and the standard value. According to the size of the variation in the variation analysis result of the target circuit and the simulation parameters of all devices in the target variation circuit, it can be determined which devices have larger fluctuation of the simulation parameters when the variation is larger (that is, the variation is not within the variation threshold range), and the device with larger fluctuation of the simulation parameters is the key device which has larger influence on the variation of the target circuit.
Step S104, performing Monte Carlo simulation meeting high yield requirements on the key device according to a preset random number table, and obtaining a random number combination in the preset random number table corresponding to the worst simulation result of the key device;
s105, performing Monte Carlo simulation on the target circuit according to the random number combination to obtain a worst simulation result of the target circuit;
and S106, obtaining a yield analysis result of the target circuit according to the worst simulation result of the target circuit.
In application, the preset random number table is determined according to a high yield requirement on a key device, the simulation parameter in the preset random number table is used for Monte Carlo simulation of the key device with high yield, the simulation parameter in the preset random number table is a random number, and the preset random number table can be called as a preset random number table. After determining the key devices which have a large influence on the variation number in the target circuit, firstly, carrying out Monte Carlo simulation which meets the high yield requirement on the key devices, namely carrying out Monte Carlo simulation on the key devices for millions of times to obtain the simulation results of the key devices; then, the worst simulation result is screened out from the simulation results, and a random number combination in a preset random number table corresponding to the worst simulation result of the key device is obtained; then, carrying out Monte Carlo simulation on the target circuit according to a small number of simulation parameters in the random number combination to obtain the worst simulation result of the target circuit; finally, only comparing the simulation value in the worst simulation result of the target circuit with the standard value meeting the high yield requirement can determine whether the target circuit meets the high yield requirement, and compared with the method of directly carrying out Monte Carlo simulation on the whole target circuit in millions of levels, the method can effectively reduce the calculation power resource required to be consumed and save the cost.
In application, a user can input a random number table setting instruction through a human-computer interaction device of the simulation equipment so as to set a random number table used for Monte Carlo simulation meeting high yield requirements on a key device as a preset random number table.
In one embodiment, before step S104, the method includes:
and determining the preset random number table according to the high yield requirement of the key device.
In one embodiment, before step S104, the method includes:
receiving a random number table setting instruction;
and setting a preset random number table according to the random number table setting instruction.
In application, after the simulation equipment obtains a yield analysis result of the target circuit, the yield analysis result can be output through the human-computer interaction device so as to inform a user. The man-machine interaction device can also comprise a display screen, so that the simulation equipment can output the yield analysis result of the target circuit in a voice playing or display mode.
In one embodiment, after step S106, the method includes:
and outputting a yield analysis result of the target circuit.
In one embodiment, step S101 includes:
carrying out Monte Carlo simulation on the read current of an IP core of a static random access memory for preset times to obtain the simulated read current of the IP core;
step S103 includes:
and determining key devices in a driving pipe, a transmission pipe and a load pipe of the IP core, wherein the variation is not in the variation threshold range, according to the variation of the analog read current of the IP core.
In application, the target circuit may be an IP core of a static random access memory, the integrated circuit performance analysis method may be specifically configured to verify a read current (read current) of the IP core, and perform montgocarlo simulation on the read current of the IP core for a preset number of times to obtain corresponding simulated read currents equal to the preset number of times, and then obtain a corresponding number of variance numbers obtained by the simulated read currents and the standard read currents, and determine which devices among the driving transistor, the transmission transistor, and the load transistor have large fluctuation of simulation parameters when the variance numbers are large (that is, the variance numbers are not within a variance number threshold range) according to the magnitude of the variance numbers and the simulation parameters of the driving transistor, the transmission transistor, and the load transistor in the IP core, where the device with large fluctuation of simulation parameters is a key device having a large influence on the change of the variance numbers of the IP core.
In an application, an IP core of a common sram generally includes six transistors, i.e., two driver transistors, two pass transistors, and two load transistors.
As shown in fig. 2, the circuit structure of an IP core of a static random access memory including six transistors is exemplarily shown; the IP core comprises a first transmission pipe PG1, a second transmission pipe PG2, a first driving pipe PD1, a second driving pipe PD2, a first load pipe PU1 and a second load pipe PU 2;
the input end of a first transmission tube PG1 is electrically connected with a first bit line BL, the output end of the first transmission tube PG1 is respectively electrically connected with the input end of a first driving tube PD1, the output end of a first load tube PU1, the controlled end of a second driving tube PD2 and the controlled end of a second load tube PU2, and the control end of a first transmission tube PG1 is electrically connected with a word line WL;
the input end of a second pass tube PG2 is electrically connected with a second bit line BLB, the output end of the second pass tube PG2 is respectively and electrically connected with the input end of a second drive tube PD2, the output end of a second load tube PU2, the controlled end of the first drive tube PD1 and the controlled end of a first load tube PG1, and the control end of a second pass tube PG2 is connected with a word line WL;
the output end of the first driving tube PD1 and the output end of the second driving tube PD2 are grounded GND;
the input end of the first load tube PU1 and the input end of the second load tube PU2 are connected with the power supply VDD.
As shown in fig. 3, a parameter table for performing 3000 monte carlo simulations on the read current of the IP core of the sram is exemplarily shown, where data in a column corresponding to each transistor of the first pass transistor PG1, the second pass transistor PG2, the first drive transistor PD1, the second drive transistor PD2, the first load transistor PU1 and the second load transistor PU2 includes 3000 simulation parameters for performing the monte carlo simulations, and data in a column corresponding to the read current includes 3000 simulation read currents.
From the parameter table shown in fig. 3, it can be seen that the key devices in the IP core of the sram include the first pass transistor PG1 and the first drive transistor PD 1.
According to the integrated circuit performance analysis method provided by the embodiment of the application, a target circuit is subjected to Monte Carlo simulation for a few times to obtain a simulation result of the target circuit; then carrying out variation analysis on the simulation result of the target circuit to obtain a variation analysis result of the target circuit; then, determining a key device in the target circuit according to the variation analysis result of the target circuit, and carrying out Monte Carlo simulation meeting the high yield requirement on the key device according to a preset random table to obtain a random combination in the preset random table corresponding to the worst simulation result of the key device; and finally, carrying out Monte Carlo simulation on the target circuit according to the random number combination to obtain the worst simulation result of the target circuit, and obtaining the yield analysis result of the target circuit according to the worst simulation result of the target circuit, so that the resources consumed during industrial verification of the target circuit can be effectively saved, and the cost is reduced.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
As shown in fig. 4, the present application further provides an integrated circuit performance analysis apparatus for performing the steps in the lighting control embodiment. The integrated circuit performance analysis device may be a virtual appliance (virtual application) in the simulation apparatus, which is executed by a processor of the simulation apparatus, or may be the simulation apparatus itself.
As shown in fig. 4, an integrated circuit performance analysis apparatus 100 according to an embodiment of the present application includes:
the first simulation unit 101 is configured to perform Monte Carlo simulation on a target circuit for a preset number of times to obtain a simulation result of the target circuit, where the preset number of times is much smaller than the Monte Carlo simulation number of times meeting a high yield requirement;
a first analyzing unit 102, configured to perform variance analysis on the simulation result of the target circuit to obtain a variance analysis result of the target circuit;
a determining unit 103, configured to determine a key device in the target circuit according to a variance analysis result of the target circuit;
the second simulation unit 104 is configured to perform monte carlo simulation meeting the high yield requirement on the key device according to a preset random number table, and obtain a random number combination in the preset random number table corresponding to the worst simulation result of the key device;
a third simulation unit 105, configured to perform a monte carlo simulation on the target circuit according to the random number combination, so as to obtain a worst simulation result of the target circuit;
and the second analysis unit 106 is configured to obtain a yield analysis result of the target circuit according to the worst simulation result of the target circuit.
In one embodiment, the integrated circuit performance analysis apparatus further comprises:
a receiving unit for receiving an analog number setting instruction;
and the setting unit is used for setting the preset times according to the simulation time setting instruction.
In one embodiment, the determining unit is further configured to determine the preset random number table according to a high yield requirement for the critical device.
In one embodiment, the receiving unit is further configured to receive a random number table setting instruction;
the setting unit is also used for setting a preset random number table according to the random number table setting instruction.
In one embodiment, the integrated circuit performance analysis apparatus further comprises:
and the output unit is used for outputting the yield analysis result of the target circuit.
In application, each module in the integrated circuit performance analysis apparatus may be a software program module, may be implemented by different logic circuits integrated in a processor, and may also be implemented by a plurality of distributed processors.
As shown in fig. 5, an embodiment of the present application further provides a simulation apparatus 200 including: at least one processor 201 (only one processor is shown in fig. 5), a memory 202, and a computer program 203 stored in the memory 202 and executable on the at least one processor 201, the steps in the various integrated circuit performance analysis method embodiments described above being implemented when the computer program 203 is executed by the processor 201.
In an application, the emulation device can include, but is not limited to, a processor, a memory. Those skilled in the art will appreciate that fig. 5 is merely an example of an emulation device and does not constitute a limitation of an emulation device, and may include more or fewer components than those shown, or some components in combination, or different components, such as input output devices, network access devices, etc. The input and output device may comprise the human-computer interaction device, and when the human-computer interaction device comprises a display screen, the display screen is used for displaying the working parameters of the simulation device. The network access device may include a communication module to communicate the emulation device with the user terminal.
In an Application, the Processor may be a Central Processing Unit (CPU), and the Processor may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
In an application, the storage may in some embodiments be an internal storage unit of the emulation device, such as a hard disk or a memory of the emulation device. The memory may also be an external storage device of the emulation device in other embodiments, such as a plug-in hard disk provided on the emulation device, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory may also include both internal storage units of the emulation device and external storage devices. The memory is used for storing an operating system, application programs, a BootLoader (BootLoader), data, and other programs, such as program codes of computer programs. The memory may also be used to temporarily store data that has been output or is to be output.
In application, the Display screen may be a Thin Film Transistor Liquid Crystal Display (TFT-LCD), a Liquid Crystal Display (LCD), an Organic electroluminescent Display (OLED), a Quantum Dot Light Emitting diode (QLED) Display screen, or the like.
In application, the Communication module may be configured as any device capable of performing wired or Wireless Communication with a client directly or indirectly according to actual needs, for example, the Communication module may provide a solution for Communication applied to a network device, including Wireless Local Area Network (WLAN) (e.g., Wi-Fi network), bluetooth, Zigbee, mobile Communication network, Global Navigation Satellite System (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), Infrared (Infrared, IR), and the like. The communication module may include an antenna, and the antenna may have only one array element, or may be an antenna array including a plurality of array elements. The communication module can receive electromagnetic waves through the antenna, frequency-modulate and filter electromagnetic wave signals, and send the processed signals to the processor. The communication module can also receive a signal to be sent from the processor, frequency-modulate and amplify the signal, and convert the signal into electromagnetic waves through the antenna to radiate the electromagnetic waves.
It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/modules, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and reference may be made to the part of the embodiment of the method specifically, and details are not described here.
It will be clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely illustrated, and in practical applications, the above function distribution may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to perform all or part of the above described functions. Each functional module in the embodiments may be integrated into one processing module, or each module may exist alone physically, or two or more modules are integrated into one module, and the integrated module may be implemented in a form of hardware, or in a form of software functional module. In addition, specific names of the functional modules are only used for distinguishing one functional module from another, and are not used for limiting the protection scope of the application. The specific working process of the modules in the system may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
An embodiment of the present application further provides a simulation device, where the simulation device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, the processor implementing the steps in the various integrated circuit performance analysis method embodiments described above when executing the computer program.
The embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program can implement the steps in the above-mentioned embodiments of the integrated circuit performance analysis method.
Embodiments of the present application provide a computer program product, which, when running on a simulation device, enables the simulation device to implement the steps in the above-mentioned embodiments of the integrated circuit performance analysis method when executed.
The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or apparatus capable of carrying computer program code to the photo emulation device, the recording medium, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, and software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed simulation apparatus and method may be implemented in other ways. For example, the above-described embodiment of the simulation apparatus is merely illustrative, and for example, the division of the modules is only one logical functional division, and there may be other divisions when the actual implementation is performed, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A method for analyzing performance of an integrated circuit, comprising:
carrying out Monte Carlo simulation on a target circuit for a preset number of times to obtain a simulation result of the target circuit, wherein the preset number of times is far less than the Monte Carlo simulation number of times meeting the high yield requirement;
carrying out variance analysis on the simulation result of the target circuit to obtain a variance analysis result of the target circuit;
determining a key device in the target circuit according to the variation analysis result of the target circuit;
performing Monte Carlo simulation meeting the high yield requirement on the key device according to a preset random number table to obtain a random number combination in the preset random number table corresponding to the worst simulation result of the key device;
carrying out Monte Carlo simulation on the target circuit according to the random number combination to obtain a worst simulation result of the target circuit;
and obtaining a yield analysis result of the target circuit according to the worst simulation result of the target circuit.
2. The method of analyzing performance of an integrated circuit of claim 1, wherein said determining critical devices in the target circuit based on the variance analysis of the target circuit comprises:
and determining a key device in the target circuit, which enables the variance not to be within the variance threshold range, according to the variance of the target circuit in the variance analysis result.
3. The method of analyzing performance of an integrated circuit of claim 1, wherein before performing Monte Carlo simulation on the critical device according to a predetermined random number table to obtain a random number combination in the predetermined random number table corresponding to a worst simulation result of the critical device, the method comprises:
and determining the preset random number table according to the high yield requirement of the key device.
4. The method of analyzing performance of an integrated circuit of any of claims 1 to 3, wherein the performing a predetermined number of Monte Carlo simulations on the target circuit to obtain the simulation result of the target circuit comprises:
carrying out Monte Carlo simulation on the read current of an IP core of the static random access memory for preset times to obtain the simulated read current of the IP core.
5. The method of analyzing performance of an integrated circuit of claim 4, wherein said determining critical devices in the target circuit based on the variance analysis of the target circuit comprises:
and determining key devices in a driving pipe, a transmission pipe and a load pipe of the IP core, wherein the variation is not in the variation threshold range, according to the variation of the analog read current of the IP core.
6. The integrated circuit performance analysis method of claim 4, wherein the IP core comprises a first transmission pipe, a second transmission pipe, a first driving pipe, a second driving pipe, a first load pipe and a second load pipe;
the input end of the first transmission tube is electrically connected with a first bit line, the output end of the first transmission tube is respectively and electrically connected with the input end of the first driving tube, the output end of the first load tube, the controlled end of the second driving tube and the controlled end of the second load tube, and the control end of the first transmission tube is electrically connected with a word line;
the input end of the second transmission tube is electrically connected with a second bit line, the output end of the second transmission tube is respectively electrically connected with the input end of the second driving tube, the output end of the second load tube, the controlled end of the first driving tube and the controlled end of the first load tube, and the control end of the second transmission tube is connected with a word line;
the output end of the first driving tube and the output end of the second driving tube are grounded;
the input end of the first load tube and the input end of the second load tube are connected with a power supply.
7. The method of integrated circuit performance analysis of claim 6, wherein the critical component comprises the first transfer tube and the first drive tube.
8. An integrated circuit performance analysis apparatus, comprising:
the first simulation unit is used for carrying out Monte Carlo simulation on a target circuit for a preset number of times to obtain a simulation result of the target circuit, wherein the preset number of times is far less than the Monte Carlo simulation number of times meeting the requirement of high yield;
the first analysis unit is used for carrying out variance analysis on the simulation result of the target circuit to obtain a variance analysis result of the target circuit;
the determining unit is used for determining a key device in the target circuit according to the variation analysis result of the target circuit;
the second simulation unit is used for carrying out Monte Carlo simulation meeting the high yield requirement on the key device according to a preset random number table to obtain a random number combination in the preset random number table corresponding to the worst simulation result of the key device;
the third simulation unit is used for carrying out Monte Carlo simulation on the target circuit according to the random number combination to obtain the worst simulation result of the target circuit;
and the second analysis unit is used for obtaining a yield analysis result of the target circuit according to the worst simulation result of the target circuit.
9. Simulation device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor realizes the steps of the integrated circuit performance analysis method according to any of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by at least one processor, implements the steps of the integrated circuit performance analysis method of any one of claims 1 to 7.
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