CN105261389B - Improve method, circuit and the DRAM memory of input clock duty ratio immunity - Google Patents
Improve method, circuit and the DRAM memory of input clock duty ratio immunity Download PDFInfo
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- CN105261389B CN105261389B CN201510785063.7A CN201510785063A CN105261389B CN 105261389 B CN105261389 B CN 105261389B CN 201510785063 A CN201510785063 A CN 201510785063A CN 105261389 B CN105261389 B CN 105261389B
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Abstract
The present invention relates to the method, circuit and the DRAM memories that improve input clock duty ratio immunity, wherein circuit includes increasing duty cycle circuit, reducing duty cycle circuit and decision circuitry, increase duty cycle circuit to be used to carry out duty ratio increase processing to required clock Clk_G, obtains increasing duty cycle clock Clk_G+；The reduction duty cycle circuit is used to carry out duty ratio reduction processing to required clock Clk_G, obtains reducing duty cycle clock Clk_G-；Decision circuitry adjusts input clock receiver according to judging result for judging required clock Clk_G, increase duty cycle clock Clk_G+, reducing whether duty cycle clock Clk_G- has loss.The present invention, which solves existing clock path, there is technical issues that loss of clock or control circuit, the present invention can greatly improve the immunity to input clock duty ratio.
Description
Technical field
The invention belongs to semiconductor chip design fields, and in particular to the circuit of raising input clock duty ratio immunity,
DRAM memory and method.
Background technique
Computer and various electronic equipments are widely used in the various aspects of the modern life, to semiconductor chip demand
It is increasing.People are getting faster rate request, and chip clock with regard to smaller and smaller, done by small by the clock that system provides
Disturbing can all cause the generation of input clock duty ratio to arrive very much variation.And the variation of input clock duty ratio easily leads to chip functions event
Barrier.A kind of design method proposed by the present invention can greatly improve semiconductor chip to the immunity of input clock duty ratio,
Improve the reliability of chip.Fig. 1 often uses the basic framework of semiconductor chip clock path, including input clock receiver, clock
Device for switching, digital delay phase-locked loop, control circuit and test circuit.
1, external system clock VCLK is firstly inputted clock recipient and receives to generate internal clocking clk_i；
2, clock Clk_G needed for internal clocking CLK_i generates each functional module first place by clock switch electric appliance S；By
It can change in external system clock duty ratio, and input clock recipient and clock switch electric appliance S can allow duty in chip
It is further exacerbated by than variation.So as to cause clock needed for functional module each in piece it is imperfect in addition lose so that chip send out
Raw functional fault.
Summary of the invention
There is technical issues that loss of clock or control circuit to solve existing clock path, the present invention
A kind of circuit and method for improving input clock duty ratio immunity is provided, the present invention can greatly be improved and be accounted for input clock
The immunity of empty ratio.
Technical solution of the invention:
The circuit for improving input clock duty ratio immunity is characterized in that including increasing duty cycle circuit, reducing
Duty cycle circuit and decision circuitry,
The increase duty cycle circuit is used to carry out duty ratio increase processing to required clock Clk_G, obtains increasing duty
Than clock Clk_G+；
The reduction duty cycle circuit is used to carry out duty ratio reduction processing to required clock Clk_G, obtains reducing duty
Than clock Clk_G-；
The decision circuitry is for judging required clock Clk_G, increasing duty cycle clock Clk_G+, reduction duty cycle clock
Whether Clk_G- has loss, and adjusts input clock receiver according to judging result.
Above-mentioned increase duty cycle circuit includes adjusting driving tube, and the adjusting driving tube p/n ratio is greater than on the path Clk_G
P/n ratio.
Above-mentioned reduction duty cycle circuit includes adjusting driving tube, and the adjusting driving tube p/n ratio is less than on the path Clk_G
P/n ratio.
Above-mentioned decision circuitry includes three clock counters.
To the DRAM memory of the high immunity of duty ratio, including input clock receiver, clock switch electric appliance, digital delay
Phaselocked loop, control circuit and test circuit, external system clock vclk generate internal clocking clk_ by input clock recipient
i；Clock Clk_G needed for internal clocking clk_i is generated by clock switch electric appliance；Required clock Clk_G respectively enters number and prolongs
Slow phaselocked loop, control circuit and test circuit.
Above-mentioned increase duty cycle circuit includes adjusting driving tube, and the adjusting driving tube p/n ratio is greater than on the path Clk_G
P/n ratio.
Above-mentioned reduction duty cycle circuit includes adjusting driving tube, and the adjusting driving tube p/n ratio is less than on the path Clk_G
P/n ratio.
Above-mentioned decision circuitry includes three clock counters.
Improve input clock duty ratio immunity method, be characterized in that the following steps are included:
1) duty ratio increase processing is carried out to required clock Clk_G, obtains increasing duty cycle clock Clk_G+；Simultaneously to right
Required clock Clk_G carries out duty ratio reduction processing, obtains reducing duty cycle clock Clk_G-；
2) judge:
Clock Clk_G needed for judging, increase duty cycle clock Clk_G+, reduce duty cycle clock Clk_G- and whether have and lose
It loses；
3) it adjusts:
Input clock receiver is adjusted according to judging result.
Above-mentioned steps 3) specifically:
It is not lost if increasing duty cycle clock Clk_G+ and reducing duty cycle clock Clk_G-, when not adjusting input
Clock receiver；
It is lost if reducing duty cycle clock Clk_G- and existing, adjusts input clock receiver, so that input clock receives
The duty ratio for the internal clocking CLK_i that device generates increases；
It is lost if increasing duty cycle clock Clk_G+ and existing, adjusts input clock receiver, so that input clock receives
The duty ratio for the internal clocking CLK_i that device generates reduces.
Of the invention is had an advantage in that
The present invention is by adding duty cycle circuit, reducing duty cycle circuit and decision circuitry, according to judging result realization pair
Input clock receiver is adjusted, so that Clk_G obtains preferable duty ratio, to improve chip to input clock duty ratio
Immunity.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of existing DRAM memory；
Fig. 2 is the circuit diagram of raising input clock duty ratio immunity of the invention；
Fig. 3 is DRAM memory structure schematic diagram of the present invention to the high immunity of duty ratio；
Fig. 4 is the preferable situation schematic diagram of input clock duty ratio；
Fig. 5 is the lesser situation schematic diagram of input clock duty ratio；
Fig. 6 is the biggish situation schematic diagram of input clock duty ratio.
Specific embodiment
As shown in Fig. 2, improving the circuit of input clock duty ratio immunity, including increases duty cycle circuit, reduces duty
Than circuit and decision circuitry, increases duty cycle circuit and be used to carry out duty ratio increase processing to required clock Clk_G, increased
Add duty cycle clock Clk_G+；Reduce duty cycle circuit to be used to carry out duty ratio reduction processing to required clock Clk_G, be subtracted
Small duty cycle clock Clk_G-；Decision circuitry is accounted for for judging required clock Clk_G, increase duty cycle clock Clk_G+, reducing
Whether sky has loss than clock Clk_G-, and adjusts input clock receiver according to judging result.
The general duty cycle circuit that increases includes adjusting driving tube, (it can be simply by driving tube p/n ratio be adjusted, p is strong
N is weak to be realized)；Reducing duty cycle circuit includes adjusting driving tube.It can be simply by adjusting driving tube p/n ratio, the weak n of p
It is strong to realize)；Decision circuitry includes three clock counters.Increasing duty cycle circuit (can be simply by adjusting driving tube
P/n ratio, p strong n is weak to be realized)；Reduce duty cycle circuit (can come by force simply by adjusting driving tube p/n ratio, the weak n of p
It realizes)；Decision circuitry (can be the counter of simple 3 clocks).
Certainly circuit known to existing many kinds, which can be realized, to be increased duty cycle circuit, reduces duty cycle circuit and judgement
Circuit.
This circuit for improving input clock duty ratio immunity can adjust clock duty cycle using with any need
In system.Using applying the DRAM memory for forming a kind of pair of high immunity of duty ratio in DRAM memory, as shown in figure 3,
Including input clock receiver, clock switch electric appliance, digital delay phase-locked loop, control circuit, test circuit, increase duty ratio electricity
Road reduces duty cycle circuit and decision circuitry.
External system clock VCLK generates internal clocking CLK_i by input clock recipient；Internal clocking CLK_i passes through
Clock Clk_G needed for clock switch electric appliance generates；Required clock Clk_G respectively enter digital delay phase-locked loop, control circuit and
Test circuit.
Concrete operating principle are as follows:
1, when external clock duty is relatively good and is not destroyed by receiver and switching circuit accounting, then increase or
Person, which reduces duty ratio, will not all make loss of clock, such as Fig. 4.Input clock recipient is not adjusted by decision circuitry judgement；
2, when external clock duty is smaller or receiver and switching circuit make duty ratio become smaller, then by reducing duty ratio
Clk_G- will lose after circuit, such as Fig. 5.Input clock recipient can be then adjusted by decision circuitry, so that clock receiver
The clock duty cycle of input increases, so that Clk_G obtains preferable duty ratio, to improve chip to input clock duty ratio
Immunity；
3, when external clock duty is larger or receiver and switching circuit make duty ratio become larger, then by increasing duty ratio
Clk_G+ will lose after circuit, such as Fig. 6.Input clock recipient can be then adjusted by decision circuitry, so that clock receiver
The clock duty cycle of input reduces, so that Clk_G obtains preferable duty ratio, to improve chip to input clock duty ratio
Immunity.
Claims (9)
1. the method for improving input clock duty ratio immunity, it is characterised in that: the following steps are included:
1) duty ratio increase processing is carried out to required clock Clk_G, obtains increasing duty cycle clock Clk_G+；Simultaneously to required
Clock Clk_G carries out duty ratio reduction processing, obtains reducing duty cycle clock Clk_G-；
2) judge:
Clock Clk_G needed for judging, increase duty cycle clock Clk_G+, reduce whether duty cycle clock Clk_G- has loss；
3) it adjusts:
It is not lost if increasing duty cycle clock Clk_G+ and reducing duty cycle clock Clk_G-, does not adjust input clock and connect
Receive device；
It is lost if reducing duty cycle clock Clk_G- and existing, adjusts input clock receiver, so that input clock receiver produces
The duty ratio of raw internal clocking CLK_i increases；
It is lost if increasing duty cycle clock Clk_G+ and existing, adjusts input clock receiver, so that input clock receiver produces
The duty ratio of raw internal clocking CLK_i reduces.
2. realizing the circuit of the method for raising input clock duty ratio immunity described in claim 1, it is characterised in that: including increasing
Add duty cycle circuit, reduce duty cycle circuit and decision circuitry,
The increase duty cycle circuit is used to carry out duty ratio increase processing to required clock Clk_G, when obtaining increasing duty ratio
Clock Clk_G+；
The reduction duty cycle circuit is used to carry out duty ratio reduction processing to required clock Clk_G, when obtaining reducing duty ratio
Clock Clk_G-；
The decision circuitry is for judging required clock Clk_G, increasing duty cycle clock Clk_G+, reduction duty cycle clock Clk_
Whether G- has loss, and adjusts input clock receiver according to judging result.
3. circuit according to claim 2, it is characterised in that: the increase duty cycle circuit includes adjusting driving tube, institute
State the p/n ratio that driving tube p/n ratio is greater than on the path Clk_G that adjusts.
4. circuit according to claim 3, it is characterised in that: the reduction duty cycle circuit includes adjusting driving tube, institute
State the p/n ratio that driving tube p/n ratio is less than on the path Clk_G that adjusts.
5. according to circuit described in Claims 2 or 3 or 4, it is characterised in that: the decision circuitry includes three clock counts
Device.
6. the DRAM memory to the high immunity of duty ratio based on circuit described in claim 2, including input clock receiver,
Clock switch electric appliance, digital delay phase-locked loop, control circuit and test circuit, external system clock vclk connect by input clock
Receiver generates internal clocking clk_i；Clock Clk_G needed for internal clocking clk_i is generated by clock switch electric appliance；Required clock
Clk_G respectively enters digital delay phase-locked loop, control circuit and test circuit.
7. the DRAM memory according to claim 6 to the high immunity of duty ratio, it is characterised in that: the increase duty
It include adjusting driving tube than circuit, the p/n ratio for adjusting driving tube p/n ratio and being greater than on the path Clk_G.
8. the DRAM memory according to claim 7 to the high immunity of duty ratio, it is characterised in that: the reduction duty
It include adjusting driving tube than circuit, the p/n ratio for adjusting driving tube p/n ratio and being less than on the path Clk_G.
9. to the DRAM memory of the high immunity of duty ratio described according to claim 6 or 7 or 8, it is characterised in that: described to sentence
Deenergizing includes three clock counters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510785063.7A CN105261389B (en) | 2015-11-16 | 2015-11-16 | Improve method, circuit and the DRAM memory of input clock duty ratio immunity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510785063.7A CN105261389B (en) | 2015-11-16 | 2015-11-16 | Improve method, circuit and the DRAM memory of input clock duty ratio immunity |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105261389A CN105261389A (en) | 2016-01-20 |
| CN105261389B true CN105261389B (en) | 2019-05-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510785063.7A Active CN105261389B (en) | 2015-11-16 | 2015-11-16 | Improve method, circuit and the DRAM memory of input clock duty ratio immunity |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3772344B2 (en) * | 2002-02-14 | 2006-05-10 | 日本電気株式会社 | Duty ratio adjustment circuit |
| CN102361444A (en) * | 2010-05-24 | 2012-02-22 | 索尼公司 | Clock adjustment circuit, shift detection circuit of duty ratio, imaging device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6529057B2 (en) * | 2001-04-12 | 2003-03-04 | Sun Microsystems, Inc. | Stretching, shortening, and/or removing a clock cycle |
| US7221204B2 (en) * | 2005-02-01 | 2007-05-22 | Infineon Technologies Ag | Duty cycle corrector |
-
2015
- 2015-11-16 CN CN201510785063.7A patent/CN105261389B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3772344B2 (en) * | 2002-02-14 | 2006-05-10 | 日本電気株式会社 | Duty ratio adjustment circuit |
| CN102361444A (en) * | 2010-05-24 | 2012-02-22 | 索尼公司 | Clock adjustment circuit, shift detection circuit of duty ratio, imaging device |
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| Publication number | Publication date |
|---|---|
| CN105261389A (en) | 2016-01-20 |
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Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant before: Xi'an Sinochip Semiconductors Co., Ltd. |
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