CN205177407U - Improve circuit and DRAM memory of input clock duty cycle immunity - Google Patents
Improve circuit and DRAM memory of input clock duty cycle immunity Download PDFInfo
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- CN205177407U CN205177407U CN201520911615.XU CN201520911615U CN205177407U CN 205177407 U CN205177407 U CN 205177407U CN 201520911615 U CN201520911615 U CN 201520911615U CN 205177407 U CN205177407 U CN 205177407U
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Abstract
The utility model relates to an improve circuit and DRAM memory of input clock duty cycle immunity, including increasing the duty cycle circuit, reduce the duty cycle circuit and judging the circuit, increase duty cycle circuit is used for carrying out the duty cycle increase to required clock clk_G to be handled, is increased duty cycle clock clk_G+, reduce the duty cycle circuit and be used for carrying out the duty cycle to required clock clk_G and reduce to handle, reduced duty cycle clock clk_G -, judge that the circuit is used for judging required clock clk_G, increases duty cycle clock clk_G+, reduces duty cycle clock clk_G - whether having and losing to adjust the input clock receiver according to the judged result. The utility model provides a current clock route have that the clock is lost or control circuit dysfunction's technical problem, the utility model discloses improvement that can be very big is to the immunity of input clock duty cycle.
Description
Technical field
The utility model belongs to semiconductor chip design field, is specifically related to the method improving input clock dutycycle immunity.
Background technology
Computing machine and various electronic equipment are widely used in the various aspects of the modern life, increasing to semi-conductor chip demand.People are more and more faster to rate request, and chip clock is just more and more less, and the clock that system provides is subject to small interference and input clock dutycycle all can be caused to occur to arrive very much change.And the change of input clock dutycycle very easily causes chip functions fault.A kind of method for designing that the utility model proposes can improve the immunity of semi-conductor chip to input clock dutycycle greatly, improves the reliability of chip.Fig. 1 commonly uses the basic framework of semi-conductor chip clock path, comprises input clock receiver, clock switch electrical equipment, digital delay phase-locked loop, control circuit and test circuit.
1, first external system clock VCLK is transfused to clock receptacle acceptance generation internal clocking clk_i;
2, internal clocking CLK_i produces clock Clk_G needed for each functional module first place through clock switch electrical equipment S; Because external system clock dutycycle can change, and in chip, input clock receptacle and clock switch electrical equipment S can allow change in duty cycle aggravate further.Thus cause that the clock in sheet needed for each functional module is imperfect even to be lost, make chip generating function fault.
Summary of the invention
Loss of clock or the parafunctional technical matters of control circuit is there is in order to solve existing clock path, the utility model provides a kind of circuit improving input clock dutycycle immunity, and the utility model can greatly improve the immunity to input clock dutycycle.
Technical solution of the present utility model:
Improve the circuit of input clock dutycycle immunity, its special character is: comprise and increase duty cycle circuit, reduction duty cycle circuit and decision circuitry,
Described increase duty cycle circuit is used for carrying out dutycycle to required clock Clk_G increases process, obtains increasing duty cycle clock Clk_G+;
Described reduction duty cycle circuit is used for carrying out dutycycle to required clock Clk_G and reduces process, obtains reducing duty cycle clock Clk_G-;
Described decision circuitry is for judging whether required clock Clk_G, increase duty cycle clock Clk_G+, reduction duty cycle clock Clk_G-have loss, and regulate input clock receiver according to judged result.
Above-mentioned increase duty cycle circuit comprises adjustment driving tube, and described adjustment driving tube p/n ratio is greater than the p/n ratio on Clk_G path.
Above-mentioned reduction duty cycle circuit comprises adjustment driving tube, and described adjustment driving tube p/n ratio is less than the p/n ratio on Clk_G path.
Above-mentioned decision circuitry comprises three clock counters.
To the DRAM storer of dutycycle high immunity, comprise input clock receiver, clock switch electrical equipment, digital delay phase-locked loop, control circuit and test circuit, external system clock vclk produces internal clocking clk_i through input clock receptacle; Internal clocking clk_i produces required clock Clk_G through clock switch electrical equipment; Required clock Clk_G enters digital delay phase-locked loop, control circuit and test circuit respectively.
Above-mentioned increase duty cycle circuit comprises adjustment driving tube, and described adjustment driving tube p/n ratio is greater than the p/n ratio on Clk_G path.
Above-mentioned reduction duty cycle circuit comprises adjustment driving tube, and described adjustment driving tube p/n ratio is less than the p/n ratio on Clk_G path.
Above-mentioned decision circuitry comprises three clock counters.
Improve the method for input clock dutycycle immunity, its special character is: comprise the following steps:
1) dutycycle is carried out to required clock Clk_G and increase process, obtain increasing duty cycle clock Clk_G-+; Reduce process to carrying out dutycycle to required clock Clk_G simultaneously, obtain reducing duty cycle clock Clk_G-;
2) judge:
Judge whether required clock Clk_G, increase duty cycle clock Clk_G+, reduction duty cycle clock Clk_G-have loss;
3) regulate:
Input clock receiver is regulated according to judged result.
Above-mentioned steps 3) be specially:
All do not lose if increase duty cycle clock Clk_G+ and reduce duty cycle clock Clk_G-, then do not adjust input clock receiver;
If reduce duty cycle clock Clk_G-to there is loss, then adjust input clock receiver, the dutycycle of the internal clocking CLK_i that input clock receiver is produced increases;
If increase duty cycle clock Clk_G+ to there is loss, then adjust input clock receiver, the dutycycle of the internal clocking CLK_i that input clock receiver is produced reduces.
Had advantage of the present utility model:
The utility model is by adding duty cycle circuit, reducing duty cycle circuit and decision circuitry, realize regulating input clock receiver according to judged result, make Clk_G obtain good dutycycle, thus improve chip to the immunity of input clock dutycycle.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing DRAM storer;
Fig. 2 is the circuit diagram of raising input clock dutycycle immunity of the present utility model;
Fig. 3 is the DRAM memory construction schematic diagram of the utility model to dutycycle high immunity;
Fig. 4 is the good situation schematic diagram of input clock dutycycle;
Fig. 5 is the smaller situation schematic diagram of input clock duty;
Fig. 6 is the situation schematic diagram that input clock dutycycle is larger.
Embodiment
As shown in Figure 2, improve the circuit of input clock dutycycle immunity, comprise and increase duty cycle circuit, reduction duty cycle circuit and decision circuitry, increase duty cycle circuit and be used for carrying out dutycycle increase process to required clock Clk_G, obtain increase duty cycle clock Clk_G+; Reduce duty cycle circuit to be used for carrying out dutycycle reduction process to required clock Clk_G, obtain reducing duty cycle clock Clk_G-; Decision circuitry is for judging whether required clock Clk_G, increase duty cycle clock Clk_G+, reduction duty cycle clock Clk_G-have loss, and regulate input clock receiver according to judged result.
General increase duty cycle circuit comprises adjustment driving tube, (can simply by adjustment driving tube p/n ratio, the strong n of p is weak to be realized); Reduce duty cycle circuit and comprise adjustment driving tube.Can simply by adjustment driving tube p/n ratio, the weak n of p realizes by force); Decision circuitry comprises three clock counters.Increase duty cycle circuit (can simply by adjustment driving tube p/n ratio, the strong n of p is weak to be realized); Reduce duty cycle circuit (can simply by adjustment driving tube p/n ratio, the weak n of p realizes by force); Decision circuitry (can be the counter of simple 3 clocks).
Certain existing a variety of known circuit can realize increasing duty cycle circuit, reducing duty cycle circuit and decision circuitry.
The circuit of this raising input clock dutycycle immunity can be applied and regulate in the system of clock duty cycle with any needs.Utilize to be applied in DRAM storer and form a kind of DRAM storer to dutycycle high immunity, as shown in Figure 3, comprise input clock receiver, clock switch electrical equipment, digital delay phase-locked loop, control circuit, test circuit, increase duty cycle circuit, reduce duty cycle circuit and decision circuitry.
External system clock VCLK produces internal clocking CLK_i through input clock receptacle; Internal clocking CLK_i produces required clock Clk_G through clock switch electrical equipment; Required clock Clk_G enters digital delay phase-locked loop, control circuit and test circuit respectively.
Specific works principle is:
1, when external clock dutycycle better and be not destroyed through receiver and on-off circuit accounting, then increase or reduce dutycycle and all can not make loss of clock, as Fig. 4.Judge not adjust input clock receptacle through decision circuitry;
2, when external clock duty is less or receiver and on-off circuit make dutycycle diminish, then after reducing duty cycle circuit, Clk_G-will lose, as Fig. 5.Then can adjust input clock receptacle through decision circuitry, the clock duty cycle that clock receiver is inputted increases, and makes Clk_G obtain good dutycycle, thus improves chip to the immunity of input clock dutycycle;
3, when external clock duty is comparatively large or receiver and on-off circuit make dutycycle become large, then after increasing duty cycle circuit, Clk_G+ will lose, as Fig. 6.Then can adjust input clock receptacle through decision circuitry, the clock duty cycle that clock receiver is inputted reduces, and makes Clk_G obtain good dutycycle, thus improves chip to the immunity of input clock dutycycle.
Claims (8)
1. improve the circuit of input clock dutycycle immunity, it is characterized in that: comprise and increase duty cycle circuit, reduction duty cycle circuit and decision circuitry,
Described increase duty cycle circuit is used for carrying out dutycycle to required clock Clk_G increases process, obtains increasing duty cycle clock Clk_G+;
Described reduction duty cycle circuit is used for carrying out dutycycle to required clock Clk_G and reduces process, obtains reducing duty cycle clock Clk_G-;
Described decision circuitry is for judging whether required clock Clk_G, increase duty cycle clock Clk_G+, reduction duty cycle clock Clk_G-have loss, and regulate input clock receiver according to judged result.
2. the circuit of raising input clock dutycycle immunity according to claim 1, is characterized in that: described increase duty cycle circuit comprises adjustment driving tube, and described adjustment driving tube p/n ratio is greater than the p/n ratio on Clk_G path.
3. the circuit of raising input clock dutycycle immunity according to claim 2, is characterized in that: described reduction duty cycle circuit comprises adjustment driving tube, and described adjustment driving tube p/n ratio is less than the p/n ratio on Clk_G path.
4. the circuit of the raising input clock dutycycle immunity according to claim 1 or 2 or 3, is characterized in that: described decision circuitry comprises three clock counters.
5. based on the DRAM storer to dutycycle high immunity of the arbitrary described circuit of claim 1-4, comprise input clock receiver, clock switch electrical equipment, digital delay phase-locked loop, control circuit and test circuit, external system clock vclk produces internal clocking clk_i through input clock receptacle; Internal clocking clk_i produces required clock Clk_G through clock switch electrical equipment; Required clock Clk_G enters digital delay phase-locked loop, control circuit and test circuit respectively.
6. the DRAM storer to dutycycle high immunity according to claim 5, is characterized in that: described increase duty cycle circuit comprises adjustment driving tube, and described adjustment driving tube p/n ratio is greater than the p/n ratio on Clk_G path.
7. the DRAM storer to dutycycle high immunity according to claim 6, is characterized in that: described reduction duty cycle circuit comprises adjustment driving tube, and described adjustment driving tube p/n ratio is less than the p/n ratio on Clk_G path.
8. the DRAM storer to dutycycle high immunity according to claim 5 or 6 or 7, is characterized in that: described decision circuitry comprises three clock counters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520911615.XU CN205177407U (en) | 2015-11-16 | 2015-11-16 | Improve circuit and DRAM memory of input clock duty cycle immunity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520911615.XU CN205177407U (en) | 2015-11-16 | 2015-11-16 | Improve circuit and DRAM memory of input clock duty cycle immunity |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205177407U true CN205177407U (en) | 2016-04-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520911615.XU Active CN205177407U (en) | 2015-11-16 | 2015-11-16 | Improve circuit and DRAM memory of input clock duty cycle immunity |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205177407U (en) |
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2015
- 2015-11-16 CN CN201520911615.XU patent/CN205177407U/en active Active
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| GR01 | Patent grant |