JP3772344B2 - Duty ratio adjustment circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a duty ratio variable circuit that changes the duty ratio of a clock supplied to an LSI. Have The present invention relates to a duty ratio adjustment circuit that adjusts the duty ratio of a clock supplied into an LSI using this duty ratio variable circuit.
[0002]
[Prior art]
Since it is necessary to operate the internal circuit in synchronization within the LSI, a clock is supplied to the entire surface of the LSI. In general, it is desirable to distribute the clock evenly over the entire surface of the LSI. Various distribution methods have been proposed. As an example, the H clock tree method is introduced in Chapter 8 of “VLSI System Design Circuits and Implementation Basics” (translated by Hirozabu Nakamura, directed by Hiroshi Nakamura “Circuits, Interconnections and Packaging for VLSI” published by HB Bakoglu, Addison-Wesley Publishing Company). Has been. There is usually one clock input terminal for the LSI, and any distribution method is used to distribute evenly over the entire surface from there, and a dedicated clock distribution buffer called a clock driver is connected in multiple stages for distribution. The number of stages depends on the LSI size and the like, but may be several to ten or more stages. The clock driver is generally an inverter or a buffer in which inverters are connected in cascade. FIG. 13 is a block diagram showing one system of clock distribution, which is cited and added from the above-mentioned literature. The clock input from the clock input terminal 51 is multiplied by a PLL (phase-locked loop) circuit 52 and distributed in the order of a, b, c, d, and e through the clock driver 53 in the clock tree. In this figure, a three-stage clock driver 53 is used.
[0003]
[Problems to be solved by the invention]
In the conventional clock distribution method described above, the duty ratio of 50% is compensated for in the PLL circuit output. However, in the clock distributed from a to e in the clock tree, the duty ratio deviates from 50% due to process variations. FIG. 14 is a waveform diagram for explaining the situation, and (a) to (e) in FIG. 14 correspond to a to e in FIG. The deviation width of the duty ratio depends on the process, the number of stages, and the distribution method, but may be about +/− 20%. On the other hand, the frequency of clocks is constantly increasing, and even a collapse of about 20% causes serious problems in operation. For example, in the case of a high frequency exceeding 2 GHz, it may happen that the clock is lost without full amplitude at the distribution end. Further, in ordinary logic circuits, only the rising edge of the clock (hereinafter referred to as the rise edge) has been used, but in recent years, the falling edge (hereinafter referred to as the fall edge) is used for further speeding up and multi-function. In this case, if the duty ratio at the distribution end deviates greatly from 50%, there is a possibility that normal operation cannot be performed.
An object of the present invention is to solve the above-described problems of the prior art, and an object of the present invention is to accurately adjust the clock duty ratio at the distribution end to, for example, 50%. Shi Thus, even when the operation speed is increased, the LSI can be stably operated.
[0004]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a distribution end clock signal obtained from a circuit end of a circuit to which a clock is distributed is input, and the clock is delayed in phase based on the duty ratio of the distribution end clock signal. A first type phase lag circuit for outputting a signal as a first type control clock signal;
An inverter to which a clock signal is input, a first type switching element connected between an output line of the inverter and a power source, controlled by the first type control clock signal, and the output line A duty ratio variable circuit having a voltage discrimination circuit for identifying a voltage and outputting a high / low signal;
And a duty ratio adjustment circuit for adjusting a duty ratio of the clock signal.
In order to achieve the above object, according to the present invention, a distribution end clock signal obtained from a circuit end of a circuit to which a clock is distributed is input, and the phase is delayed based on the duty ratio of the distribution end clock signal. A second type of phase lag circuit that outputs the clock signal as a second type of control clock signal;
An inverter to which a clock signal is input, a second type switching element connected between an output line of the inverter and a ground potential, controlled by the second type control clock signal, and a voltage of the output line A duty ratio variable circuit having a voltage discriminating circuit that discriminates and outputs a high / low signal;
And a duty ratio adjustment circuit for adjusting a duty ratio of the clock signal.
In order to achieve the above object, according to the present invention, a distribution end clock signal obtained from a circuit end of a circuit to which a clock is distributed is input, and the phase is delayed based on the duty ratio of the distribution end clock signal. A first type and a second type of phase delay circuit for outputting the two types of clock signals as first and second type control clock signals, respectively;
An inverter to which a clock signal is input, a first type switching element connected between an output line of the inverter and a power source, controlled by the first type control clock signal, and an output of the inverter A second type switching element connected between a line and a ground potential and controlled by the second type control clock signal, and a voltage for identifying a voltage of the output line and outputting a high / low signal A duty ratio variable circuit having a discrimination circuit;
And a duty ratio adjustment circuit for adjusting a duty ratio of the clock signal.
[0005]
In order to achieve the above object, according to the present invention, a distribution end clock signal obtained from a circuit end of a circuit to which a clock is distributed is input, and the phase is delayed based on the duty ratio of the distribution end clock signal. Two types of clock signals, a first type and a second type of phase delay circuit for outputting a first type and a second type of control clock signal, respectively,
A first type inverter to which a clock signal is input, and a first type switching controlled by the first type control clock signal connected between an output line of the first type inverter and a power source. A duty ratio variable circuit of the first type having an element and a voltage discriminating circuit for identifying a voltage of the output line and outputting a high / low signal;
The second type inverter to which the output signal of the first type duty ratio variable circuit is input, and the second type control clock signal connected between the output line of the second type inverter and the ground potential. A second type duty ratio variable circuit comprising: a second type switching element controlled by: a voltage discriminating circuit for identifying a voltage of the output line and outputting a high / low signal;
And a duty ratio adjustment circuit for adjusting a duty ratio of the clock signal.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a duty variable circuit of the present invention. As shown in FIG. 1, the controlled clock S0 is input to the inverter 1 and inverted. The output line of the inverter 1 is connected to a voltage modulation circuit that is controlled by the control clock S1 and the output signal of the inverter 1 is voltage-modulated by this circuit, and the output signal of the output line of the inverter 1 is voltage-modulated. Converted to clock SS0. This voltage modulation clock SS0 is inputted to the voltage discriminating circuit 3 and discriminated into a high / low (logic value “1”, “0”) voltage according to the threshold voltage, thereby adjusting the duty ratio to 50%, for example. Converted to the adjusted clock S2.
Here, the control clock S1 is a signal delayed in phase from the controlled clock S0. The amount of phase delay is determined by the duty ratio of the clock whose duty ratio is adjusted.
[0007]
The inverter 1 and the voltage discriminating circuit 3 are preferably constituted by an inverter having a CMOS configuration. In addition, the voltage modulation circuit 2 has a p-channel MOS transistor (hereinafter referred to as pMOS) in which the control clock S1 is input to the gate, the drain is connected to the output line of the inverter 1 and the source is connected to the power supply, or the gate An n-channel MOS transistor (hereinafter referred to as nMOS) in which S1 is input and a drain is connected to the output line of the inverter 1 and a source is connected to the ground point, or a first control clock is input to the gate and a drain is connected to the inverter 1 The pMOS is connected to the output line, the source is connected to the power supply, the gate is connected to the second control clock, the drain is connected to the output line of the inverter 1, and the source is connected to the ground.
According to the present invention, in the above configuration, by providing the control clock S1 with the phase delay signal of the controlled clock S0, only the rise edge or the fall edge of the clock waveform can be moved, and the clock duty ratio can be arbitrarily set. Can be changed.
[0008]
【Example】
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[First embodiment]
FIG. 2 is a circuit diagram of the duty ratio variable circuit according to the first embodiment of the present invention, and FIG. 3 is a block diagram of the duty ratio adjustment circuit according to the first embodiment of the present invention. As shown in FIG. 2, the controlled clock S0 is input to an inverter INV1 including pMOS Q1, Q2 and nMOS Q3, Q4 connected in series. The control clock S1 is input to the gate of the pMOS Q5 whose source is connected to the power supply and whose drain is connected to the output terminal of the inverter INV1. The voltage modulation clock SS0 generated by being subjected to voltage modulation by the pMOS Q5 is input to an inverter INV2 constituted by a CMOS, and an adjusted clock S2 having an adjusted duty ratio is output from the inverter INV2.
[0009]
FIG. 3 is a block diagram of a duty adjustment circuit including the duty ratio variable circuit shown in FIG. The input clock CLK is input to the delay line 11, and delayed delay clocks S6 and S7 to Sn are output from the delay line 11. The delayed clocks S7 to Sn are input to the selector 13, and the selector 13 selects one of them by the select signal S5 and outputs it as the control clock S1. On the other hand, the delay clock S6 is input to the delay circuit 12. The delay amount of the delay circuit 12 is equal to that of the selector 13, and the delay of the selector 13 is compensated by the delay circuit 12 which is a delay buffer. The controlled clock S0 that is the output signal is input to the duty ratio variable circuit 14 provided by the present invention together with the control clock S1. The adjusted clock S2 that is the output is distributed by the clock distribution network 15. In order to detect the duty of the clock, the distribution end clock S3 is extracted from the end of the clock distribution network 15 and input to the duty ratio detection circuit 16, and the counter 17 is up / down by the output. Then, the selector 13 is switched by the select signal S5 output from the counter 17.
[0010]
Next, the operation of the circuit of this embodiment will be described. First, the operation of the duty ratio variable circuit of FIG. 2 will be described with reference to FIG. 4 which is an operation explanatory diagram and FIG. 5 which is a timing chart. The circuit operations in the periods a, b, c, and d shown in FIG. 5 are shown by (a), (b), (c), and (d) in FIG. In FIG. 5, t1 is the delay time of S1 with respect to S0. In the period a, S0 and S1 are both low level, the pMOS Q1, Q2, and Q5 are turned on, SS0 is high, and S2 is low level. In the period b, when S0 becomes high level, the nMOS Q3 and Q4 are turned on, and current flows through the pMOS Q5. The value Vd is determined by the pressure. This voltage Vd is set higher than the logical threshold value Vt of the inverter INV2 at the subsequent stage. Therefore, S2 remains at a low level throughout the period b. When t1 elapses after S0 becomes high, period c starts, and at the same time as S0, S1 becomes high level and pMOS Q5 is turned off, so that SS0 becomes low level and S2 becomes high level.
[0011]
Therefore, the rising edge of S2 is delayed by the phase difference (t1) between S0 and S1 with respect to S0. On the other hand, regarding the fall edge, since the pMOS Q1 and Q2 are turned on at the same time as the S0 becomes the low level in the period d, the SS0 becomes high and the S2 becomes the low level, so that no phase difference occurs. With the above operation, the adjusted clock S2 in which only the phase of the rising edge is delayed from the phase difference between S0 and S1 with respect to the controlled clock S0 can be extracted. Here, since the potential Vd of the voltage modulation clock SS0 is determined by the DC characteristics of the transistor, the design is easy.
[0012]
Next, the operation of the duty ratio adjusting circuit 100 will be described with reference to FIG. In FIG. 3, delay clocks S6 and S7 to Sn in which the phase of the input clock CLK is delayed by the delay line 11 are created. In S7 to Sn, the delay time increases sequentially at equal intervals. One of the clocks is selected by the selector 13 (hereinafter referred to as Sm) and output as the control clock S1. The delay circuit 12 receives S6 and outputs S0. The delay circuit 12 is for compensating for the delay time that the clocks S7 to Sn appear as S1 through the selector 13, and therefore the delay time is the same as that of the selector 13. As a result, the phase relationship between S0 and S1 is the same as the phase relationship between S6 and Sm. S0 and S1 are input, and the duty ratio variable circuit 14 changes the duty ratio of the clock.
[0013]
The adjusted clock S2 obtained by the duty ratio variable circuit 14 is distributed in the LSI by the clock distribution network 15. The target having a duty ratio of 50% is not the clock S2, but the distribution end clock S3 obtained at another observation point. The distribution end clock S3 is input to the duty ratio detection circuit 16 where the duty ratio is examined. Depending on whether the duty ratio is increased or decreased, an up or down signal is sent to the counter 17, and the counter 17 generates a select signal S5 and drives the selector 13.
The duty ratio variable circuit 14 of this embodiment works only in the direction of lowering the duty ratio of the adjusted S2 with respect to the duty ratio of the controlled clock S0. That is, the circuit of this embodiment cannot increase the duty ratio of the controlled clock S0.
[0014]
[Second Embodiment]
FIG. 6 is a circuit diagram of the duty ratio variable circuit according to the second embodiment of the present invention. In FIG. 6, parts that are the same as those in the circuit of the first embodiment shown in FIG. In this embodiment, instead of the pMOS Q5 of the first embodiment, an nMOS Q6 is connected between the output terminal of the inverter INV1 and the ground. The timings of S0 and S1 inputted to the inverter INV1 and the nMOS Q6 are the same as those in the first embodiment.
In the circuit of this embodiment, as shown in FIG. 7, in the period a, the pMOS Q1, Q2 are turned on, the nMOS Q3, Q4, Q6 are turned off, SS0 is high, and S2 is low level. In the period b, the nMOS Q3 and Q4 are turned on, and in the period c, the nMOS Q3, Q4, and Q6 are turned on, SS0 is low, and S2 is high level. In the period d, since the pMOS Q1 and Q2 are turned on, SS0 becomes a value Vd ′ determined by the resistance voltage division of the on-resistances of the pMOS Q1, Q2 and nMOS Q6. Here, since the logic threshold value Vt of the inverter INV2 is set higher than Vd ′ (the total on-resistance of the pMOS Q1 and Q2 is set higher than the on-resistance of the nMOS Q6), the S2 maintains a high level. To do. When the period d ends, the state returns to the period a.
In the present embodiment, in contrast to the first embodiment, the fall edge side of S2 can be made variable to increase the duty ratio (the duty ratio of the adjusted clock S2 is made higher than that of the controlled clock S0). Cannot be small).
[0015]
[Third embodiment]
In each of the duty ratio variable circuits of the first and second embodiments, the change direction of the duty ratio of S0 is limited to one direction. However, if these are combined, S2 is on either side of S0. The duty ratio can be made variable. FIG. 8 is a block diagram showing the configuration of the duty adjustment circuit 200 according to the third embodiment of the present invention, which is a combination of the two previous embodiments. In FIG. 8, parts that are the same as the parts of the first embodiment shown in FIG. 3 are given the same reference numerals, and redundant descriptions are omitted. In the present embodiment, two duty ratio variable circuits, ie, a first duty ratio variable circuit 141 and a second duty ratio variable circuit 142 are used and are controlled by the counter 17a. The first duty ratio variable circuit 141 uses the duty ratio variable circuit shown in FIG. 6 and the second duty ratio variable circuit 142 uses the duty ratio variable circuit shown in FIG. Control clock S0 ₁ , S0 ₂ And the first and second control clocks S1 ₁ , S1 ₂ And the first and second adjusted clocks S2 ₁ , S2 ₂ Is output. Corresponding to the first and second duty ratio variable circuits 141 and 142, two selectors, a first selector 131 and a second selector 132, are prepared, and their outputs are the first and second control clocks S1. ₁ , S1 ₂ Are input to the first and second duty ratio variable circuits 141 and 142. S0 is input to the first selector 131 in addition to S7 to Sn. In addition to S7 to Sn, the second selector 132 outputs S2 output from the first duty ratio variable times 141. ₁ Is entered. S7 to Sn output from the delay line 11 are input to the second selector 132 via the delay circuit 12a, and S2 output from the first duty ratio variable circuit 141. ₁ Is input to the second duty ratio variable circuit 142 via the delay circuit 12b. The delay circuits 12a and 12b receive the first adjusted clock S2 input to the second duty ratio variable circuit 142. ₁ And the second control clock S1 ₂ The delay circuit 12 a is for compensating for the delay of the first selector 131 and the first duty ratio variable circuit 141, and the delay circuit 12 b is for compensating for the delay of the second selector 132. S2 ₁ The clock delayed by the delay circuit 12b is the second controlled clock S0. ₂ It becomes.
[0016]
Next, the operation of the circuit of this embodiment will be described. When lowering the duty ratio, only the first duty ratio variable circuit 141 side is effectively operated. At this time, in order not to cause the second duty ratio variable circuit 142 to operate effectively, the second selector 132 sets the first adjusted clock S2. ₁ Select. When increasing the duty ratio, only the second duty ratio variable circuit 142 side is effectively operated. At this time, the first selector 131 selects the delay clock S6 so that the first duty ratio variable circuit 141 is not effectively operated. To enable such an operation, the counter 17a causes the second selector 132 to select the first adjusted clock S2 when the first selector 131 selects one of S7 to Sn. ₁ When the second selector 132 selects one of S7 to Sn, a control signal is generated that causes the first selector 131 to select the delay clock S6. With this configuration, the duty ratio can be arbitrarily adjusted.
[0017]
[Fourth embodiment]
FIG. 9 is a circuit diagram of a duty ratio variable circuit used in the fourth embodiment of the present invention, and FIG. 10 is a block diagram showing the configuration of the duty adjustment circuit 300 of the fourth embodiment of the present invention. . 9 and 10, parts that are the same as the parts of the other embodiments are given the same reference numerals, and redundant descriptions are omitted.
As shown in FIG. 9, in the duty ratio variable circuit of this embodiment, a series connection circuit of pMOS Q5 and Q7 is connected between the output terminal of the inverter INV1 and the power supply, and nMOS Q8 is connected between the ground potential. A series connection circuit of Q6 is connected. The gates of Q5 and Q6 have first and second control clocks S1, respectively. ₁ , S1 ₂ Is entered. The switching signal U1 is input to the gates of Q7 and Q8 in common. First control clock S1 ₁ Indicates the rising edge of the second control clock S1. ₂ Is a delay clock for moving the fall edge. U1 is a signal for controlling which edge is moved.
[0018]
Next, the operation of the duty ratio variable circuit of this embodiment shown in FIG. 9 will be described. As in the duty ratio variable circuit of FIG. 2, the switching signal U1 is set to low in order to make the high level period narrow. In this case, since the pMOS Q7 is turned on and the nMOS Q8 is turned off, the circuit is substantially the same as the circuit of FIG. Further, as in the case of the duty ratio variable circuit of FIG. 6, when the clock high level period is to be widened, the switching signal U1 is set to high. As a result, the nMOS Q8 is turned on and the pMOS Q7 is turned off. In this case, the circuit is substantially the same as the circuit of FIG. Since it is determined exclusively whether the high level period of the clock is narrowed or widened, the switching signal U1 can be uniquely determined.
[0019]
FIG. 10 is a block diagram of a duty ratio adjustment circuit 300 using this duty ratio variable circuit. The duty ratio variable circuit 14a is the circuit shown in FIG. In the present embodiment, the first selector 133 and the second selector 134 are used, and the delay clocks S7 to Sn output from the delay line 11 are input to the first and second control clocks S1, respectively. ₁ , S1 ₂ Is output. The switching signal U1 is formed in the counter 17b.
[0020]
[Fifth embodiment]
FIG. 11 is a circuit diagram of a duty ratio variable circuit used in the fifth embodiment of the present invention, and FIG. 12 is a block diagram showing the configuration of the duty adjustment circuit 400 of the fifth embodiment of the present invention. . In FIG. 11 and FIG. 12, parts that are the same as the parts of the other embodiments are given the same reference numerals, and redundant descriptions are omitted.
As shown in FIG. 11, in the duty ratio variable circuit of this embodiment, a pMOS Q5 is connected between the output terminal of the inverter INV1 and the power supply, and an nMOS Q6 is connected between the ground potential. The gates of Q5 and Q6 have first and second control clocks S1, respectively. ₃ , S1 ₄ Is entered. First control clock S1 ₃ Indicates the rising edge of the second control clock S1. ₄ Is a delay clock for moving the fall edge, but when moving the rise edge, S1 ₄ Is placed at a low level and when moving the fall edge, S1 ₃ Is at a high level.
The duty ratio variable circuit of this embodiment shown in FIG. ₄ Is maintained at a low level, it is substantially the same as the circuit of FIG. ₃ Is substantially the same as the circuit of FIG.
[0021]
FIG. 12 is a block diagram of a duty ratio adjustment circuit 400 using this duty ratio variable circuit. The duty ratio variable circuit 14b is a circuit shown in FIG. In this embodiment, two of the first selector 135 and the second selector 136 are used. The power supply potential is input to the first selector 135 in addition to the delay clocks S7 to Sn output from the delay line 11, and the ground potential is input to the second selector 136 in addition to the delay clocks S7 to Sn output from the delay line 11. , And the first selector 135 and the second selector 136 select either one by the select signal S5 output from the counter 17a, and the first and second control clocks S1 ₃ , S1 ₄ Output as.
[0022]
The duty ratio variable circuit of the present invention described above is complicated because the configuration is very simple. Na Does not require timing adjustment. Therefore, no abnormal pulse is generated in the adjusted clock (S2) whenever the selector (13) is switched. In other words, it is a timing-free circuit. In addition, the duty ratio adjustment circuit of the present invention can function so that the duty ratio of another observation point is 50% instead of 50% at the output of the duty ratio variable circuit. It is possible to place observation points at arbitrary points in the clock tree and set the duty ratio at that point to 50%. Further, according to the present invention, the duty ratio of the target need not be 50%, and if the detection circuit is devised, the duty ratio can be adjusted to an arbitrary value assumed by the designer. Furthermore, since these can all be designed as digital circuits, complicated designs such as analog circuits are not required.
The variable range and pitch of the duty ratio variable circuit can be determined by the delay line 11 which is another mechanism. When the delay line is composed of a simple buffer circuit, the pitch is about 20 ps / 1 pitch in the 0.18 μm process. However, when the adjustment is made in finer units, the delay line 11 is improved without changing the duty ratio variable circuit of the present invention. do it.
[0023]
The preferred embodiments have been described above, but the present invention is not limited to these embodiments, and appropriate modifications can be made without departing from the scope of the present invention. For example, the inverter is not necessarily constituted by a CMOS, and a bipolar transistor can be adopted as a transistor.
[0024]
【The invention's effect】
As described above, according to the present invention, the rising edge or falling edge of the input clock can be delayed or advanced by an arbitrary width, so that the duty ratio of the clock can be accurately adjusted to, for example, 50%. Become. Further, according to the present invention, the duty ratio at the observation point of the duty ratio can be adjusted to 50%, for example, so that the duty ratio deviation due to manufacturing variations is absorbed and the duty ratio of the entire LSI surface is set to 50%. It is possible to move closer, and it is possible to stably operate a high-speed LSI.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an embodiment of the present invention.
FIG. 2 is a circuit diagram of a duty ratio variable circuit according to the first embodiment of the present invention.
FIG. 3 is a block diagram of a duty ratio adjustment circuit according to the first embodiment of the present invention.
FIG. 4 is an operation explanatory diagram of the duty ratio variable circuit according to the first embodiment of the present invention.
FIG. 5 is a timing chart for explaining the operation of the duty ratio variable circuit according to the first embodiment of the present invention;
FIG. 6 is a circuit diagram of a duty ratio variable circuit according to a second embodiment of the present invention.
FIG. 7 is a timing chart for explaining the operation of the duty ratio variable circuit according to the second embodiment of the present invention.
FIG. 8 is a block diagram of a duty ratio adjustment circuit according to a third embodiment of the present invention.
FIG. 9 is a circuit diagram of a duty ratio variable circuit according to a fourth embodiment of the present invention.
FIG. 10 is a block diagram of a duty ratio adjustment circuit according to a fourth embodiment of the present invention.
FIG. 11 is a circuit diagram of a duty ratio variable circuit according to a fifth embodiment of the present invention.
FIG. 12 is a block diagram of a duty ratio adjustment circuit according to a fifth embodiment of the present invention.
FIG. 13 is a block diagram showing a conventional H clock tree type clock distribution network.
FIG. 14 is a clock waveform diagram for explaining problems of the conventional example.
[Explanation of symbols]
1, INV1, INV2 inverter
2 Voltage modulation circuit
3 Voltage discrimination circuit
11 Delay line
12, 12a, 12b Delay circuit
13 Selector
131, 133, 135 First selector
132, 134, 136 Second selector
14 Duty ratio variable circuit
141 First duty ratio variable circuit
142 Second Duty Ratio Variable Circuit
15 Clock distribution network
16 Duty ratio detection circuit
17, 17a, 17b Counter
51 Input terminal
52 PLL circuit
53 Clock driver
100, 200, 300, 400 Duty ratio adjustment circuit
CLK input clock
S0 Controlled clock
S0 ₁ 1st controlled clock
S0 ₂ Second controlled clock
S1 Control clock
S1 ₁ , S1 ₃ First control clock
S1 ₂ , S1 ₄ Second control clock
S2 Adjusted clock
S2 ₁ First adjusted clock
S2 ₂ Second adjusted clock
S3 Distribution end clock
S4 Duty ratio signal
S5 Select signal
S6 to Sn delay clock
SS0 Voltage modulation clock
U1 switching signal

Claims (14)

A distribution end clock signal obtained from a circuit end of a circuit to which a clock is distributed is input, and a clock signal delayed in phase based on a duty ratio of the distribution end clock signal is output as a first type control clock signal. A kind of phase lag circuit,
An inverter to which a clock signal is input, a first type switching element connected between an output line of the inverter and a power source, controlled by the first type control clock signal, and the output line A duty ratio variable circuit having a voltage discrimination circuit for identifying a voltage and outputting a high / low signal;
And a duty ratio adjustment circuit for adjusting a duty ratio of the clock signal. A distribution end clock signal obtained from a circuit end of a circuit to which a clock is distributed is input, and a clock signal delayed in phase based on the duty ratio of the distribution end clock signal is output as a second type control clock signal. A kind of phase lag circuit,
An inverter to which a clock signal is input, a second type switching element connected between an output line of the inverter and a ground potential, controlled by the second type control clock signal, and a voltage of the output line A duty ratio variable circuit having a voltage discriminating circuit that discriminates and outputs a high / low signal;
And a duty ratio adjustment circuit for adjusting a duty ratio of the clock signal. A distribution end clock signal obtained from a circuit end of a circuit to which a clock is distributed is input, and two types of clock signals whose phases are delayed based on the duty ratio of the distribution end clock signal are classified into a first type and a second type, respectively. A first type and a second type of phase lag circuit that are output as control clock signals;
An inverter to which a clock signal is input, a first type switching element connected between an output line of the inverter and a power source, controlled by the first type control clock signal, and an output of the inverter A second type switching element connected between a line and a ground potential and controlled by the second type control clock signal, and a voltage for identifying a voltage of the output line and outputting a high / low signal A duty ratio variable circuit having a discrimination circuit;
And a duty ratio adjustment circuit for adjusting a duty ratio of the clock signal.   4. The duty ratio adjustment circuit according to claim 3, wherein the first type switching element and the second type switching element are complementarily controlled to be disconnected from the output line of the inverter. 5. . A distribution end clock signal obtained from a circuit end of a circuit to which a clock is distributed is input, and two types of clock signals whose phases are delayed based on the duty ratio of the distribution end clock signal are classified into a first type and a second type, respectively. A first type and a second type of phase delay circuit for outputting a control clock signal of
A first type inverter to which a clock signal is input, and a first type switching controlled by the first type control clock signal connected between an output line of the first type inverter and a power source. A duty ratio variable circuit of the first type having an element and a voltage discriminating circuit for identifying a voltage of the output line and outputting a high / low signal;
The second type inverter to which the output signal of the first type duty ratio variable circuit is input, and the second type control clock signal connected between the output line of the second type inverter and the ground potential. A second type duty ratio variable circuit comprising: a second type switching element controlled by: a voltage discriminating circuit for identifying a voltage of the output line and outputting a high / low signal;
And a duty ratio adjustment circuit for adjusting a duty ratio of the clock signal.   The first type or second type phase delay circuit receives the clock signal and outputs a delay line that outputs a plurality of delayed clocks to a selector circuit; and a duty ratio detection circuit that detects a duty ratio of the distribution end clock signal And a selector control circuit that controls the selector circuit based on the duty ratio detected by the duty ratio detection circuit and outputs a delay clock having a desired delay amount. 6. The duty ratio adjustment circuit according to any one of 1 to 5.   The duty ratio adjustment circuit according to claim 6, wherein the variable duty ratio circuit aligns a rise edge or a fall edge with that of the input delay clock. A distribution end clock signal obtained from a circuit end of a circuit to which a clock is distributed is input, and two types of clock signals whose phases are delayed based on the duty ratio of the distribution end clock signal are classified into a first type and a second type, respectively. A first type and a second type of phase lag circuit that are output as control clock signals;
An inverter to which a clock signal is input, a first type switching element connected between an output line of the inverter and a power source, controlled by the first type control clock signal, and an output of the inverter A second type switching element connected between a line and a ground potential and controlled by the second type control clock signal, and a voltage for identifying a voltage of the output line and outputting a high / low signal A duty ratio variable circuit having a discrimination circuit;
The first or second phase delay circuit includes a delay line that receives the clock signal and outputs a plurality of delay clocks to a selector circuit, and the distribution end clock. A duty ratio detection circuit for detecting a duty ratio of the signal, and a selector control circuit for controlling the selector circuit based on the duty ratio detected by the duty ratio detection circuit and outputting a delay clock having a desired delay amount. The first type switching element and the second type switching element are selectively controlled to be connected / disconnected to the output line by a switching signal output from the selector control circuit. Duty ratio adjustment circuit. The distribution end clock signal obtained from the circuit end of the circuit to which the clock is distributed, the power supply potential and the ground potential are input, and the clock signal or the power supply potential whose phase is delayed based on the duty ratio of the distribution end clock signal Are output as first and second type control clock signals, respectively, and first and second type phase delay circuits,
An inverter to which a clock signal is input, a first type switching element connected between an output line of the inverter and a power source, controlled by the first type control clock signal, and an output of the inverter A second type switching element connected between a line and a ground potential and controlled by the second type control clock signal, and a voltage for identifying a voltage of the output line and outputting a high / low signal A duty ratio variable circuit having a discrimination circuit;
The first or second phase delay circuit includes a delay line that receives the clock signal and outputs a plurality of delay clocks to a selector circuit, and the distribution end clock. A duty ratio detection circuit for detecting a duty ratio of the signal, and a selector control circuit for controlling the selector circuit based on the duty ratio detected by the duty ratio detection circuit and outputting a delay clock having a desired delay amount. And whether the first type phase lag circuit outputs a power supply potential or the second type phase lag circuit outputs a ground potential is selected based on an output signal of the selector control circuit. One of the one type of switching elements and the second type of switching elements is controlled to be disconnected from the output line. Ti ratio adjustment circuit.   10. The first type switching element is configured by a p-channel MOS transistor having a gate to which the control clock signal or the first control clock signal is input. The duty ratio adjustment circuit according to any one of the above.   10. The second type switching element is configured by an n-channel MOS transistor in which the control clock signal or the second control clock signal is input to a gate. The duty ratio adjustment circuit described in 1.   12. The duty ratio adjusting circuit according to claim 10, wherein the inverter is an inverter having a CMOS configuration.   13. The duty according to claim 12, wherein an on-resistance of an n-channel MOS transistor constituting the inverter or a plurality of n-channel MOS transistors connected in series is higher than an on-resistance of the first switching element. Ratio adjustment circuit.   14. The on-resistance of a p-channel MOS transistor constituting the inverter or a plurality of p-channel MOS transistors connected in series is higher than the on-resistance of the second switching element. A duty ratio adjusting circuit according to claim 1.

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