CN105244331A - Chip package structure - Google Patents

Chip package structure Download PDF

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Publication number
CN105244331A
CN105244331A CN201510651331.6A CN201510651331A CN105244331A CN 105244331 A CN105244331 A CN 105244331A CN 201510651331 A CN201510651331 A CN 201510651331A CN 105244331 A CN105244331 A CN 105244331A
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CN
China
Prior art keywords
chip
structure according
bridge
encapsulating structure
metal wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510651331.6A
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Chinese (zh)
Inventor
曹周
黄源炜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Great Team Backend Foundry Dongguan Co Ltd
Original Assignee
Great Team Backend Foundry Dongguan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Great Team Backend Foundry Dongguan Co Ltd filed Critical Great Team Backend Foundry Dongguan Co Ltd
Priority to CN201510651331.6A priority Critical patent/CN105244331A/en
Publication of CN105244331A publication Critical patent/CN105244331A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8412—Aligning
    • H01L2224/84136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/84138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8434—Bonding interfaces of the connector
    • H01L2224/84345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Wire Bonding (AREA)

Abstract

The embodiment of the invention discloses a chip package structure, which comprises a lead frame, a chip and a universal bridge, wherein the chip is located on lead frame; the universal bridge is electrically connected with the chip through a conductive combination material; and a support is arranged in the conductive combination material, and respectively contacts the chip and the universal bridge. Through the chip package structure disclosed by the embodiment of the invention, unified production of the bridge structure is achieved, so that management is facilitated; the product cost is relatively low; and the development period is shortened.

Description

A kind of chip-packaging structure
Technical field
The embodiment of the present invention relates to application semiconductor packaging structure, particularly relates to a kind of chip-packaging structure.
Background technology
Semiconductor packaging industry develops various multi-form packaging structure, such as, be integrated in single encapsulation module by multiple chip.When for multiple chip (such as logic chip and storage chip) integration is arranged on a base plate for packaging, one intermediary layer must be first set usually on described substrate, then more described chip is arranged on described intermediary layer, carry out circuit layout again by intermediary layer upper and lower surface, complete the electric connection between chip and substrate.
Utilize bridge construction as intermediary layer in prior art, for connecting chip and substrate circuit.If Fig. 1 is that shown in a kind of bridge construction planing surface figure of the prior art, bridge of the prior art generally comprises: circuit connecting section divides 01, chip connect portions 02 and supporting construction part 03.Wherein, supporting construction part 03 cause described bridge to cave in for preventing because scolding tin or conducting resinl do not have solid shape or connection area excessive.Because in prior art, this supporting construction part 03 and bridge are one, inseparable.Therefore, a kind of bridge construction with immovable supporting construction part is only suitable for the connection of a kind of chip and circuit, thus causes bridge construction not unify production management, and the raising of production cost.
Summary of the invention
The embodiment of the present invention provides a kind of chip-packaging structure, produces to realize the unified of bridge construction, thus convenient management, and comparatively low production cost, shorten the construction cycle.
Embodiments provide a kind of chip-packaging structure, this structure comprises:
Lead frame;
Be positioned at the chip on described lead frame;
Universal bridge, connect in conjunction with material and chip electrical by conduction, described conduction is provided with supporter in conjunction with in material, and above support contacts with described universal bridge with described chip respectively.
Further, above support is Metal Ball, and the fusing point of Metal Ball is higher than scolding tin.
Further, described Metal Ball is ping-pong ball or copper ball.
Further, described Metal Ball adopts thermosonic bonding processes to contact with described universal bridge with described chip.
Further, above support is the metal wire with certain flexibility, and described metal wire is with its mid point for summit, and bending two ends becomes necessarily to spend angle, and described summit is connect in conjunction with material and chip electrical by conduction, and described metal wire two ends prop up the lower surface of universal bridge.
Further, described metal wire is aluminium core, and its skin is silver layer.
Further, described bond material is tin material.
Further, described bond material is silver-colored material or conducting resinl.
The present invention arranges supporter by conduction in conjunction with in material, this supporter can according to the different size of chip and the chip different connected modes from circuit, be arranged on diverse location, realize the support of universal bridge and chip, make same bridge construction go for the connection of the chip of different size, thus realize the unified production of bridge construction, convenient management, simultaneously comparatively low production cost, shortens the construction cycle.
Accompanying drawing explanation
Fig. 1 is a kind of bridge construction planing surface figure of the prior art;
Fig. 2 A is the vertical view of a kind of chip-packaging structure in the embodiment of the present invention one;
Fig. 2 B is the Welding Structure planing surface figure along the A-A direction in Fig. 2 A;
Fig. 3 A is the vertical view of a kind of chip-packaging structure in the embodiment of the present invention two;
Fig. 3 B is the Welding Structure planing surface figure along the A-A direction in Fig. 3 A.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not entire infrastructure.
Embodiment one
Fig. 2 A is the vertical view of a kind of chip-packaging structure in the embodiment of the present invention one, and the present embodiment is applicable to the connection of bridge and chip, and this Welding Structure comprises: lead frame 1, chip 2 and universal bridge 3.
Wherein, chip 2 is positioned on lead frame 1, and the size of this chip 2 can have multiple.
For adapting to the connection of different size chip 2, universal bridge 3 and chip 2 connect conduction used in conjunction with material 5 in be provided with supporter, above support contacts with universal bridge 3 with chip 2 respectively.This supporter can be arbitrary shape, such as, can be square, and the present embodiment is preferably the Metal Ball 4 of fusing point higher than tin material, for supporting universal bridge 3.This Metal Ball 4 can be connected any one or both ends by ultrasonic wave cold welding technology with chip 2 and universal bridge 3, is ping-pong ball for convenience of connecting the present embodiment preferable alloy ball 4.For reducing costs, this ping-pong ball also can be the Metal Ball of electroplate, or is covered with the copper ball of tin material solder joint up and down.
Wherein, what realize the electric connection of chip 2 and universal bridge 3 can be conductive bonding material also can be conductive metal balls, and this conduction can be silver-colored material, tin material or conducting resinl etc. in conjunction with material.
The welded operation principle of this universal bridge framework is: universal bridge 3 is supported on chip 2 by Metal Ball 4, then utilizes conduction to realize the electric connection of universal bridge 3 and chip 2 in conjunction with material 5 or conductive metal balls.
In the technical scheme of the present embodiment, universal bridge is by according to the different size of chip and the chip different connected modes from circuit, arranging Metal Ball is supported on chip at diverse location, realize the connection that same bridge construction goes for the chip of different size, thus realize the unified production of bridge construction, convenient management, simultaneously comparatively low production cost, shorten the construction cycle.
Embodiment two
Fig. 3 A is the vertical view of a kind of chip-packaging structure in the embodiment of the present invention two, the present embodiment is a kind of chip-packaging structure proposed on the basis of embodiment one, and this structure is applicable to the connection of bridge and chip, and this Welding Structure comprises: lead frame 1, chip 2, and universal bridge 3.
When universal bridge 3 places weight, for preventing the chip 2 from crushing, the conduction that universal bridge 3 is connected with chip 2 is the metal wire 6 with certain flexibility in conjunction with the supporter arranged in material 5.This metal wire is with its mid point for summit, and bending two ends becomes necessarily to spend angle, and described summit is connected with chip 2 in conjunction with material 5 by conduction, and described metal wire 6 two ends prop up the lower surface of universal bridge 3.Therefore, when universal bridge 3 places weight, because bending metal wire 6 has certain elasticity, thus there is certain buffering to the gravity that weight on universal bridge 3 produces.
Wherein, metal wire 6 can be the metal wire arbitrarily with certain flexibility, such as, can be copper cash or aluminum steel, for convenience of this metal wire 6 and chip connection and reduce costs, the present embodiment preferably this metal wire is aluminium core, and silver is outer.
Wherein, what realize the electric connection of chip 2 and universal bridge 3 can be conductive bonding material also can be conductive metal wire.
In the technical scheme of the present embodiment, universal bridge 3 is according to the different size of chip and the chip different connected modes from circuit, be supported on chip 2 by the outer field metal wire 6 of bending aluminium core silver, realize the connection that same bridge construction goes for the chip 2 of different size.Because bending metal wire 6 has certain elasticity, thus has certain buffering to the gravity that weight on universal bridge 3 produces, and prevents chip 2 crushed.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.

Claims (8)

1. a chip-packaging structure, is characterized in that, comprising:
Lead frame;
Be positioned at the chip on described lead frame;
Universal bridge, connect in conjunction with material and chip electrical by conduction, described conduction is provided with supporter in conjunction with in material, and above support contacts with described universal bridge with described chip respectively.
2. encapsulating structure according to claim 1, is characterized in that,
Above support is Metal Ball, and the fusing point of Metal Ball is higher than scolding tin.
3. encapsulating structure according to claim 2, is characterized in that,
Described Metal Ball is ping-pong ball or copper ball.
4. encapsulating structure according to claim 2, is characterized in that,
Described Metal Ball adopts thermosonic bonding processes to contact with described chip or described universal bridge.
5. encapsulating structure according to claim 1, is characterized in that,
Above support is the metal wire with certain flexibility, and described metal wire is with its mid point for summit, and bending two ends becomes necessarily to spend angle, and described summit is connected with chip in conjunction with material by conduction, and described metal wire two ends prop up the lower surface of universal bridge.
6. encapsulating structure according to claim 5, is characterized in that,
Described metal wire internal layer is aluminium core, and its skin is silver layer.
7. encapsulating structure according to claim 1, is characterized in that,
Described conductive bonding material is tin material.
8. encapsulating structure according to claim 1, is characterized in that,
Described conductive bonding material is silver-colored material or conducting resinl.
CN201510651331.6A 2015-10-10 2015-10-10 Chip package structure Pending CN105244331A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112509998A (en) * 2020-11-18 2021-03-16 杰群电子科技（东莞）有限公司 Wafer-level packaging process for high-power semiconductor product and semiconductor product

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110241198A1 (en) * 2010-04-02 2011-10-06 Hitachi, Ltd. Power Semiconductor Module
CN103503132A (en) * 2011-06-09 2014-01-08 三菱电机株式会社 Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110241198A1 (en) * 2010-04-02 2011-10-06 Hitachi, Ltd. Power Semiconductor Module
CN103503132A (en) * 2011-06-09 2014-01-08 三菱电机株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112509998A (en) * 2020-11-18 2021-03-16 杰群电子科技（东莞）有限公司 Wafer-level packaging process for high-power semiconductor product and semiconductor product

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