CN102157485B - Semiconductor packaging frame - Google Patents
Semiconductor packaging frame Download PDFInfo
- Publication number
- CN102157485B CN102157485B CN201110071199A CN201110071199A CN102157485B CN 102157485 B CN102157485 B CN 102157485B CN 201110071199 A CN201110071199 A CN 201110071199A CN 201110071199 A CN201110071199 A CN 201110071199A CN 102157485 B CN102157485 B CN 102157485B
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- CN
- China
- Prior art keywords
- pin
- regular
- chip bearing
- semiconductor packages
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
The invention relates to a semiconductor packaging frame. The semiconductor packaging frame comprises a chip bearing base, base connecting ribs and regular pins, wherein the regular pins are distributed around the chip bearing base. The semiconductor packaging frame is characterized in that the frame also comprises a bridging pin; the bridging pin is of flexed door frame structure; the lateral frame part of the door frame structure protrudes out of the tips of the regular pins along the direction of the chip bearing base; and the two vertical frames of the door frame structure serve as the output ends and are embedded among the regular pins. Compared with the prior art, the semiconductor packaging frame which the invention requests to protect has the following advantages: various weld line requirements can be met; the packaging density is optimized; the electrical and thermal properties and reliability of the product are improved; and the developing and manufacturing costs of the frame are lowered.
Description
Technical field
The present invention relates to semiconductor technology, relate in particular to a kind of semiconductor packages framework.
Background technology
In conventional semiconductor packages; Particularly highdensity pin is evenly distributed on the framework around the chip bearing pedestal; Chip carries out in the interconnected process of bonding through metal lead wire and pin, the far away or corresponding demand in pin position etc. during because of chip design demand, mother matrix surface mount because of pin distance, regular meeting occur metal lead wire intersect, long, silk even dash curved problem collapses; And then it is stable to have influence on performance of products, brings reliability hidden danger.
Summary of the invention
The technical problem that the present invention solves is: how having now under the constant prerequisite of package dimension, the semiconductor packages framework that a kind of flexibility is high, bonding effect is stable, reliability is high is provided.
For solving the problems of the technologies described above; The present invention provides a kind of semiconductor packages framework, comprises that chip bearing pedestal, pedestal connect muscle, regular pin, said regular pin be distributed in said chip bearing pedestal around; It is characterized in that: also comprise the bridge joint pin; Said bridge joint pin is the doorframe structure of warpage, and the horizontal frame of said doorframe structure partly protrudes in the tiptoe of regular pin along chip bearing pedestal direction, and two munnions of doorframe structure are output and are embedded between a plurality of regular pins.
Alternatively; Also comprise the riveted pin; Said riveted pin is two doorframe structures that L shaped parts axial symmetry is formed, and the horizontal frame of said doorframe structure is provided with opening, is provided with insulated connecting piece between said opening the two ends riveted of opening is fixed; The horizontal frame of said doorframe structure partly protrudes in the tiptoe of regular pin along chip bearing pedestal direction, two munnions of doorframe structure are output and are embedded between a plurality of regular pins.
Alternatively, comprise also leaning out pin that the said tiptoe that leans out pin is longer than regular pin and is extended to chip bearing pedestal direction.
Alternatively, also comprise wide pin, the contact area of said wide pin is greater than the contact area of regular pin.
Compared with prior art, a kind of semiconductor packages framework that the present invention asks for protection has following advantage:
When the chip bonding pad position distribution of a plurality of identical functions far away when again can't be interconnected with pin nearby; This frame structure can provide good bridge to accept transitional function through the bridge joint pin, and then produces integrity problems such as metal lead wire intersection, short circuit when avoiding bonding technology;
2. when the chip bonding pad of many difference in functionalitys pin difficult and nearby is interconnected; This frame structure can provide good bridge to accept through the riveted pin to be used for supplying chip interconnected nearby, and the insulated connecting piece of riveted pin can make the riveted pin have two sections output functions that insulate independently to satisfy the electrical functionality demand;
3. in the bonding technology process; Consideration from metal lead wire integrated planning layout; Chip bonding pad need with all around the distance far pin carry out interconnected; This frame structure is through leaning out pin design with local pin lengthening, and then the bonding distance between shortening and chip bonding pad, avoids metal lead wire long and produce the silk that collapses, dash curved problem;
4. in bonding technology, because the needs of chip design, when a plurality of chip bonding pads needed to carry out function output through a pin, this frame structure can make metal lead wire that pin carries greater number to satisfy design requirement through being provided with of wide the pin in part.
Description of drawings
Fig. 1 is the sketch map of a kind of semiconductor packages framework one embodiment of the present invention;
Fig. 2 is the foregoing description chips and the interconnected sketch map of bridge joint pin;
Fig. 3 is the foregoing description chips and the interconnected sketch map of riveted pin;
Fig. 4 is for the foregoing description chips and lean out the interconnected sketch map of pin;
Fig. 5 is the foregoing description chips and wide the sketch map that pin is interconnected.
Embodiment
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, and when the embodiment of the invention was detailed, for ease of explanation, said sketch map was an instance, and it should not limit the scope of the present invention's protection at this.
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
With reference to figure 1; Show the sketch map of a kind of semiconductor packages framework one embodiment of the present invention; Comprise that chip bearing pedestal 201, pedestal connect muscle 202, regular pin 203; Said pedestal connects muscle 202 and is used for fixing chip bearing pedestal 201, said regular pin 203 be distributed in said chip bearing pedestal 201 around, it is characterized in that: also comprise bridge joint pin 101, riveted pin 102, lean out pin 103, wide pin 104.Particularly:
With reference to figure 2, said bridge joint pin 101 is the doorframe structure of warpage, and the horizontal frame of doorframe structure partly protrudes in the tiptoe of regular pin along chip bearing pedestal direction, and two munnions of doorframe structure are output and are embedded in 203 of a plurality of regular pins.Chip 301 is arranged on the chip bearing base 201, and metal lead wire 303 is interconnected with chip bonding pad 302 and bridge joint pin 101 bondings.When identical chip bonding pad 302 position distribution of a plurality of functions far away when again can't be interconnected with nearby regular pin 203; Bridge joint pin 101 can provide good bridge to accept effect, and then avoids when the semiconductor packages bonding technology, producing integrity problems such as metal lead wire 303 banks intersection, short circuit.
With reference to figure 3; Said riveted pin 102 is two doorframe structures that L shaped parts 102a axial symmetry is formed; The horizontal frame of said doorframe structure is provided with opening; Be provided with insulated connecting piece 102b between opening the two ends riveted of opening is fixed, the horizontal frame of said doorframe structure partly protrudes in the tiptoe of regular pin 203 along chip bearing pedestal 201 directions, and two munnions of doorframe structure are output and are embedded in 203 of a plurality of regular pins.Chip 301 is arranged on the chip bearing base 201, and metal lead wire 303 is interconnected with chip bonding pad 302 and riveted pin 102 bondings.Because the qualification of chip circuit design and final products pin position when mother matrix welds; And consider when bonding technology integrity problems such as being prone to produce metal lead wire 303 banks intersection, short circuit; The chip bonding pad 302 of a plurality of difference in functionalitys is difficult interconnected with regular pin 203 nearby; This moment, riveted pin 102 can provide good bridge to accept to be used for supplying between chip 301 and pin interconnected nearby; And the insulated connecting piece 102b of riveted pin 102 makes riveted pin 102 have two sections output functions that insulate independently to satisfy the electrical functionality demand; Simultaneously, insulated connecting piece 102b rivets together two L shaped parts 102a parts can also improve the mechanical strength of riveted pin 102, improves bonding effect.
With reference to figure 4, the said tiptoe that leans out pin 103 is longer than regular pin 203 and is extended to chip bearing pedestal 201 directions.Chip 301 is arranged on the chip bearing base 201, metal lead wire 303 with chip bonding pad 302 with to lean out pin 103 bondings interconnected.In semiconductor packages bonding technology process; Consideration from metal lead wire 303 integrated plannings layout; Chip bonding pad 302 need carry out interconnected, traditional rule 203 modes that go between with the far pin of distance all around and cause metal lead wire 303 long and produce the integrity problem such as silk grade that collapses easily; At this moment, local lean out pin 103 designs and can shorten the bonding distance, metal lead wire 303 is dashed curved risk when avoiding metal lead wire 303 to occur collapsing silk and follow-up plastic package process.
With reference to figure 5, said semiconductor packages framework also comprises wide pin 104, and the contact area of said wide pin 104 is greater than the contact area of regular pin 203.Chip 301 is arranged on the chip bearing base 201, and metal lead wire 303 is interconnected with chip bonding pad 302 and wide pin 104 bondings.In the semiconductor packages bonding technology; Because the needs of chip 301 designs; A plurality of chip bonding pads 302 need carry out function output through a pin, correspondingly, can make metal lead wire 303 that pin carries greater number to satisfy design requirement through being provided with of wide the pin 104 in part.
Comprise bridge joint pin 101, riveted pin 102 in the foregoing description, leant out pin 103 and wide pin 104; But the present invention is not restricted to this, and those skilled in the art can correspondingly make up, be out of shape and replace above-mentioned several kinds of special pin designs on the basis of existing regular pin 203 according to design requirement.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (4)
1. a semiconductor packages framework comprises that chip bearing pedestal, pedestal connect muscle, regular pin, said regular pin be distributed in said chip bearing pedestal around, it is characterized in that:
Also comprise the bridge joint pin, said bridge joint pin is the doorframe structure of warpage, and the horizontal frame of said doorframe structure partly protrudes in the tiptoe of regular pin along chip bearing pedestal direction, and two munnions of doorframe structure are output and are embedded between a plurality of regular pins;
Said semiconductor packages framework also comprises the riveted pin; Said riveted pin is two doorframe structures that L shaped parts axial symmetry is formed; The horizontal frame of said doorframe structure is provided with opening; Be provided with insulated connecting piece between said opening the two ends riveted of opening is fixed, the horizontal frame of said doorframe structure partly protrudes in the tiptoe of regular pin along chip bearing pedestal direction, and two munnions of doorframe structure are output and are embedded between a plurality of regular pins.
2. a kind of semiconductor packages framework as claimed in claim 1 is characterized in that: comprise also leaning out pin that the said tiptoe that leans out pin is longer than regular pin and is extended to chip bearing pedestal direction.
3. according to claim 1 or claim 2 a kind of semiconductor packages framework, it is characterized in that: also comprise wide pin, the contact area of said wide pin is greater than the contact area of regular pin.
4. a kind of semiconductor packages framework as claimed in claim 3 is characterized in that: also comprise wide pin, the contact area of said wide pin is greater than the contact area of regular pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110071199A CN102157485B (en) | 2011-03-23 | 2011-03-23 | Semiconductor packaging frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110071199A CN102157485B (en) | 2011-03-23 | 2011-03-23 | Semiconductor packaging frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102157485A CN102157485A (en) | 2011-08-17 |
| CN102157485B true CN102157485B (en) | 2012-10-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110071199A Active CN102157485B (en) | 2011-03-23 | 2011-03-23 | Semiconductor packaging frame |
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| Country | Link |
|---|---|
| CN (1) | CN102157485B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103534A (en) * | 2013-04-02 | 2014-10-15 | 瑞萨电子株式会社 | Semiconductor device manufacturing method and semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449587A (en) * | 2016-08-30 | 2017-02-22 | 北京握奇数据系统有限公司 | Lead frame structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2763978Y (en) * | 2004-12-16 | 2006-03-08 | 南通富士通微电子股份有限公司 | Welding wire-leading frame for IC |
| CN101800211A (en) * | 2009-02-10 | 2010-08-11 | 株式会社东芝 | Semiconductor device |
| CN202003989U (en) * | 2011-03-23 | 2011-10-05 | 南通富士通微电子股份有限公司 | Semiconductor packaging framework |
-
2011
- 2011-03-23 CN CN201110071199A patent/CN102157485B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2763978Y (en) * | 2004-12-16 | 2006-03-08 | 南通富士通微电子股份有限公司 | Welding wire-leading frame for IC |
| CN101800211A (en) * | 2009-02-10 | 2010-08-11 | 株式会社东芝 | Semiconductor device |
| CN202003989U (en) * | 2011-03-23 | 2011-10-05 | 南通富士通微电子股份有限公司 | Semiconductor packaging framework |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103534A (en) * | 2013-04-02 | 2014-10-15 | 瑞萨电子株式会社 | Semiconductor device manufacturing method and semiconductor device |
| CN104103534B (en) * | 2013-04-02 | 2018-06-22 | 瑞萨电子株式会社 | Method, semi-conductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102157485A (en) | 2011-08-17 |
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| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
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| CP01 | Change in the name or title of a patent holder |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |