CN105227162A - A kind of signal burr eliminates circuit - Google Patents
A kind of signal burr eliminates circuit Download PDFInfo
- Publication number
- CN105227162A CN105227162A CN201510580200.3A CN201510580200A CN105227162A CN 105227162 A CN105227162 A CN 105227162A CN 201510580200 A CN201510580200 A CN 201510580200A CN 105227162 A CN105227162 A CN 105227162A
- Authority
- CN
- China
- Prior art keywords
- reference voltage
- unit
- output signal
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 35
- 230000008030 elimination Effects 0.000 claims description 23
- 238000003379 elimination reaction Methods 0.000 claims description 23
- 230000000630 rising effect Effects 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000007812 deficiency Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 18
- 238000001914 filtration Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
The present invention relates to a kind of signal burr and eliminate circuit, this circuit comprises: comparator unit, reference voltage selected cell and burr eliminate unit; Wherein, comparator unit is used for the input signal of reception and reference voltage to compare, and generation first is outputed signal output; Reference voltage selected cell, for receiving the first reference voltage and second reference voltage of input, receives the second output signal that burr eliminates unit simultaneously, and is exported by the reference voltage produced; Burr eliminates unit for receiving the first output signal, and the produce second output signal is externally exported, and outputs to reference voltage selected cell.Signal burr provided by the invention eliminates circuit, can overcome the deficiencies in the prior art, improves signal burr and eliminate precision while reduction area.
Description
Technical Field
The present invention relates to a signal glitch processing technique, and more particularly, to a signal glitch removal circuit.
Background
In a general signal glitch removing circuit, an area needs to be increased to remove a wide glitch, and its removing effect depends heavily on the amplitude of an input signal and the power supply voltage of a receiving circuit. As a commonly used RC low pass filter plus schmitt trigger, the width of glitch removal can be increased only by increasing the value of RC, but increasing the value of RC increases the area. In addition, due to the voltage reversal characteristic of the schmitt trigger, the amplitude of the input signal and the power supply voltage of the schmitt trigger can both seriously affect the glitch elimination precision of the circuit.
Disclosure of Invention
The invention aims to provide a circuit for eliminating signal burrs, which can overcome the defects of the prior art, reduce the area and improve the accuracy of eliminating the signal burrs.
In order to achieve the above object, the present invention provides a signal glitch removal circuit, which includes a reference voltage selection unit, a comparator unit, and a glitch removal unit; wherein,
the reference voltage selection unit is used for receiving a first reference voltage and a second reference voltage and receiving a second output signal of the burr elimination unit; the reference voltage selection unit determines the first reference voltage or the second reference voltage as the reference voltage according to the second output signal of the glitch elimination unit and outputs the reference voltage; the comparator unit is used for receiving an input signal and the reference voltage, generating a first output signal according to the input signal and the reference voltage and outputting the first output signal; the burr eliminating unit is used for receiving the first output signal, eliminating burrs of the first output signal and generating a second output signal, and outputting the generated second output signal to the outside and outputting the second output signal to the reference voltage selecting unit.
Preferably, the comparator unit includes a comparator and a current driver; wherein,
the positive input end of the comparator receives an input signal, the negative input end of the comparator receives a reference voltage, and the comparator compares the rising edge or the falling edge of the input signal with the reference voltage and outputs a comparison result; the current driver outputs a first output signal according to the comparison result.
Preferably, the comparator unit comprises a load, which is a resistive load and/or a diode load and/or a current mirror load.
Preferably, the current driver in the comparator unit outputs the current in a manner of one or more of directly mirroring the load current output, switching control current source output and switching control current sink output.
Preferably, the reference voltage selection unit comprises a first MOS transistor, a second MOS transistor and an inverter; wherein,
the negative output end of the phase inverter is connected with the grid electrode of the first MOS tube, and the positive input end of the phase inverter is connected with the grid electrode of the second MOS tube and receives a second output signal; and the source electrode of the first MOS tube receives a first reference voltage, the source electrode of the second MOS tube receives a second reference voltage, the first MOS tube is connected with the drain electrode of the second MOS tube, and the first reference voltage or the second reference voltage is determined as the reference voltage according to the level of the second output signal and is output.
Preferably, the first MOS transistor in the reference voltage selection unit is an NMOS transistor, a PMOS transistor or a complementary switch transistor, and the second MOS transistor is an NMOS transistor, a PMOS transistor or a complementary switch transistor
Preferably, the glitch elimination unit includes a capacitor, a schmitt trigger, and an inverter; wherein,
the positive pole of the capacitor is connected with the input end of the Schmitt trigger and receives the first output signal, the negative plate of the capacitor is grounded, the output end of the Schmitt trigger is connected with the input end of the phase inverter, and the phase inverter outputs the second output signal.
Preferably, the spur elimination unit is capable of filtering spur noise mixed in the first output signal of the comparator unit and generating a second output signal without spur, and the eliminated signal spur width formula is: VTH C1/IREF and (VDD-VTL) C1/IREF; where VTH is a rising edge threshold voltage of the schmitt trigger, VDD is a power supply voltage of the schmitt trigger, VTL is a falling edge threshold voltage of the schmitt trigger, C1 is a capacitance of the capacitor, and IREF is a current value of the first output signal (COUT).
Preferably, the capacitor in the glitch elimination unit is a MOS capacitor, a metal-insulator-metal capacitor (MIM capacitor), or a polysilicon capacitor (POLY capacitor).
Preferably, the glitch removal unit includes a capacitor, and a schmitt trigger and/or an inverter.
Compared with the prior art, the invention has the following advantages:
according to the signal burr eliminating circuit provided by the invention, when the power supply of the input signal exceeds the reference voltage range determined by the first reference voltage and the second reference voltage, the normal receiving of the input signal can be ensured, the problem of signal receiving among different power supplies is solved, the application range of the receiving circuit is improved, and the influence of the type of the power supply is avoided; the normal work of the comparator unit is ensured, the burr of the input signal can be accurately filtered, the burr eliminating precision is improved, and the comparator unit is not influenced by the type of a power supply; the circuit of the invention adjusts the pulse width of the burr to be filtered by adjusting the current, thereby saving the area of a chip.
The circuit for eliminating the signal burr provided by the invention can overcome the defects of the prior art, and improve the precision of eliminating the signal burr while reducing the area.
Drawings
FIG. 1 is a schematic diagram of a conventional signal glitch removal circuit;
FIG. 2 is a timing diagram of a normal input signal of the conventional signal glitch removal circuit;
FIG. 3 is a timing diagram of a differential power input signal of the conventional signal glitch removal circuit;
FIG. 4 is a schematic circuit diagram of an embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of a comparator unit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a circuit structure of a reference voltage selection unit according to an embodiment of the present invention;
FIG. 7 is a schematic circuit diagram of a glitch removal unit according to an embodiment of the present invention;
FIG. 8 is a timing diagram of a normal input signal according to an embodiment of the present invention;
FIG. 9 is a timing diagram of different power input signals according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Fig. 1 is a schematic diagram of a conventional signal glitch removal circuit, which includes a resistive load, a capacitor, a schmitt trigger, and an inverter, as shown in fig. 1. The traditional signal burr elimination circuit realizes the filtration of burr noise lower than a certain pulse width by a mode of filtering and encrypting a Schmitt trigger by an RC low-pass filter.
Fig. 2 is a timing diagram of a normal input signal of a conventional signal glitch removal circuit, as shown in fig. 2, and the filter bandwidth is designed to be 250nS, and under a normal condition, the conventional circuit can filter glitch noise with a pulse width of 200nS and retain a signal with a pulse width of 300 nS.
Fig. 3 is a timing diagram of the conventional glitch removal circuit under the different power input signals, as shown in fig. 3, if the amplitude of the input signal VIN is changed, the conventional glitch removal circuit will also filter out the normal signals.
Fig. 4 is a schematic circuit structure diagram of an embodiment of the present invention, and as shown in fig. 4, the signal glitch elimination circuit of the present embodiment includes a comparator unit 01, a reference voltage selection unit 02, and a glitch elimination unit 03; wherein,
the comparator unit 01 is configured to receive the input signal VIN and the reference voltage VREF output by the reference voltage selection unit 02, and output the generated first output signal COUT to the spur cancellation unit 03; the reference voltage selection unit 02 is configured to receive the input first reference voltage VH and the second reference voltage VL, and also receive the second output signal VOUT of the glitch elimination unit 03, and output the generated reference voltage VREF to the comparator unit 01; the glitch removal unit 03 is configured to receive the first output signal COUT output by the comparator unit 01, output the generated second output signal VOUT with the glitch removed to the outside, and output the second output signal VOUT to the reference voltage selection unit.
Fig. 5 is a schematic circuit diagram of a comparator unit according to an embodiment of the present invention, and as shown in fig. 5, a comparator unit 01 in the signal glitch elimination circuit of the present embodiment includes a comparator 11 and a current driver 12; wherein,
a positive input end of the comparator 11 is configured to receive an input signal VIN, a negative input end of the comparator 11 is configured to receive a reference voltage VREF output by the reference voltage selection unit 02, and the comparator 11 compares a rising edge or a falling edge of the input signal VIN with the reference voltage VREF; the current driver 12 outputs the first output signal COUT to the glitch removal unit 03 according to the comparison result generated by the comparator 11.
In this embodiment, the comparator unit 01 includes a load, which is a resistive load and/or a diode load and/or a current mirror load.
In the present embodiment, one embodiment of the current drive output of the current driver 12 in the comparator unit 01 is a direct mirror load current output, another embodiment is a switch-controlled current source output, and yet another embodiment is a switch-controlled current sink output.
Fig. 6 is a schematic circuit structure diagram of a reference voltage selection unit according to an embodiment of the present invention, and as shown in fig. 6, the reference voltage selection unit 02 in the signal glitch elimination circuit of the present embodiment includes a first MOS transistor 22, a second MOS transistor 23, and an inverter 21; wherein,
a first reference voltage VH is input to the source of the first MOS tube 22, a second reference voltage VL is input to the source of the second MOS tube 23, the first open MOS tube 22 is connected with the drain of the second MOS tube 23, and a reference voltage VREF is output to the comparator unit 01; the input end of the inverter 21 is connected to the gate of the first MOS transistor 22 and receives the second output signal VOUT of the glitch elimination unit 03, and the output end of the inverter 21 is connected to the gate of the second MOS transistor 23.
In this embodiment, the first MOS transistor 22 is an NMOS transistor, a PMOS transistor, or a complementary switch transistor, and the second MOS transistor 23 is an NMOS transistor, a PMOS transistor, or a complementary switch transistor.
Fig. 7 is a schematic circuit diagram of a glitch removal unit according to an embodiment of the present invention, and as shown in fig. 7, a glitch removal unit 03 in the signal glitch removal circuit according to this embodiment includes a capacitor 31, a schmitt trigger 32, and an inverter 33; wherein,
a positive plate of the capacitor 31 is connected to an input terminal of the schmitt trigger 32 and receives the first output signal COUT of the comparator unit 01, and a negative plate of the capacitor 31 is grounded; the schmitt trigger 32 outputs the generated flip-flop to the inverter 33; the inverter 33 receives the flip-flop sent by the schmitt trigger 32; the generated second output signal VOUT is output to the outside, and the second output signal VOUT is output to the reference voltage selection unit 02.
In this embodiment, the glitch elimination unit 03 is capable of filtering the glitch noise included in the first output signal COUT of the comparator unit 01 to generate a second output signal VOUT without glitch, and the formula of the width of the signal glitch eliminated is: VTH C1/IREF and (VDD-VTL) C1/IREF; where VTH is a rising edge threshold voltage of the schmitt trigger 32, VDD is a power supply voltage of the schmitt trigger 32, VTL is a falling edge threshold voltage of the schmitt trigger 32, C1 is a capacitance of the capacitor 31, and IREF is a current value of the first output signal COUT.
In the present embodiment, the capacitor 31 in the glitch elimination unit 03 is a MOS capacitor, a metal-insulator-metal capacitor (MIM capacitor), or a polysilicon capacitor (POLY capacitor).
In the present embodiment, the glitch removal unit 03 includes a capacitor, and a schmitt trigger and/or an inverter.
As shown in fig. 4-7, the signal glitch elimination circuit provided in this embodiment can be specifically divided into two operation processes according to the level of the input signal:
the working process 1: input signal VIN is low
Since the input signal VIN is low, the first output signal COUT of the comparator unit 01 is low, which causes the second output signal VOUT of the glitch elimination unit 03 to be low; the voltage selection unit 02 selects the first reference voltage VH as the reference voltage VREF to output according to the level of the received second output signal VOUT, and the voltage selection unit 02 outputs the finally obtained reference voltage VREF to the comparator unit 01; the comparator unit 01 receives an input signal VIN and a reference voltage VREF output by the voltage selection unit 02, meanwhile, the comparator unit 01 detects a rising edge of the input signal VIN, and when the detected rising edge is higher than the reference voltage VREF, the output of the comparator 11 is turned to the current driver 12; the current driver 12 outputs a pull-up current source IREF according to the received signal, and outputs IREF to the spur cancellation unit 03 as a first output signal COUT; the voltage value at the input end of the schmitt trigger 32 is continuously increased at the speed of IREF/C1(IREF is the current value of the pull-up current source, and C1 is the capacitance of the capacitor 31), when the voltage value at the input end of the schmitt trigger 32 is increased to the rising edge threshold VTH of the schmitt trigger 32, the output of the schmitt trigger 32 is inverted, so that the second output signal VOUT is driven to be high; if the voltage at the input of the schmitt trigger 32 does not rise to VTH, the high level pulse carried by the input signal VIN at this time is filtered out as glitch noise. The filtered bandwidth formula is: VTH C1/IREF.
The working process is as follows: input signal VIN is high
Since the input signal VIN is high, the first output signal COUT of the comparator unit 01 is high, which causes the second output signal VOUT of the glitch elimination circuit 03 to be high; the voltage selection unit 02 selects the first reference voltage VL as the reference voltage VREF according to the level of the received second output signal VOUT, and the voltage selection unit 02 outputs the finally obtained reference voltage VREF to the comparator unit 01; the comparator unit 01 receives an input signal VIN and a reference voltage VREF output by the voltage selection unit 02, meanwhile, the comparator unit 01 detects a falling edge of the input signal VIN, and when the detected falling edge is lower than the reference voltage VREF, the output of the comparator 11 is turned to the current driver 12; the current driver 12 outputs a pull-down current sink IREF according to the received signal, and outputs IREF to the spur cancellation unit 03 as a first output signal COUT; the voltage value at the input end of the schmitt trigger 32 continuously decreases at the speed of IREF/C1(IREF is the current value of the pull-down current well, and C1 is the capacity of the capacitor 31), and when the voltage value at the input end of the schmitt trigger 32 decreases to the falling edge threshold VTL of the schmitt trigger 32, the output of the schmitt trigger 32 is inverted, so that the second output signal VOUT is driven to become low; if the voltage at the input of the schmitt trigger 32 does not drop to VTL, the low level pulses carried by the input signal VIN are filtered out as glitch noise. The filtered bandwidth formula is: (VDD-VTL) C1/IREF, where VDD is the supply voltage of the schmitt trigger 32.
FIG. 8 is a timing diagram of a normal input signal according to an embodiment of the present invention, and as shown in FIG. 8, the filter bandwidth is designed to be 250nS, and the circuit of the present invention can filter the glitch noise of 200nS pulse width and retain the signal of 300nS pulse width.
Fig. 9 is a timing diagram of an input signal of a different power supply according to an embodiment of the present invention, and as shown in fig. 9, when the amplitude of the input signal VIN is changed, the circuit according to an embodiment of the present invention can still accurately filter the glitch noise with a pulse width of 200nS, and retain the signal with a pulse width of 300 nS.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A signal glitch cancellation circuit, comprising: a comparator unit (01), a reference voltage selection unit (02), and a burr removal unit (03); wherein,
the reference voltage selection unit (02) is used for receiving a first reference Voltage (VH) and a second reference Voltage (VL) and receiving a second output signal (VOUT) output by the glitch elimination unit (03); the reference voltage selection unit (02) determines the first reference Voltage (VH) or the second reference Voltage (VL) as a reference Voltage (VREF) according to a second output signal (VOUT) output by the glitch elimination unit (03), and outputs the reference Voltage (VH) or the second reference Voltage (VL);
the comparator unit (01) is used for receiving an input signal (VIN) and the reference Voltage (VREF), generating a first output signal (COUT) according to the input signal (VIN) and the reference Voltage (VREF) and outputting the first output signal (COUT);
the spur cancellation unit (03) is configured to receive the first output signal (COUT), perform spur cancellation on the first output signal (COUT), and generate a second output signal (VOUT); the glitch elimination unit (03) outputs the second output signal (VOUT) to the outside, and to the reference voltage selection unit (02).
2. A circuit according to claim 1, characterized in that the comparator unit (01) comprises a comparator (11) and a current driver (12); wherein,
a positive input terminal of the comparator (11) receives the input signal (VIN), a negative input terminal of the comparator (11) receives the reference Voltage (VREF), and the comparator (11) compares a rising edge or a falling edge of the input signal (VIN) with the reference Voltage (VREF) and outputs a comparison result; the current driver (12) outputs the first output signal (COUT) according to the comparison result.
3. The circuit according to claim 1, wherein the reference voltage selection unit (02) comprises an inverter (21), a first MOS transistor (22) and a second MOS transistor (23); wherein,
the negative output end of the phase inverter (21) is connected with the grid electrode of the first MOS tube (22), and the positive input end of the phase inverter (21) is connected with the grid electrode of the second MOS tube (23) and receives the second output signal (VOUT);
the source electrode of the first MOS tube (22) receives a first reference Voltage (VH), the source electrode of the second MOS tube (23) receives a second reference Voltage (VL), the first MOS tube (22) is connected with the drain electrode of the second MOS tube (23), and the first reference Voltage (VH) or the second reference Voltage (VL) is determined as the reference Voltage (VREF) according to the level of the second output signal (VOUT) and is output.
4. The circuit according to claim 1, wherein the glitch removal unit (03) comprises a capacitor (31), a schmitt trigger (32), and an inverter (33); wherein,
the positive electrode of the capacitor (31) is connected with the input end of the Schmitt trigger (32) and receives a first output signal (COUT), the output end of the Schmitt trigger (32) is connected with the input end of the inverter (33), and the inverter (33) outputs the second output signal (VOUT).
5. The circuit according to claim 4, wherein the width of the glitch removal signal removed by the glitch removal unit (03) is calculated by the following formula: VTH C1/IREF and (VDD-VTL) C1/IREF; VTH is a rising edge threshold voltage of the Schmitt trigger (32), VDD is a power supply voltage of the Schmitt trigger (32), VTL is a falling edge threshold voltage of the Schmitt trigger (32), C1 is a capacitance of the capacitor (31), and IREF is a current value of the first output signal (COUT).
6. A circuit according to claim 1, characterized in that the comparator unit (01) comprises a load, which load is one or more of a resistive load, a diode load and a current mirror load.
7. The circuit according to claim 2, wherein the current driver (12) in the comparator unit (01) has one or more of a direct mirror load current output, a switch controlled current source output and a switch controlled current sink output.
8. The circuit according to claim 1, wherein the first MOS transistor (22) in the reference voltage selection unit (02) is an NMOS transistor, a PMOS transistor or a complementary switch transistor, and the second MOS transistor (23) is an NMOS transistor, a PMOS transistor or a complementary switch transistor.
9. The circuit according to claim 1, characterized in that the capacitor (31) in the glitch elimination unit (03) is a MOS capacitor, a metal-insulator-metal capacitor (MIM capacitor) or a polysilicon capacitor (POLY capacitor).
10. A circuit according to claim 1, characterized in that the glitch removal unit (03) comprises a capacitor, and a schmitt trigger and/or an inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510580200.3A CN105227162B (en) | 2015-09-11 | 2015-09-11 | A kind of signal burr eliminates circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510580200.3A CN105227162B (en) | 2015-09-11 | 2015-09-11 | A kind of signal burr eliminates circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105227162A true CN105227162A (en) | 2016-01-06 |
| CN105227162B CN105227162B (en) | 2018-03-16 |
Family
ID=54995908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510580200.3A Active CN105227162B (en) | 2015-09-11 | 2015-09-11 | A kind of signal burr eliminates circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105227162B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109813952A (en) * | 2018-12-12 | 2019-05-28 | 珠海亿智电子科技有限公司 | A kind of envelope detected circuit |
| CN112600539A (en) * | 2021-03-03 | 2021-04-02 | 上海亿存芯半导体有限公司 | Circuit for filtering burr |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080157830A1 (en) * | 2006-12-28 | 2008-07-03 | Matsushita Electric Industrial Co., Ltd. | Triangle oscillator and pulse width modulator |
| CN101794613A (en) * | 2009-02-02 | 2010-08-04 | 世界先进积体电路股份有限公司 | Sensing amplifier, memory device and sensing method |
| CN102014017A (en) * | 2010-09-30 | 2011-04-13 | 华为技术有限公司 | Signal detection circuit, method and system |
| CN102291109A (en) * | 2011-04-18 | 2011-12-21 | 烽火通信科技股份有限公司 | Power-on reset circuit of digital integrated circuit supplied with power by chip internal regulator |
| CN204906344U (en) * | 2015-09-11 | 2015-12-23 | 英特格灵芯片(天津)有限公司 | Signal burr cancelling circuit |
-
2015
- 2015-09-11 CN CN201510580200.3A patent/CN105227162B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080157830A1 (en) * | 2006-12-28 | 2008-07-03 | Matsushita Electric Industrial Co., Ltd. | Triangle oscillator and pulse width modulator |
| CN101794613A (en) * | 2009-02-02 | 2010-08-04 | 世界先进积体电路股份有限公司 | Sensing amplifier, memory device and sensing method |
| CN102014017A (en) * | 2010-09-30 | 2011-04-13 | 华为技术有限公司 | Signal detection circuit, method and system |
| CN102291109A (en) * | 2011-04-18 | 2011-12-21 | 烽火通信科技股份有限公司 | Power-on reset circuit of digital integrated circuit supplied with power by chip internal regulator |
| CN204906344U (en) * | 2015-09-11 | 2015-12-23 | 英特格灵芯片(天津)有限公司 | Signal burr cancelling circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109813952A (en) * | 2018-12-12 | 2019-05-28 | 珠海亿智电子科技有限公司 | A kind of envelope detected circuit |
| CN112600539A (en) * | 2021-03-03 | 2021-04-02 | 上海亿存芯半导体有限公司 | Circuit for filtering burr |
| CN112600539B (en) * | 2021-03-03 | 2021-05-18 | 上海亿存芯半导体有限公司 | Circuit for filtering burr |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105227162B (en) | 2018-03-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8519762B2 (en) | Adjusting circuit of duty cycle and its method | |
| KR100994386B1 (en) | Output circuit | |
| CN104113211B (en) | Low-power-dissipation hysteresis voltage detection circuit applied to energy acquisition system | |
| US20140111258A1 (en) | Power-on-Reset and Supply Brown Out Detection Circuit with Programmability | |
| CN105871207B (en) | Power supply changeover device | |
| CN105227162B (en) | A kind of signal burr eliminates circuit | |
| WO2017016319A1 (en) | Dv/dt detection and protection apparatus and method | |
| CN205212814U (en) | Level conversion's device | |
| US20150146772A1 (en) | Data receiver and fail-safe circuit | |
| CN112600539B (en) | Circuit for filtering burr | |
| CN204906344U (en) | Signal burr cancelling circuit | |
| US20140266361A1 (en) | Duty cycle correction circuit | |
| CN105141305A (en) | Level conversion method and device | |
| CN205811849U (en) | The charge pump system that driving force is stable | |
| CN116781046A (en) | Hysteresis comparator | |
| CN210780702U (en) | Filter circuit | |
| US11770120B2 (en) | Bootstrap circuit supporting fast charging and discharging and chip | |
| CN110673679B (en) | Digital voltage stabilizer | |
| CN117200752B (en) | Synchronous high-frequency square wave signal circuit | |
| TWI829286B (en) | Glitch-free low-pass filter circuit and system circuit using the same | |
| CN216451352U (en) | Analog circuit for realizing clock frequency comparison | |
| US7019563B2 (en) | Waveform shaping circuit | |
| CN110850201B (en) | High-frequency narrow pulse detection locking circuit and method | |
| CN101977039B (en) | Congestion control based monostable circuit | |
| CN216122367U (en) | Filter circuit with quick response |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201223 Address after: 7 / F, building C, no.3000, Longdong Avenue, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai 201203 Patentee after: WILL SEMICONDUCTOR Ltd. Address before: Room 2701-1, building 2, TEDA service outsourcing park, 19 Xinhuan West Road, Tanggu District, Tianjin, 300457 Patentee before: INTERNATIONAL GREEN CHIP (TIANJIN) Co.,Ltd. |
|
| TR01 | Transfer of patent right |