CN116781046A

CN116781046A - Hysteresis comparator

Info

Publication number: CN116781046A
Application number: CN202310775347.2A
Authority: CN
Inventors: 程君永
Original assignee: Yijing Microelectronics Taizhou Co ltd
Current assignee: Yijing Microelectronics Taizhou Co ltd
Priority date: 2023-06-28
Filing date: 2023-06-28
Publication date: 2023-09-19

Abstract

The application discloses a hysteresis comparator, comprising: the bias current module is used for providing bias current for the hysteresis control module, the comparison module and the driving module; the comparison module is used for receiving the voltage signal input from the first external interface, generating a comparison signal according to the voltage signal and outputting the comparison signal to the driving module; the hysteresis control module is used for receiving a hysteresis control signal input from the second external interface, generating a hysteresis time length according to the hysteresis control signal and outputting the hysteresis time length to the comparison module; the comparison module is also used for determining a first moment when the hysteresis time is received, and continuously outputting a comparison signal of the first moment to the driving module in the hysteresis time; the driving module is used for outputting a comparison signal to the third external interface. The hysteresis comparator can adjust the hysteresis quantity according to the actual situation.

Description

Hysteresis comparator

Technical Field

The application relates to the technical field of electronics, in particular to a hysteresis comparator.

Background

A hysteresis comparator is a comparator circuit with hysteresis characteristics that can compare an input signal with a threshold value and output a corresponding signal. The hysteresis comparator has certain hysteresis, can effectively reduce misjudgment caused by tiny fluctuation of an input signal, and filters noise and interference in the input signal, thereby improving the stability and noise resistance of the system.

When the hysteresis comparator is in a complex environment, it is necessary to adjust the appropriate hysteresis according to the interference of different signals, so as to resist noise. In the prior art, the hysteresis of the hysteresis comparator is usually determined by parameters of circuit elements, and cannot be adjusted according to actual conditions.

Therefore, there is a need for a hysteresis comparator with adjustable hysteresis.

Disclosure of Invention

The application provides a hysteresis comparator which can adjust the hysteresis according to actual conditions.

In a first aspect, the present application provides a hysteresis comparator comprising: the device comprises a bias current module, a hysteresis control module, a comparison module and a driving module, wherein:

the output end of the bias current module is respectively connected with the power end of the hysteresis control module, the power end of the comparison module and the power end of the driving module, and the bias current is used for providing bias current for the hysteresis control module, the comparison module and the driving module;

the first end of the comparison module is connected with the first end of the hysteresis control module, and the second end of the comparison module is connected with the first end of the driving module;

The second end of the hysteresis control module is connected with the first end of the driving module;

the comparison module is used for receiving a voltage signal input from a first external interface, generating a comparison signal according to the voltage signal, and outputting the comparison signal to the driving module;

the hysteresis control module is used for receiving a hysteresis control signal input from a second external interface, generating a hysteresis time according to the hysteresis control signal, and outputting the hysteresis time to the comparison module;

the comparison module is further configured to determine a first time when the hysteresis duration is received, and continuously output a comparison signal of the first time to the driving module within the hysteresis duration;

the driving module is used for outputting the comparison signal output by the comparison module to a third external interface.

By adopting the technical scheme, when various interference sources exist in the hysteresis comparator in actual application, hysteresis time can be generated according to the hysteresis control signal input by the second external interface.

Optionally, the driving module is a front stage driving module, and the bias current module includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube and a second NMOS tube, where:

the drain electrode of the first PMOS tube is respectively connected with the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube, the source electrode of the first PMOS tube is connected with a direct current power supply, and the grid electrode of the first PMOS tube is connected with a bias voltage;

the drain electrode of the second NMOS tube is respectively connected with the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube;

the drain electrode of the third PMOS tube is connected with the hysteresis control module;

the drain electrode of the fourth PMOS tube is connected with the front-stage driving module;

the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are grounded.

By adopting the technical scheme, the bias current module can provide stable static working current for the hysteresis comparator, and the bias current of the hysteresis comparator is configured by different width-to-length ratios of all the pipes so as to maintain the precision and stability of the hysteresis comparator.

Optionally, the driving module is a front driving module, the first external interface includes a first voltage input interface and a second voltage input interface, and the comparing module includes a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube and a sixth NMOS tube, where:

the grid electrode of the fifth PMOS tube is connected with the first voltage input interface, the source electrode of the fifth PMOS tube is connected with the first end of the hysteresis control module, and the drain electrode of the fifth PMOS tube is respectively connected with the grid electrode of the third NMOS tube, the drain electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube;

the source electrode of the sixth PMOS tube is connected with the first end of the hysteresis control module, the grid electrode of the sixth PMOS tube is connected with the second voltage input interface, and the drain electrode of the sixth PMOS tube is respectively connected with the drain electrode of the fourth NMOS tube and the grid electrode of the sixth NMOS tube;

the drain electrode of the sixth NMOS tube is respectively connected with the output end of the bias current module and the first end of the front-stage driving module, and the source electrode of the sixth NMOS tube is grounded;

and the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are grounded.

By adopting the technical scheme, the current of the comparison module is provided by the bias current module, and when the input voltages of the input signals INP or INN are different, the current flowing through the fifth PMOS tube and the sixth PMOS tube are different. And if the current flowing through the fifth PMOS tube is larger than the current flowing through the sixth PMOS tube, the grid electrode of the sixth NMOS tube is high level, and if the current flowing through the fifth PMOS tube is smaller than the current flowing through the sixth PMOS tube, the grid electrode of the sixth NMOS tube is low level, so that quick response to an input signal is realized.

Optionally, the driving module is a front driving module, the hysteresis control module includes at least two hysteresis control units, a hysteresis output unit, a constant current source unit and a feedback unit, wherein:

each hysteresis control unit is connected step by step, the first hysteresis control unit is connected with the bias current module, and the last hysteresis control unit is connected with the first end of the hysteresis output unit;

the second end of the hysteresis output unit is connected with one end of the feedback unit, and the third end of the hysteresis output unit is connected with the first end of the constant current source unit;

the second end of the constant current source unit is connected with the bias current module, and the third end of the constant current source unit is grounded;

The other end of the feedback unit is connected with the first end of the front-stage driving module.

By adopting the technical scheme, the hysteresis quantity control unit can generate response of the delayed output signal according to the control input signal, thereby realizing hysteresis characteristics of the hysteresis comparator and enabling the output signal to be more stable and reliable.

Optionally, the hysteresis control module includes a first hysteresis control unit, a second hysteresis control unit, a third hysteresis control unit, a fourth hysteresis control unit, the hysteresis output unit, the constant current source unit and the feedback unit, the second external interface includes a first signal input interface, a second signal input interface, a third signal input interface, a fourth signal input interface, the first hysteresis control unit includes a thirteenth NMOS tube, a fourteenth NMOS tube, a first resistor and a second resistor, the second hysteresis control unit includes a twelfth NMOS tube, a fifteenth NMOS tube, a third resistor and a fourth resistor, the third hysteresis control unit includes an eleventh NMOS tube, a sixteenth NMOS tube, a fifth resistor and a sixth resistor, the fourth hysteresis control unit includes a tenth NMOS tube, a seventeenth NMOS tube, a seventh resistor and an eighth resistor, the constant current source unit is a fifth NMOS tube, the feedback unit includes an eighth NMOS tube, a ninth PMOS tube, an eighth PMOS tube and a ninth resistor, wherein:

The grid electrode of the thirteenth NMOS tube is respectively connected with the first signal input interface and the grid electrode of the fourteenth NMOS tube, the drain electrode of the thirteenth NMOS tube is respectively connected with one end of the first resistor, one end of the second resistor, the drain electrode of the fourteenth NMOS tube and the bias current module, and the source electrode of the thirteenth NMOS tube is respectively connected with the other end of the first resistor, the drain electrode of the twelfth NMOS tube and one end of the third resistor;

the source electrode of the fourteenth NMOS tube is respectively connected with the other end of the second resistor, one end of the fourth resistor and the drain electrode of the fifteenth NMOS tube;

the grid electrode of the twelfth NMOS tube is respectively connected with the second signal input interface and the grid electrode of the fifteenth NMOS tube, and the source electrode of the second NMOS tube is respectively connected with the other end of the third resistor, one end of the fifth resistor and the drain electrode of the eleventh NMOS tube;

the source electrode of the fifteenth NMOS tube is respectively connected with the other end of the fourth resistor, one end of the sixth resistor and the drain electrode of the sixteenth NMOS tube;

the grid electrode of the eleventh NMOS tube is respectively connected with the third signal input interface and the grid electrode of the sixteenth NMOS tube; the source electrode of the eleventh NMOS tube is respectively connected with the other end of the fifth resistor, the drain electrode of the tenth NMOS switch and one end of the seventh resistor;

The source electrode of the sixteenth NMOS tube is respectively connected with the other end of the sixth resistor, the drain electrode of the seventeenth NMOS tube and one end of the eighth resistor;

the grid electrode of the tenth NMOS tube is respectively connected with the fourth signal input interface and the grid electrode of the seventeenth NMOS tube, and the source electrode of the tenth NMOS tube is respectively connected with the other end of the seventh resistor, one end of the comparison module and the source electrode of the seventh PMOS tube;

the source electrode of the seventeenth NMOS tube is respectively connected with the other end of the eighth resistor and one end of the comparison module;

the drain electrode of the seventh PMOS tube is connected with the drain electrode of the fifth NMOS tube, and the grid electrode of the seventh PMOS tube is respectively connected with the drain electrode of the ninth PMOS tube and the drain electrode of the seventh NMOS tube;

the grid electrode of the fifth NMOS tube is connected with the bias current module, and the source electrode of the fifth NMOS tube is grounded;

the source electrode of the ninth PMOS tube is connected with a direct current power supply, and the grid electrode of the ninth PMOS tube is respectively connected with the grid electrode of the seventh NMOS tube, the drain electrode of the eighth PMOS tube and the drain electrode of the eighth NMOS tube;

the grid electrode of the eighth PMOS tube is respectively connected with one end of the front-stage driving module and the grid electrode of the eighth NMOS tube;

And the source electrode of the seventh NMOS tube and the source electrode of the eighth NMOS tube are respectively grounded.

By adopting the technical scheme, 4 hysteresis control units are adopted to form a hysteresis control module, and 16 control combinations can be generated by inputting signals F1, F2, F3, F4=0000 to F1, F2, F3 and F4=1111, so that the precision of the hysteresis control signals can be further improved.

Optionally, the driving module is a rear driving module, and the rear driving module includes a tenth PMOS tube and a ninth NMOS tube, a fifteenth PMOS tube and a twenty-fourth NMOS tube, where:

the grid electrode of the fifteenth PMOS tube is respectively connected with the grid electrode of the twenty-fourth NMOS tube, the output end of the bias current module, the second end of the comparison module and the second end of the hysteresis control module, the drain electrode of the fifteenth PMOS tube is respectively connected with the drain electrode of the twenty-fourth NMOS tube, the grid electrode of the tenth PMOS tube and the grid electrode of the ninth NMOS tube, and the source electrode of the fifteenth PMOS tube, the source electrode of the tenth PMOS tube and the direct current source are connected;

the drain electrode of the tenth PMOS tube is respectively connected with the drain electrode of the ninth NMOS tube and the third external interface;

and the source electrode of the twenty-fourth NMOS tube and the source electrode of the ninth NMOS tube are grounded.

By adopting the technical scheme, the rear-stage driving module has the capability of converting the output of the comparison module and the hysteresis control module into the driving/closing of the external device, and can be used for controlling the operation of other circuits or external devices.

Optionally, the hysteresis comparator further includes: a reference current module, wherein:

one end of the reference current module is connected with the input end of the bias current module, and the reference current module is used for generating reference current for the bias current module.

By adopting the technical scheme, the reference current module can provide stable current for the bias current module.

Optionally, the reference current module includes: eighteenth NMOS pipe, nineteenth NMOS pipe, twentieth NMOS pipe, eleventh PMOS pipe and ninth resistance, wherein:

the drain electrode of the eighteenth NMOS tube is respectively connected with the drain electrode of the eleventh PMOS tube, the grid electrode of the eleventh PMOS tube and the input end of the bias current module, the grid electrode of the eighteenth NMOS tube is connected with one end of the ninth resistor, and the grid electrode of the eighteenth NMOS tube is respectively connected with the grid electrode of the nineteenth NMOS tube, the drain electrode of the nineteenth NMOS tube, the grid electrode of the twentieth NMOS tube and the source electrode of the twentieth NMOS tube;

The source electrode of the eleventh PMOS tube and the drain electrode of the twentieth NMOS tube are respectively connected with a direct current power supply;

and the source electrode of the nineteenth NMOS tube and the other end of the ninth resistor are respectively grounded.

Optionally, the hysteresis comparator further includes: the driving module is a front driving module, wherein:

one end of the front-stage driving module is connected with the second end of the comparison module and the second end of the hysteresis control module respectively, the other end of the front-stage driving module is connected with the first end of the front-stage driving module, and the front-stage driving module is used for filtering noise interference in the voltage signal.

By adopting the technical scheme, the front-stage driving module can effectively reduce noise output by the comparator and improve the precision of the output signal of the hysteresis comparator.

Optionally, the front stage driving module includes: twelfth PMOS pipe, thirteenth PMOS pipe, fourteenth PMOS pipe, twenty-first NMOS pipe, twenty-second NMOS pipe and twenty-third NMOS pipe, wherein:

the grid electrode of the twenty-second NMOS tube is respectively connected with the grid electrode of the twelfth PMOS tube, the grid electrode of the thirteenth PMOS tube, the grid electrode of the twenty-first NMOS tube, the second end of the comparison module, the second end of the hysteresis control module and the output end of the bias current module, the drain electrode of the twenty-second NMOS tube is respectively connected with the drain electrode of the thirteenth PMOS tube, the grid electrode of the twenty-third NMOS tube, the grid electrode of the fourteenth PMOS tube and the first end of the front-stage driving module, and the source electrode of the twenty-second NMOS tube is respectively connected with the source electrode of the twenty-third NMOS tube and the drain electrode of the twenty-first NMOS tube;

The source electrode of the thirteenth PMOS tube is respectively connected with the source electrode of the fourteenth PMOS tube and the drain electrode of the twelfth PMOS tube;

the source electrode of the twelfth PMOS tube and the drain electrode of the twenty-third NMOS tube are respectively connected with a direct current power supply;

and the source electrode of the twenty-first NMOS tube and the drain electrode of the fourteenth PMOS tube are respectively grounded.

In summary, one or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:

when various interference sources exist in the hysteresis comparator in practical application, hysteresis time can be generated according to a hysteresis control signal input by the second external interface.

Drawings

FIG. 1 is a schematic diagram of a hysteresis comparator according to an embodiment of the present application;

FIG. 2 is a schematic circuit diagram of a bias current module according to an embodiment of the present application;

FIG. 3 is a schematic circuit diagram of a comparison module according to an embodiment of the present application;

FIG. 4 is a schematic circuit diagram of a hysteresis control module according to an embodiment of the present application;

FIG. 5 is a schematic circuit diagram of another hysteresis control module according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a hysteresis comparator output waveform according to an embodiment of the present application;

fig. 7 is a schematic circuit diagram of a rear driving module according to an embodiment of the present application;

FIG. 8 is a schematic circuit diagram of a reference current module according to an embodiment of the present application;

FIG. 9 is a schematic circuit diagram of another front-end driving module according to an embodiment of the present application;

fig. 10 is a schematic circuit diagram of another hysteresis comparator according to an embodiment of the present application.

Detailed Description

In order that those skilled in the art will better understand the technical solutions in the present specification, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments.

In describing embodiments of the present application, words such as "for example" or "for example" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "such as" or "for example" in embodiments of the application should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "or" for example "is intended to present related concepts in a concrete fashion.

In the description of embodiments of the application, the term "plurality" means two or more. For example, a plurality of systems means two or more systems, and a plurality of screen terminals means two or more screen terminals. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating an indicated technical feature. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

The present application will be described in detail with reference to specific examples.

Referring to fig. 1, a schematic circuit diagram of a hysteresis comparator provided by the present application includes: the device comprises a bias current module, a hysteresis control module, a comparison module and a driving module, wherein: the output end of the bias current module is respectively connected with the power end of the hysteresis control module, the power end of the comparison module and the power end of the driving module; the first end of the comparison module is connected with the first end of the hysteresis control module, and the second end of the comparison module is connected with the first end of the driving module; the second end of the hysteresis control module is connected with the first end of the driving module.

The bias current module is used for providing bias current for the hysteresis control module, the comparison module and the driving module so as to ensure the normal operation of the hysteresis comparator. The comparison module is provided with a first external interface, the first external interface is provided with two signal input ends, and the comparison module can receive two voltage signals input by the first external interface, compare the two voltage signals and output comparison signals to the driving module.

The hysteresis control module is provided with a second external interface, the second external interface can be provided with more than two signal input ends, and the hysteresis control module can generate a delay signal according to a hysteresis control signal input by the second external interface and output the delay signal to the comparison module. The delay signal is used to generate a delay time, which in the embodiment of the application is defined as a delay time. When the hysteresis control module outputs the hysteresis time to the comparison module, the time when the comparison module receives the hysteresis time may be defined as the first time. At this time, the comparison module keeps the comparison signal output at the first moment unchanged within the hysteresis time length and outputs the comparison signal to the driving module.

The driving module is provided with a third external interface, and can convert the comparison signal output by the comparison module into a level signal and output the level signal to the third external interface.

Specifically, the hysteresis comparator has certain hysteresis, so that misjudgment caused by tiny fluctuation of an input signal can be effectively reduced, noise and interference in the input signal can be filtered, and the stability and noise resistance of the system are improved. However, due to various interference sources in practical application, the fixed hysteresis quantity set according to the parameters of the circuit element may not meet the practical requirements, and the hysteresis quantity control module in the hysteresis comparator provided by the embodiment of the application can generate hysteresis duration according to the hysteresis quantity control signal input by the second external interface, and the hysteresis quantity can be adjusted according to the practical environment.

Referring to fig. 2, as an alternative embodiment, a circuit schematic diagram of a bias current module provided by the present application is shown, wherein a driving module is a front-stage driving module, and the bias current module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a second NMOS transistor, wherein: the drain electrode of the first PMOS tube is respectively connected with the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the power supply electrode of the comparator module, the source electrode of the first PMOS tube is connected with the direct current power supply, and the grid electrode of the first PMOS tube is grounded; the drain electrode of the second NMOS tube is respectively connected with the drain electrode of the second PMOS tube, the grid electrode of the second PMOS tube, the drain electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube; the drain electrode of the third PMOS tube is connected with the power electrode of the hysteresis control module; the drain electrode of the fourth PMOS tube is connected with the power electrode of the front-stage driving module; the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are grounded.

The bias current module can provide stable static working current for the hysteresis comparator, and the bias current of the hysteresis comparator is configured by different width-to-length ratios of all the pipes so as to maintain the precision and stability of the hysteresis comparator. Specifically, the source of PMOS1 is connected to a dc power supply, and its drain is connected to the drain of NMOS1, the gate of NMOS2, and the comparator module, respectively. When PMOS1 is normally on, current flows through NMOS1 and voltages are generated at the gates of NMOS1 and NMOS 2. The current of NMOS1 is determined by the pipe flowing through PMOS1, the current flowing through NMOS2 can be adjusted by changing the width-to-length ratio, and other devices of the comparator circuit are supplied with current by designing the appropriate width-to-length ratios of PMOS2, PMOS3 and PMOS 4.

On the basis of the embodiment, as an alternative embodiment, please refer to fig. 3, which is a schematic circuit diagram of a comparison module provided by the present application, the driving module is a front-stage driving module, the first external interface includes a first voltage input interface and a second voltage input interface, and the comparison module includes a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a sixth NMOS transistor, wherein: the grid electrode of the fifth PMOS tube is connected with the first voltage input interface, the source electrode of the fifth PMOS tube is connected with the first end of the hysteresis control module, and the drain electrode of the fifth PMOS tube is respectively connected with the grid electrode of the third NMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube; the source electrode of the sixth PMOS tube is connected with the first end of the hysteresis control module, the grid electrode of the sixth PMOS tube is connected with the second voltage input interface, and the drain electrode of the sixth PMOS tube is respectively connected with the drain electrode of the fourth NMOS tube and the grid electrode of the sixth NMOS tube; the drain electrode of the sixth NMOS tube is respectively connected with the output end of the bias current module and the first end of the front-stage driving module, and the source electrode of the sixth NMOS tube is grounded; the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are grounded.

The current of the comparison module is provided by the bias current module, and when the input voltages of the input signals INP or INN are different, the magnitudes of the currents flowing through the fifth PMOS transistor and the sixth PMOS transistor are different. And if the current flowing through the fifth PMOS tube is larger than the current flowing through the sixth PMOS tube, the grid electrode of the sixth NMOS tube is high level, and if the current flowing through the fifth PMOS tube is smaller than the current flowing through the sixth PMOS tube, the grid electrode of the sixth NMOS tube is low level, so that quick response to an input signal is realized.

Specifically, the gate of PMOS5 is connected to the first voltage input interface, the source is connected to the first end of the hysteresis control module, and the drain is connected to the gate of NMOS3, the drain of NMOS3, and the gate of NMOS4, respectively. When the voltage of the first voltage input interface is lower than that of the second voltage input interface, the drain electrode potential of the PMOS5 rises, the grid electrode potential of the NMOS3 and the grid electrode potential of the NMOS4 rise correspondingly, the current provided by the bias current module flows through the PMOS5 and the NMOS3, the current is mirrored to the NMOS4, and the current is gradually increased.

Further, the source of the PMOS6 is connected to the first end of the hysteresis control module, the drain is connected to the drain of the NMOS4 and the gate of the NMOS6, respectively, and the gate is connected to the second voltage input interface. When the voltage of the second voltage input interface is higher than that of the first voltage input interface, the drain potential of the PMOS6 is lowered, so that the drain voltage of the NMOS4 is also lowered, and the gate potential of the NMOS6 is correspondingly lowered, thereby converting the input signal to the gate of the NMOS 6.

The comparison module is provided with a bias current generation module, and mainly comprises an NMOS18, a high-value resistor R1, a PMOS2, a PMOS3, a PMOS4, an NMOS1 and an NMOS 2. The gate of the NMOS18 is controlled by the previously generated reference voltage, and the reference current is obtained by subtracting the on voltage of the NMOS18 from the reference voltage to obtain the source voltage of the NMOS18 and dividing the source voltage by the resistance of this R1. The resistor type of R1 adopts a high-value polycrystalline resistor, and because the negative temperature characteristic of the high-value polycrystalline resistor band can cancel the negative temperature characteristic of the NMOS18, the influence of the temperature on the reference current is reduced. By the reference current, a plurality of branch currents are generated through the mirror image again for other circuit modules to use.

On the basis of the embodiment, as an optional embodiment, please refer to fig. 4, which is a schematic circuit diagram of a hysteresis control module provided by the present application, wherein the driving module is a front driving module, and the hysteresis control module includes at least two hysteresis control units, a hysteresis output unit, a constant current source unit and a feedback unit, wherein: each hysteresis control unit is connected step by step, the first hysteresis control unit is connected with the bias current module, and the last hysteresis control unit is connected with the first end of the hysteresis output unit; the second end of the hysteresis output unit is connected with one end of the feedback unit, and the third end of the hysteresis output unit is connected with the first end of the constant current source unit; the second end of the constant current source unit is connected with the bias current module, and the third end of the constant current source unit is grounded; the other end of the feedback unit is connected with the first end of the front-stage driving module.

The hysteresis control module is an important part of the hysteresis comparator, and mainly aims to provide a hysteresis control signal for the comparison module, namely a hysteresis effect can be generated when an input signal suddenly changes, so as to avoid the influence of noise on an output signal.

Further, the hysteresis control unit is typically implemented by a combination of PMOS and NMOS transistors, where the PMOS transistor has a negative bias and the NMOS transistor has a positive bias. When the voltage of the input signal of the comparator suddenly changes, if no hysteresis effect exists, the output signal is unstable and noise is generated, so that the subsequent circuit is influenced. In order to avoid this, it is necessary to control the magnitude of the hysteresis by the hysteresis control signal when the input voltage is suddenly changed, so as to realize stable control of the output signal. Therefore, the main function of the hysteresis control unit is to delay the response of the output signal, thereby realizing hysteresis characteristics and enabling the output signal to be more stable and reliable.

Further, the number of the hysteresis quantity control units is at least two, the hysteresis quantity control units are connected step by step, the first hysteresis quantity control unit is connected with the bias current module, and the last hysteresis quantity control unit is connected with the first end of the hysteresis quantity output unit. In the hysteresis control units, a first hysteresis control unit receives the static current provided by the bias current module, and generates corresponding hysteresis voltage according to the magnitude and the direction of the control voltage of the first hysteresis control unit so as to control a subsequent hysteresis control unit to perform corresponding control.

Further, in the hysteresis control module, different hysteresis control units can control different circuit parts, so that stable control of an output signal is realized. When a plurality of hysteresis control units are connected step by step, the latter hysteresis control unit controls on the basis of the former hysteresis control unit so as to realize more accurate circuit control. Therefore, the hysteresis control unit is used for respectively controlling the conduction states of the PMOS tube and the NMOS tube under different control voltages so as to realize the control of the falling delay of the output signal and further realize the hysteresis characteristic of the output signal.

On the basis of the embodiment, as an optional embodiment, please refer to fig. 5, which is a schematic circuit diagram of another hysteresis control module provided by the present application, the hysteresis control module includes a first hysteresis control unit, a second hysteresis control unit, a third hysteresis control unit, a fourth hysteresis control unit, a hysteresis output unit, a constant current source unit and a feedback unit, the second external interface includes a first signal input interface, a second signal input interface, a third signal input interface and a fourth signal input interface, the first hysteresis control unit includes a thirteenth NMOS tube NMOS13, a fourteenth NMOS tube, a first resistor R1 and a second resistor R2, the second hysteresis control unit includes a twelfth NMOS tube NMOS12, a fifteenth NMOS tube, a third resistor R3 and a fourth resistor R4, the third hysteresis control unit includes an eleventh NMOS tube NMOS11, a sixteenth NMOS tube, a fifth resistor R5 and a sixth resistor R6, the fourth hysteresis control unit includes a seventeenth NMOS tube NMOS10, an NMOS tube, a seventh NMOS resistor R7 and an eighth PMOS resistor R8, the eighth NMOS output unit is a PMOS transistor PMOS8, the ninth NMOS output unit is a PMOS transistor PMOS8, and the ninth NMOS unit is a PMOS transistor NMOS8, and the eighth resistor R8 is a PMOS unit is a PMOS transistor NMOS 9:

The grid electrode of the NMOS13 is respectively connected with the first signal input interface and the grid electrode of the NMOS14, the drain electrode of the NMOS13 is respectively connected with one end of R1, one end of R2, the drain electrode of the NMOS14 and the bias current module, and the source electrode of the NMOS13 is respectively connected with the other end of R1, the drain electrode of the NMOS12 and one end of R3; the source electrode of the NMOS14 is respectively connected with the other end of the R2, one end of the R4 and the drain electrode of the NMOS 15; the grid electrode of the NMOS12 is respectively connected with the second signal input interface and the grid electrode of the NMOS15, and the source electrode of the NMOS2 is respectively connected with the other end of the R3, one end of the R5 and the drain electrode of the NMOS 11; the source electrode of the NMOS15 is respectively connected with the other end of the R4, one end of the R6 and the drain electrode of the NMOS 16; the grid electrode of the NMOS11 is respectively connected with the third signal input interface and the grid electrode of the NMOS 16; the source electrode of the NMOS11 is respectively connected with the other end of the R5, the drain electrode of the tenth NMOS and one end of the R7; the source electrode of the NMOS16 is respectively connected with the other end of the R6, the drain electrode of the NMOS17 and one end of the R8; the grid electrode of the NMOS10 is respectively connected with the fourth signal input interface and the grid electrode of the NMOS17, and the source electrode of the NMOS10 is respectively connected with the other end of the R7, one end of the comparison module and the source electrode of the PMOS 7; the source electrode of the NMOS17 is respectively connected with the other end of the R8 and one end of the comparison module; the drain electrode of the PMOS7 is connected with the drain electrode of the NMOS5, and the grid electrode of the PMOS7 is respectively connected with the drain electrode of the PMOS9 and the drain electrode of the NMOS 7; the grid electrode of the NMOS5 is connected with the bias current module, and the source electrode of the NMOS5 is grounded; the source electrode of the PMOS9 is connected with a direct current power supply, and the grid electrode of the PMOS9 is respectively connected with the grid electrode of the NMOS7, the drain electrode of the PMOS8 and the drain electrode of the NMOS 8; the grid electrode of the PMOS8 is respectively connected with one end of the front-stage driving module and the grid electrode of the NMOS 8; the source of NMOS7 and the source of NMOS8 are grounded, respectively.

For example, the hysteresis control module is provided with 4 hysteresis control units, i.e. the input hysteresis control signals are 4-bit binary numbers, i.e. the input signals F1, F2, F3, f4=0000 to F1, F2, F3, f4=1111, and 16 control combinations can be generated. According to different input signals, the on-resistance values are different, so that 16 different voltages can be generated at the source electrode of the PMOS5, and finally 16-stage hysteresis voltages are generated.

For example, when f1=f2=f3=f4=1, the resistors R1 to R8 are shorted by the NMOS10 to NMOS17, and the voltage drop generated in the NMOS10 to NMOS17 is small and negligible, so the source voltage of the PMOS5 tube and the source voltage of the PMOS6 tube are substantially equal, and the hysteresis is minimal.

Referring to fig. 6, fig. 6 is a schematic diagram of an output waveform of a hysteresis comparator according to an embodiment of the present application. The first external interface of the comparison module inputs a first voltage and a second voltage signal, and the comparison module generates a comparison signal according to the first voltage signal and the second voltage signal, namely, when the first voltage signal is larger than the second voltage signal, the comparison signal (output voltage) is at a low level, and when the first voltage signal is smaller than the second voltage signal, the output voltage is at a high level. When f1=f2=f3=f4=gnd, NMOS10 to NMOS17 are turned off, the resistors R1 to R8 are connected in series, the PMOS7 is turned on by feedback in the circuit, the source voltage of the PMOS5 is lower than the source voltage of the PMOS6 under the action of the branch current of the NMOS5, the hysteresis amount generated at this time is the largest, that is, the output voltage is kept at a high level unchanged in the time period from the point a to the point B, and the AB is the delay time period.

The NMOS5 in the constant current source unit is used as a constant current source, and the current of the whole hysteresis control module is controlled through the constant current provided by the bias current module, so that the normal operation of the whole system is ensured.

In the feedback unit, a feedback signal is output from the PMOS7, passes through the front-stage driving module, passes through the drain electrode of the PMOS8 and the grid electrode of the PMOS9, and then returns to the hysteresis control module through the NMOS9 and the NMOS8 to form a feedback loop, so that the output of the whole hysteresis control module is more stable and reliable.

On the basis of the embodiment, as an alternative embodiment, please refer to fig. 7, which is a schematic circuit diagram of a post-stage driving module provided by the present application, the post-stage driving module includes a tenth PMOS transistor PMOS10 and a ninth NMOS transistor NMOS9, a fifteenth PMOS transistor PMOS15 and a twenty-fourth NMOS transistor NMOS24, wherein:

The drain electrode of the tenth PMOS tube is respectively connected with the drain electrode of the ninth NMOS tube and a third external interface;

the source electrode of the twenty-fourth NMOS tube and the source electrode of the ninth NMOS tube are grounded.

Illustratively, the rear stage driver modules include PMOS10, PMOS15, NMOS9, and NMOS24. When the outputs of the comparison module and the hysteresis control module satisfy certain conditions, the PMOS10 and the NMOS9 function as switches to connect the external device to the positive voltage, thereby realizing driving of the external device. Specifically, when the outputs of the comparison module and the hysteresis control module respectively satisfy the conditions, the PMOS15 is turned off, the PMOS10 is turned on, the NMOS24 is turned on, the NMOS9 is turned off, and the external device is connected to the positive voltage, at which time the external device is in an on state. On the contrary, when the above output does not meet the condition, PMOS15 is turned on, PMOS10 is turned off, NMOS24 is turned off, NMOS9 is turned on, and the external device is grounded, thereby realizing the turn-off. Further, the latter driving module has the capability of converting the outputs of the comparison module and the hysteresis control module into driving/turning off the external device, and can be used for controlling the operation of other circuits or external devices.

On the basis of the embodiment, as an alternative embodiment, please refer to fig. 8, which is a schematic circuit diagram of a reference current module provided by the present application, the reference current module includes: an eighteenth NMOS transistor NMOS18, a nineteenth NMOS transistor NMOS19, a twentieth NMOS transistor NMOS20, an eleventh PMOS transistor PMOS11, and a ninth resistor R9, wherein:

The drain electrode of the NMOS18 is respectively connected with the drain electrode of the PMOS11, the grid electrode of the PMOS11 and the input end of the bias current module, the source electrode of the NMOS18 is connected with one end of the R9, and the grid electrode of the NMOS18 is respectively connected with the grid electrode of the NMOS19, the drain electrode of the NMOS19, the grid electrode of the NMOS20 and the source electrode of the NMOS 20; the source electrode of the PMOS11 and the drain electrode of the NMOS20 are respectively connected with a direct current power supply; the source of NMOS19 and the other end of R9 are grounded, respectively.

Specifically, the reference current module mainly comprises an enhancement type NMOS tube NMOS19 and a depletion type NMOS tube NMOS 20. Wherein the grid electrode and the source electrode of the NMOS20 are in short circuit, the grid electrode and the drain electrode of the NMOS19 are in short circuit, and both NMOS tubes work in a saturation region. The NMOS19 and NMOS20 tube turn-on voltages have negative temperature characteristics and positive temperature characteristics, and the width-to-length ratio of the NMOS19 and the NMOS20 is adjusted to offset the positive temperature voltage and the negative temperature voltage, so that the reference voltage which is not affected by temperature is finally generated. The reference voltage structure adopts only two tubes, so that compared with other band gap reference circuits, the reference voltage structure has the advantages of simpler circuit, lower power consumption and smaller area occupied by a chip, thereby saving the cost of the hysteresis comparator.

One end of the reference current module is connected with the input end of the bias current module, and the reference current module is used for providing stable current which does not change along with the power supply voltage for the bias current module.

When the input voltage is greater than the gate-source voltage of the NMOS19, a reference voltage is generated by the two tubes of the NMOS19 and the NMOS20, the grid electrode of the NMOS18 is controlled, the starting voltage of the NMOS18 tube is subtracted from the reference voltage to obtain the source voltage of the NMOS18 tube, and the source voltage is divided by the resistor of the R1 to obtain the reference current. The resistor type of R1 adopts a high-value polycrystalline resistor, and the negative temperature characteristic of the high-value polycrystalline resistor can be mutually offset with the negative temperature characteristic of the NMOS18 tube, so that the influence of temperature on the reference current is reduced. Through the reference current, a plurality of branch currents are generated through the mirror image, and the current is convenient for other circuits to use.

On the basis of the embodiment, as an alternative embodiment, please refer to fig. 9, which is a schematic circuit diagram of a front-stage driving module provided by the present application, in which the driving module is used as a front-stage driving module, the front-stage driving module includes: a twelfth PMOS transistor PMOS12, a thirteenth PMOS transistor PMOS13, a fourteenth PMOS transistor PMOS14, a twenty-first NMOS transistor NMOS21, a twenty-second NMOS transistor NMOS22, and a twenty-third NMOS transistor NMOS23, wherein:

the grid electrode of the NMOS22 is respectively connected with the grid electrode of the PMOS12, the grid electrode of the PMOS13, the grid electrode of the NMOS21, the second end of the comparison module, the second end of the hysteresis control module and the output end of the bias current module, the drain electrode of the NMOS22 is respectively connected with the drain electrode of the PMOS13, the grid electrode of the NMOS23, the grid electrode of the MOS14 and the first end of the front-stage driving module, and the source electrode of the NMOS22 is respectively connected with the source electrode of the NMOS23 and the drain electrode of the NMOS 21; the drain electrode of the PMOS13 is respectively connected with the source electrode of the PMOS14 and the drain electrode of the PMOS 12; the source electrode of the PMOS12 and the drain electrode of the NMOS23 are respectively connected with a direct current power supply; the source of NMOS21 and the drain of PMOS14 are grounded, respectively.

One end of the front-stage driving module is connected with the second end of the comparing module and the second end of the hysteresis control module respectively, the other end of the front-stage driving module is connected with the first end of the rear-stage driving module, and the front-stage driving module can be understood as a shaping filter circuit, so that noise output by the comparator is effectively reduced, and accuracy of an output signal of the hysteresis comparator is improved.

The drain of PMOS13 is connected to the source of PMOS14 and the drain of PMOS12, respectively. The source of PMOS12 and the drain of NMOS23 are connected to dc power supply, respectively, and the source of NMOS21 and the drain of PMOS14 are grounded, respectively. After the input signal passes through the filter, it is first input to the gate of NMOS22 so that current flows through the drain-source of the pipe. After this current flows through the drain of PMOS13, it flows into the source of PMOS14, eventually returning to the dc power supply.

Specifically, the circuit module is different from the inverter in the prior art in that there are two threshold voltages, respectively called positive threshold voltage and negative threshold voltage, inside, so that when the input voltage is noisy, no change in the output voltage is caused. The structure is internally provided with positive feedback effect, and can convert a periodic signal with slow edge change into a rectangular pulse signal with steep edge. When the input voltage increases from low to high and reaches a positive threshold voltage, the output voltage is inverted, and when the input voltage changes from high to low and reaches a negative value voltage, the output voltage is inverted. By adjusting the aspect ratio of the six pipes, a satisfactory shaping and filtering effect can be obtained.

On the basis of the above embodiment, referring to fig. 10, fig. 10 shows a schematic circuit diagram of another hysteresis comparator according to an embodiment of the present application.

The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the present disclosure. That is, equivalent changes and modifications are contemplated by the teachings of this disclosure, which fall within the scope of the present disclosure. Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains.

Claims

1. A hysteresis comparator, comprising: the device comprises a bias current module, a hysteresis control module, a comparison module and a driving module, wherein:

2. The hysteresis comparator of claim 1, wherein the drive module is a pre-stage drive module, the bias current module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a second NMOS transistor, wherein:

3. The hysteresis comparator of claim 1, wherein the drive module is a pre-driver module, the first external interface comprises a first voltage input interface and a second voltage input interface, and the comparison module comprises a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a sixth NMOS transistor, wherein:

4. The hysteresis comparator according to claim 1, wherein the driving module is a front stage driving module, the hysteresis control module comprises at least two hysteresis control units, a hysteresis output unit, a constant current source unit and a feedback unit, wherein:

5. The hysteresis comparator according to claim 4, wherein the hysteresis control module includes a first hysteresis control unit, a second hysteresis control unit, a third hysteresis control unit, a fourth hysteresis control unit, the hysteresis output unit, the constant current source unit, and the feedback unit, the second external interface includes a first signal input interface, a second signal input interface, a third signal input interface, and a fourth signal input interface, the first hysteresis control unit includes a thirteenth NMOS tube, a fourteenth NMOS tube, a first resistor, and a second resistor, the second hysteresis control unit includes a twelfth NMOS tube, a fifteenth NMOS tube, a third resistor, and a fourth resistor, the third hysteresis control unit includes an eleventh NMOS tube, a sixteenth NMOS tube, a fifth resistor, and a sixth resistor, the fourth hysteresis control unit includes a tenth NMOS tube, a seventeenth NMOS tube, a seventh resistor, and an eighth resistor, the hysteresis output unit is a seventh NMOS tube, the constant current source unit is a fifth NMOS tube, and the feedback unit includes a PMOS, an eighth NMOS tube, and an eighth NMOS tube, wherein:

6. The hysteresis comparator of claim 1, wherein the drive module is a post drive module comprising a tenth PMOS transistor and a ninth NMOS transistor, a fifteenth PMOS transistor and a twenty-fourth NMOS transistor, wherein:

7. The hysteresis comparator of claim 1, further comprising: a reference current module, wherein:

8. The hysteresis comparator of claim 7, wherein the reference current module comprises: eighteenth NMOS pipe, nineteenth NMOS pipe, twentieth NMOS pipe, eleventh PMOS pipe and ninth resistance, wherein:

9. The hysteresis comparator of claim 1, wherein the drive module is a pre-drive module, wherein:

one end of the front-stage driving module is connected with the second end of the comparison module and the second end of the hysteresis control module respectively, the other end of the front-stage driving module is connected with the first end of the rear-stage driving module, and the front-stage driving module is used for filtering noise interference in the voltage signal.

10. The hysteresis comparator of claim 9, wherein the pre-driver module comprises: twelfth PMOS pipe, thirteenth PMOS pipe, fourteenth PMOS pipe, twenty-first NMOS pipe, twenty-second NMOS pipe and twenty-third NMOS pipe, wherein:

the grid electrode of the twenty-second NMOS tube is respectively connected with the grid electrode of the twelfth PMOS tube, the grid electrode of the thirteenth PMOS tube, the grid electrode of the twenty-first NMOS tube, the second end of the comparison module, the second end of the hysteresis control module and the output end of the bias current module, the drain electrode of the twenty-second NMOS tube is respectively connected with the drain electrode of the thirteenth PMOS tube, the grid electrode of the twenty-third NMOS tube, the grid electrode of the fourteenth PMOS tube and the first end of the rear driving module, and the source electrode of the twenty-second NMOS tube is respectively connected with the source electrode of the twenty-third NMOS tube and the drain electrode of the twenty-first NMOS tube;