CN109813952A - A kind of envelope detected circuit - Google Patents
A kind of envelope detected circuit Download PDFInfo
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- CN109813952A CN109813952A CN201811519984.9A CN201811519984A CN109813952A CN 109813952 A CN109813952 A CN 109813952A CN 201811519984 A CN201811519984 A CN 201811519984A CN 109813952 A CN109813952 A CN 109813952A
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Abstract
The present invention relates to a kind of envelope detected circuits, including bandgap voltage reference, for providing bandgap voltage reference signal；Bleeder circuit, for generating envelope threshold signal according to bandgap voltage reference signal；Comparator for comparing the voltage magnitude of high-speed differential signal and the voltage threshold of envelope threshold signal, and exports high level or low level signal；Shaping circuit, high level or low level signal for exporting to comparator carry out shaping, and export envelope detected signal.The present invention can be used in monitoring the quality of high-speed differential signal transmission, when high-speed differential signal voltage magnitude is less than envelope voltage threshold value, then it is assumed that the high-speed differential signal received is abnormal, on the contrary then think that the high-speed differential signal received is normal.Circuit structure of the present invention is simple, and detected speed signal is very fast, has and is flexibly widely applied.
Description
Technical field
The present invention relates to the high speed signals in microelectric technique to receive and dispatch field, especially a kind of envelope of high-speed differential signal
Detection circuit.
Background technique
High speed signal transmitting-receiving plays vital role in extensive numerical model analysis SOC (system level chip).With
The continuous development of integrated circuit technique and technological level, transistor and device size on chip become small, chip
Integrated level is higher and higher, and the speed of interface is also higher and higher, and the voltage magnitude of signal transmission is also smaller and smaller, so that high on chip
The design difficulty of fast signal transmitting and receiving circuit is greatly improved with complexity.
During high-speed differential signal transmitting-receiving, usual signal needs to meet eye diagram requirements, to ensure that signal can be just
Often it is received.When signal is interfered or circuit abnormal connection occurs, signal is unsatisfactory for eye diagram requirements, it may be possible to voltage amplitude
It is worth too small, receiving end is still possible to receive signal at this time, and carries out data recovery to the signal received, but restored
There are the biggish bit error rates for data.
In order to solve problem above, it may require that an envelope detected circuit in part of interface (such as USB 2.0), for detecting
The voltage magnitude size of high-speed differential signal.When the high-speed differential signal received is second-rate, envelope detected circuit
It detects the generation of abnormal conditions and reports that receiving end must ignore received data at this time to receiving end.Traditional packet
Structure is complicated for network detection circuit, and speed is slower, it is difficult to meet higher and higher request signal transmission.
Summary of the invention
For overcome the deficiencies in the prior art, the object of the present invention is to provide a kind of envelope detected of high-speed differential signal electricity
Road, for detecting whether the high-speed differential signal voltage magnitude received meets concrete specification requirement.
The technical solution adopted by the present invention to solve the technical problems is:
A kind of envelope detected circuit, including bandgap voltage reference, the bandgap voltage reference is for providing band gap base
Quasi- voltage signal；Bleeder circuit, the bleeder circuit are connect with bandgap voltage reference, for according to bandgap voltage reference signal
Generate envelope threshold signal；Comparator, the comparator include two input terminals, and first input end is connect with bleeder circuit, the
Two input terminals are connect with high-speed differential signal input terminal, and the comparator is used to compare the voltage magnitude and packet of high-speed differential signal
The voltage threshold of network threshold signal, and export high level or low level signal；Shaping circuit, the input terminal of the shaping circuit with
The output end of comparator connects, and the high level or low level signal for exporting to comparator carry out shaping, and exports envelope inspection
Survey signal.
Further, the first input end of the comparator includes input terminal vrefp and input terminal vrefn, the partial pressure electricity
Road includes fixed resistance R1 and variable resistance R2, one end of fixed resistance R1 respectively with bandgap voltage reference and input terminal
Vrefp connection, the other end of fixed resistance R1 are connect with one end of variable resistance R2 and input terminal vrefn respectively, variable resistance
The other end of R2 is grounded.
Further, the comparator includes current source I1, PMOS tube M1, M2, M3, M4, NMOS tube M5, M6, the grid of M1
It is connect with the anode of drain electrode, the grid of M2 and current source I1；The source electrode of the drain electrode of M2, the source electrode of M3 and M4 is connected；M3
Grid be comparator input terminal vrefp, and the grid of M4 is then the input terminal vrefn of comparator；The drain electrode of M3 and
The drain and gate of M5 is connected；The drain electrode of M4, the drain electrode of M6 are connected with grid；The cathode of current source I1, the source electrode of M5, M6
Source electrode be all connected to ground；The source electrode of M1, the source electrode of M2 are all connected to power supply.
Further, the second input terminal of the comparator includes input terminal vip and input terminal vin, and the comparator includes
PMOS tube M7, M8, M9, NMOS tube M10, M11, the anode connection of the grid and current source I1 of M7；The drain electrode of M6 and grid phase
Connection；The source electrode of the drain electrode of M7, the source electrode of M8 and M9 is connected；The grid of M8 is the input terminal vip of comparator, and the grid of M9
Pole is the input terminal vin of comparator；The drain electrode of M8, the grid of M10 are connected with drain electrode；The drain electrode of M9, the grid of M11 and leakage
Pole is connected；The source electrode of M10, the source electrode of M11 are all connected to ground；The source electrode of M7 is connected to power supply.
Further, the output end of the comparator includes output end vop and output end von, and the comparator includes PMOS
Pipe M14, M15, M18 and M19, NMOS tube include M12, M13, M16 and M17, and the grid of M13 and the grid of M17 are connected
It connects；The drain electrode of M8, the grid of M10 are connected with the grid of drain electrode and M16；The drain electrode of M9, the grid of M11 and drain electrode and
The grid of M12 is connected；The drain electrode of M12, the grid of M14 are connected with the grid of drain electrode and M15；The drain electrode of M15 is with M13's
Drain electrode is connected, and constitutes the output end von of comparator；The drain electrode of M16, the grid of M18 are connected with the grid of drain electrode and M19
It connects；The drain electrode of M19 is connected with the drain electrode of M17, constitutes the output end vop of comparator；The source electrode of M12, the source electrode of M13, M16
Source electrode and the source electrode of M17 be all connected to ground；The source electrode of M14, the source electrode of M15, the source electrode of M18 and M19 source electrode connect
It is connected to power supply.
Further, the input terminal of the shaping circuit includes input terminal vip and input terminal vin, output end vop and input terminal
Vip connection, output end von are connect with input terminal vin, and the output end of shaping circuit includes output end vo, and output end vo is used as packet
The output end of network detection signal.
Further, the shaping circuit includes current source I2, phase inverter INV11, INV2, PMOS tube M4, NMOS tube M1,
M2, M3, the cathode of current source I2, the grid of M1 are connected with the grid of drain electrode, the grid of M2, M3；The leakage of the source electrode and M3 of M2
Pole is connected；The input terminal of the drain electrode of M4, the drain electrode of M2 and INV2 is connected；The grid of M4 and the output end of INV1 are connected
It connects；The input terminal of INV1 is the input terminal vip of shaping circuit.
Further, the shaping circuit includes phase inverter INV3, INV4, PMOS tube M5, NMOS tube M6, M7, current source I2
Cathode, the grid of M6 and the grid of M7 be connected；The source electrode of M6 is connected with the drain electrode of M7；The drain electrode of M5, the drain electrode of M6
And the input terminal of INV4 is connected；The grid of M5 and the output end of INV3 are connected；The input terminal of INV3 is shaping electricity
The input terminal vin on road.
Further, the shaping circuit includes that two output ends of NAND gate NAND1, INV2 and INV4 are connected respectively to
Two input terminals of NAND gate NAND2；The output end of NAND gate NAND2 is the output end vo of shaping circuit.
The beneficial effects of the present invention are: the present invention can be used in monitoring the quality of high-speed differential signal transmission, when high speed difference
Sub-signal voltage magnitude is less than envelope voltage threshold value, then it is assumed that the high-speed differential signal received is abnormal, on the contrary then think to connect
The high-speed differential signal received is normal.Circuit structure of the present invention is simple, and detected speed signal is very fast, has and flexibly widely answers
With.
Detailed description of the invention
Further description of the specific embodiments of the present invention with reference to the accompanying drawing:
Fig. 1 is the working principle block diagram of present pre-ferred embodiments；
Fig. 2 is the circuit diagram of the comparator of present pre-ferred embodiments；
Fig. 3 is the circuit diagram of the shaping circuit of present pre-ferred embodiments.
Specific embodiment
In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is implemented below in conjunction with attached drawing
Technical solution in example is clearly and completely described, it is clear that described embodiment is only the implementation of present invention a part
Example, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creativeness
The every other embodiment obtained under the premise of labour, should fall within the scope of the present invention.
Referring to Fig.1, a kind of envelope detected circuit of the present embodiment, including bandgap voltage reference 1, the band-gap reference electricity
Potential source 1 is for providing bandgap voltage reference signal；Bleeder circuit 2, the bleeder circuit 2 are connect with bandgap voltage reference 1, are used
According to bandgap voltage reference signal generation envelope threshold signal；Comparator 3, the comparator 3 include two input terminals, first
Input terminal is connect with bleeder circuit 2, and the second input terminal is connect with high-speed differential signal input terminal, and the comparator 3 is for comparing
The voltage magnitude of high-speed differential signal and the voltage threshold of envelope threshold signal, and export high level or low level signal；Shaping
The input terminal of circuit 4, the shaping circuit 4 is connect with the output end of comparator 3, high level for being exported to comparator 3 or
Low level signal carries out shaping, and exports envelope detected signal.
The first input end of the comparator 3 includes input terminal vrefp and input terminal vrefn, and the bleeder circuit 2 includes
Fixed resistance R1 and variable resistance R2, one end of fixed resistance R1 connect with bandgap voltage reference 1 and input terminal vrefp respectively
It connects, the other end of fixed resistance R1 is connect with one end of variable resistance R2 and input terminal vrefn respectively, and variable resistance R2's is another
End ground connection.When circuit works normally, the voltage on variable resistance R2 controls the voltage threshold size of envelope threshold signal, increases
The resistance value of big variable resistance R2 can be improved the voltage threshold of envelope threshold signal, on the contrary then can reduce.
Second input terminal of the comparator 3 includes input terminal vip and input terminal vin, input terminal vip and input terminal vin
As high-speed differential signal input terminal.The output end of the comparator 3 includes output end vop and output end von, shaping circuit 4
Input terminal include input terminal vip and input terminal vin, output end vop is connect with input terminal vip, output end von and input terminal
Vin connection, the output end of shaping circuit 4 include output end vo, and output end vo is used as the output end of envelope detected signal.
Referring to Fig. 2, the comparator 3 includes current source I1, several PMOS tube and several NMOS tubes.PMOS tube packet
M1, M2, M3, M4, M7, M8, M9, M14, M15, M18 and M19 are included, NMOS tube includes M5, M6, M10, M11, M12, M13, M16
And M17.Its connection relationship is as follows: the anode company of the grid of M1 and drain electrode, the grid of M2, the grid of M7 and current source I1
It connects；The source electrode of the drain electrode of M2, the source electrode of M3 and M4 is connected；The grid of M3 is the input terminal vrefp of comparator 3, and M4
Grid be then comparator 3 input terminal vrefn；The drain electrode of M3 and the drain and gate of M5 are connected；The drain electrode of M4, M6
Drain electrode is connected with the grid of grid, the grid of M13 and M17；The source electrode of the drain electrode of M7, the source electrode of M8 and M9 is connected；
The grid of M8 is the input terminal vip of comparator 3, and the grid of M9 is the input terminal vin of comparator 3；The drain electrode of M8, M10
Grid is connected with the grid of drain electrode and M16；The drain electrode of M9, the grid of M11 are connected with the grid of drain electrode and M12；M12
Drain electrode, M14 grid be connected with the grid of drain electrode and M15；The drain electrode of M15 is connected with the drain electrode of M13, constitutes ratio
Compared with the output end von of device 3；The drain electrode of M16, the grid of M18 are connected with the grid of drain electrode and M19；The drain electrode of M19 and M17
Drain electrode be connected, constitute the output end vop of comparator 3；The cathode of current source I1, the source electrode of M5, the source electrode of M6, M10
Source electrode, the source electrode of M11, the source electrode of M12, the source electrode of M13, the source electrode of M16 and M17 source electrode be all connected to ground；The source electrode of M1,
The source electrode of M2, the source electrode of M7, the source electrode of M14, the source electrode of M15, the source electrode of M18 and M19 source electrode be all connected to power supply.
Referring to Fig. 3, the shaping circuit 4 include current source I2, several phase inverters, several PMOS tube, several
NMOS tube and NAND gate NAND1.Phase inverter includes INV11, INV2, INV3 and INV4, and PMOS tube includes M4 and M5,
NMOS tube includes M1, M2, M3, M6 and M7.Its connection relationship is as follows: the cathode of current source I2, the grid of M1 and drain electrode, M2
Grid, the grid of M3, the grid of M6 and M7 grid be connected；The source electrode of M2 is connected with the drain electrode of M3；The drain electrode of M4, M2
Drain electrode and the input terminal of INV2 be connected；The grid of M4 and the output end of INV1 are connected；The input terminal of INV1 is
The input terminal vip of shaping circuit 4；The source electrode of M6 is connected with the drain electrode of M7；The drain electrode of M5, the drain electrode of M6 and the input of INV4
End is connected；The grid of M5 and the output end of INV3 are connected；The input terminal of INV3 is the input terminal vin of shaping circuit 4；
Two output ends of INV2 and INV4 are connected respectively to two input terminals of NAND gate NAND2；The output end of NAND gate NAND2
The as output end vo of shaping circuit 4.
When the voltage magnitude of high-speed differential signal is higher than the voltage threshold of envelope threshold signal, due to high-speed differential signal
It may be 0 or 1, such as sending is 1, then an input terminal vip envelope voltage threshold value higher than input terminal vin in certain section of moment；Instead
It, an input terminal vin envelope voltage threshold value higher than input terminal vip in certain section of moment.When input terminal vip is higher than input terminal vin
When one envelope voltage threshold value, the output end vop of comparator 3 is 1；When an input terminal vip envelope voltage lower than input terminal vin
When threshold value, the output end von of comparator is 1, and therefore, two signals that comparator 3 exports are according to the voltage of high-speed differential signal
Amplitude variation is alternately 1；Since the voltage magnitude of high-speed differential signal changes, the signal 1 that comparator 3 exports is not always weight
It is folded, when the voltage of two high-speed differential signal input terminals is close, while two output ends are possible to occur of short duration for 0 feelings
Condition, it is therefore necessary to the burr generated during high-speed differential signal jump is removed using shaping circuit 4, shaping circuit 4 is by prolonging
Long 3 output end von of comparator and output end vop remains for 1 time, guarantees that time long enough allows the two to be overlapped, steady to realize
Fixed filter action makes output instruction stabilize to 1.When high-speed differential signal voltage magnitude than envelope threshold signal voltage threshold
When being worth low, two signals that comparator 3 exports can always remain as 0.When output is designated as 1, high speed voltage difference is indicated
Sub-signal transmission quality is preferable；When output is designated as 0, indicate that high speed voltage differential signal transmission quality is bad, the bit error rate can
It can increase.
The partial pressure coefficient that variable resistance R2 of the invention realizes bleeder circuit 2 is adjustable, can adjust according to specific needs
The size of envelope voltage threshold value, and it is unrelated with the variation of voltage with temperature, technique.
In conclusion the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although referring to before
Stating embodiment, invention is explained in detail, those skilled in the art should understand that；It still can be to preceding
It states technical solution documented by each embodiment to modify, or is equivalently replaced to being wherein no lack of technical characteristic, and these
It modifies or replaces, the spirit and scope for technical solution of the embodiment of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (9)
1. a kind of envelope detected circuit, it is characterised in that: including
Bandgap voltage reference (1), the bandgap voltage reference (1) is for providing bandgap voltage reference signal；Bleeder circuit
(2), the bleeder circuit (2) connect with bandgap voltage reference (1), for generating envelope threshold according to bandgap voltage reference signal
Value signal；
Comparator (3), the comparator (3) include two input terminals, and first input end is connect with bleeder circuit (2), and second is defeated
Enter end to connect with high-speed differential signal input terminal, the comparator (3) is used to compare the voltage magnitude and packet of high-speed differential signal
The voltage threshold of network threshold signal, and export high level or low level signal；
The input terminal of shaping circuit (4), the shaping circuit (4) is connect with the output end of comparator (3), for comparator
(3) high level or low level signal exported carries out shaping, and exports envelope detected signal.
2. envelope detected circuit according to claim 1, it is characterised in that: the first input end packet of the comparator (3)
Input terminal vrefp and input terminal vrefn are included, the bleeder circuit (2) includes fixed resistance R1 and variable resistance R2, fixed resistance
One end of R1 is connect with bandgap voltage reference (1) and input terminal vrefp respectively, the other end of fixed resistance R1 respectively with it is variable
One end of resistance R2 is connected with input terminal vrefn, the other end ground connection of variable resistance R2.
3. envelope detected circuit according to claim 2, it is characterised in that: the comparator (3) includes current source I1,
The grid of PMOS tube M1, M2, M3, M4, NMOS tube M5, M6, M1 are connect with the anode of drain electrode, the grid of M2 and current source I1；
The source electrode of the drain electrode of M2, the source electrode of M3 and M4 is connected；The grid of M3 is the input terminal vrefp of comparator (3), and M4
Grid is then the input terminal vrefn of comparator (3)；The drain electrode of M3 and the drain and gate of M5 are connected；
The drain electrode of M4, the drain electrode of M6 are connected with grid；The cathode of current source I1, the source electrode of M5, M6 source electrode be all connected to ground；
The source electrode of M1, the source electrode of M2 are all connected to power supply.
4. envelope detected circuit according to claim 3, it is characterised in that: the second input terminal packet of the comparator (3)
Input terminal vip and input terminal vin are included, the comparator (3) includes PMOS tube M7, M8, M9, NMOS tube M10, M11, the grid of M7
And the anode connection of current source I1；The drain electrode of M6 is connected with grid；The source electrode of the drain electrode of M7, the source electrode of M8 and M9 is connected
It connects；The grid of M8 is the input terminal vip of comparator (3), and the grid of M9 is the input terminal vin of comparator (3)；The leakage of M8
Pole, M10 grid be connected with drain electrode；The drain electrode of M9, the grid of M11 are connected with drain electrode；Source electrode, the source electrode of M11 of M10 is equal
It is connected to ground；The source electrode of M7 is connected to power supply.
5. envelope detected circuit according to claim 4, it is characterised in that: the output end of the comparator (3) includes defeated
Outlet vop and output end von, the comparator (3) include PMOS tube M14, M15, M18 and M19, NMOS tube include M12,
M13, M16 and M17, the grid of M13 and the grid of M17 are connected；The drain electrode of M8, the grid of M10 and drain electrode and M16's
Grid is connected；The drain electrode of M9, the grid of M11 are connected with the grid of drain electrode and M12；The drain electrode of M12, M14 grid with
The grid of drain electrode and M15 are connected；The drain electrode of M15 is connected with the drain electrode of M13, constitutes the output end of comparator (3)
von；The drain electrode of M16, the grid of M18 are connected with the grid of drain electrode and M19；The drain electrode of M19 is connected with the drain electrode of M17,
Constitute the output end vop of comparator (3)；The source electrode of M12, the source electrode of M13, the source electrode of M16 and M17 source electrode be all connected to
Ground；The source electrode of M14, the source electrode of M15, the source electrode of M18 and M19 source electrode be all connected to power supply.
6. envelope detected circuit according to claim 5, it is characterised in that: the input terminal of the shaping circuit (4) includes
Input terminal vip and input terminal vin, output end vop are connect with input terminal vip, and output end von is connect with input terminal vin, shaping electricity
The output end on road (4) includes output end vo, and output end vo is used as the output end of envelope detected signal.
7. envelope detected circuit according to claim 6, it is characterised in that: the shaping circuit (4) includes current source I2,
Phase inverter INV11, INV2, PMOS tube M4, NMOS tube M1, M2, M3, the grid of the cathode of current source I2, the grid of M1 and drain electrode, M2
Pole, M3 grid be connected；The source electrode of M2 is connected with the drain electrode of M3；The input terminal of the drain electrode of M4, the drain electrode of M2 and INV2
It is connected；The grid of M4 and the output end of INV1 are connected；The input terminal of INV1 is the input terminal vip of shaping circuit (4).
8. envelope detected circuit according to claim 7, it is characterised in that: the shaping circuit (4) includes phase inverter
The grid of INV3, INV4, PMOS tube M5, NMOS tube M6, M7, the cathode of current source I2, the grid of M6 and M7 are connected；M6's
Source electrode is connected with the drain electrode of M7；The input terminal of the drain electrode of M5, the drain electrode of M6 and INV4 is connected；The grid and INV3 of M5
Output end be connected；The input terminal of INV3 is the input terminal vin of shaping circuit (4).
9. envelope detected circuit according to claim 8, it is characterised in that: the shaping circuit (4) includes NAND gate
Two output ends of NAND1, INV2 and INV4 are connected respectively to two input terminals of NAND gate NAND2；NAND gate NAND2's
Output end is the output end vo of shaping circuit (4).
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| CN201811519984.9A CN109813952A (en) | 2018-12-12 | 2018-12-12 | A kind of envelope detected circuit |
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| CN201811519984.9A CN109813952A (en) | 2018-12-12 | 2018-12-12 | A kind of envelope detected circuit |
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| CN110912842A (en) * | 2019-11-13 | 2020-03-24 | 珠海市一微半导体有限公司 | Envelope detection circuit |
| CN111208347A (en) * | 2020-03-16 | 2020-05-29 | 成都纳能微电子有限公司 | High-speed differential signal amplitude detection circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110912842A (en) * | 2019-11-13 | 2020-03-24 | 珠海市一微半导体有限公司 | Envelope detection circuit |
| CN110912842B (en) * | 2019-11-13 | 2023-09-05 | 珠海一微半导体股份有限公司 | Envelope detection circuit |
| CN111208347A (en) * | 2020-03-16 | 2020-05-29 | 成都纳能微电子有限公司 | High-speed differential signal amplitude detection circuit |
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Application publication date: 20190528 |