CN213091822U - Test communication circuit capable of improving resource utilization rate of automatic tester - Google Patents
Test communication circuit capable of improving resource utilization rate of automatic tester Download PDFInfo
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- CN213091822U CN213091822U CN202022243813.7U CN202022243813U CN213091822U CN 213091822 U CN213091822 U CN 213091822U CN 202022243813 U CN202022243813 U CN 202022243813U CN 213091822 U CN213091822 U CN 213091822U
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Abstract
The utility model discloses a can improve automatic test machine resource utilization's test communication circuit, this circuit are equipped with the automatic test machine who is connected and communicates with the probe station, automatic test machine is equipped with a plurality of test channels, each test channel of automatic test machine is connected with a single channel test result processing circuit respectively, two liang of output signal mergers to binary channels test result processing circuit of two adjacent single channel test result processing circuits, two liang of mergers of output signal of two adjacent binary channels test result processing circuit again, merge to total passageway test result processing circuit until the output signal with all passageways, total passageway test result processing circuit is connected and communicates with the probe station. The utility model discloses can improve the parallel efficiency of software testing machine's in the middle and low end automatic test machine under the condition that does not increase cost, have simple structure, efficiency of software testing is high, and test signal stability is high, characteristics such as interference immunity is strong.
Description
Technical Field
The utility model relates to an automatic test field of chip, in particular to simple structure, with low costs and efficiency of software testing is high can improve automatic testing machine resource utilization's test communication circuit.
Background
The chip is an important component of electronic equipment such as computers, and inevitably has some defects in the production process due to the fine structure and the complex manufacturing process. In order to ensure the quality of the chip, the chip needs to be tested to screen out good products. At present, the chips are usually tested by an automatic testing machine, and the chips are screened according to the test result. However, the existing middle and low-end automatic tester only supports single-channel test or dual-channel test, which causes resource waste of the automatic tester and the probe station. The high-end automatic tester can support multi-channel testing, but has the defect of high cost. Therefore, if the middle and low-end automatic tester can realize the multi-channel test function, the resource utilization rate of the automatic tester and the probe station can be improved, so that the test efficiency is improved, and the cost can be reduced.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a simple structure, with low costs, be applicable to the test communication circuit that can improve automatic test machine resource utilization of middle and low end automatic test equipment.
In order to solve the problem, the utility model provides a can improve automatic test machine resource utilization's test communication circuit, this circuit are equipped with the automatic test machine of being connected and communicating with the probe station, automatic test machine is equipped with a plurality of test channel, each test channel of automatic test machine is connected with a single channel test result processing circuit respectively, two liang of output signals of two adjacent single channel test result processing circuits merge to binary channels test result processing circuit, and two liang of mergers of output signals of two adjacent binary channels test result processing circuit again are until merging the output signal of all passageways to total channel test result processing circuit, total channel test result processing circuit is connected and is communicated with the probe station.
The automatic testing machine is provided with eight testing channels.
The structure of each single-channel test result processing circuit is the same, the first single-channel test result processing circuit comprises a first relay K1, a first chip U1, a first resistor R1, a second resistor R2 and a first capacitor C1, the positive pole of the coil of the first relay K1 is connected with a power supply, the negative pole of the coil is connected with the corresponding channel test signal output of the automatic test machine, the normally closed contact of the coil is grounded, the normally open contact of the normally open contact is connected with the power supply through a first resistor R1, the common end of the normally open contact is connected with the anode of a first chip U1, the cathode and the emitter of the first chip U1 are grounded, the collector of the first chip U1 is respectively connected with one end of a second resistor R2 and one end of a first capacitor C1, the other end of the second resistor R2 is connected with the power supply, and the other end of the first capacitor.
Further, the power supply is a 5V power supply, and the first chip U1 is a photoelectric coupler.
Each two-channel test result processing circuit's structure is the same, first two-channel test result processing circuit includes fifth chip U5, an input pin of fifth chip U5 is connected with first single channel test result processing circuit's output, and its another input pin is connected with second single channel test result processing circuit's output, and its output pin is connected with next-level two-channel test result processing circuit.
Further, the fifth chip U5 is an or gate model 74LS 32.
The total channel test result processing circuit comprises a seventh chip U7, one input pin of the seventh chip U7 is connected with the output end of a first two-channel test result processing circuit of the previous stage, the other input pin of the seventh chip U7 is connected with the output end of a second two-channel test result processing circuit of the previous stage, and the output pin of the seventh chip U7 is connected with the probe station.
Further, the seventh chip U7 is an or gate of type 74LS 32.
The automatic tester sends bin signals for mapping the test results of the test channels to the probe station.
Further, the automatic testing machine generates bin signals for mapping the test results of the test channels according to the test results of the test channels and a mapping relation configured in advance.
The utility model has the advantages that: the utility model discloses a test communication circuit carries out two liang of mergers to a total channel test result processing circuit step by step through the test signal with a plurality of passageways to can improve the parallel efficiency of software testing machine's parallel test under the condition of not increasing cost, overcome traditional well low end automatic testing machine and supported the problem that parallel test channel number is few. The utility model is not only simple in structure, and efficiency of software testing is high. In addition, each single-channel test result processing circuit is isolated by a photoelectric coupler, and the two-channel test result processing circuits merge test signals through an OR gate, so that the test signals are high in stability and strong in anti-interference performance.
Drawings
Fig. 1 is a circuit diagram of the present invention.
Fig. 2 is a schematic block diagram of the present invention.
Detailed Description
The following examples are further to explain and supplement the present invention, and do not constitute any limitation to the present invention.
As shown in fig. 1 and fig. 2, the utility model discloses a test communication circuit capable of improving the resource utilization rate of automatic testing machine includes a plurality of single-channel test result processing circuits 10, a plurality of binary channels test result processing circuits 20, total channel test result processing circuit 30, automatic testing machine 40 and probe station 50. The test communication circuit is used for chip testing of the middle and low-end automatic testing machine.
As shown in fig. 1 and 2, the automatic testing machine 40 is a middle and low-end automatic testing machine, and is connected to and communicates with a probe station 50, wherein the probe station 50 is a probe station matched with the automatic testing machine 40. The automatic tester 40 is provided with N test channels, where N is greater than or equal to 2, but supports only single-channel testing. The automatic tester 40 in this embodiment is provided with eight test channels. Each test channel of the automatic tester 40 is used to test one chip, and send an output signal of the test result to each single-channel test result processing circuit 10. The automatic tester 40 generates a bin signal for mapping the test result of each test channel according to the test result of each test channel and a preset mapping relationship, and transmits the bin signal to the probe station 50.
As shown in fig. 1 and 2, the single-channel test result processing circuit 10 has an input terminal connected to a corresponding test channel of the automatic test machine 40, and an output terminal connected to a corresponding dual-channel test result processing circuit 20. Wherein, the structure of each single-channel test result processing circuit 10 is the same. The structure of the first single-channel test result processing circuit 10 is taken as an example in the present embodiment, and includes a first relay K1, a first chip U1, a first resistor R1, a second resistor R2, and a first capacitor C1. The coil anode of the first relay K1 is connected to the power supply, the coil cathode thereof is connected to the first channel test signal output of the automatic tester 40, the normally closed contact thereof is grounded, the normally open contact thereof is connected to the power supply through the first resistor R1, the common end thereof is connected to the anode of the first chip U1, the cathode and the emitter of the first chip U1 are grounded, the collector thereof is connected to one end of the second resistor R2 and one end of the first capacitor C1, the other end of the second resistor R35 2 is connected to the power supply, and the other end of the first capacitor C1 is grounded. The power supply in this embodiment is a 5V power supply, and the first chip U1 is a photocoupler.
As shown in fig. 1 and fig. 2, two adjacent single-channel test result processing circuits 10 are combined into a two-channel test result processing circuit 20. The input end of the dual-channel test result processing circuit 20 is connected with the corresponding single-channel test result processing circuit 10, and the output end thereof is connected with the next-stage dual-channel test result processing circuit. The structure of each dual-channel test result processing circuit 20 is the same, and in this embodiment, the structure of the first dual-channel test result processing circuit is taken as an example for description, and the first dual-channel test result processing circuit includes a fifth chip U5, in which one input pin of the fifth chip U5 is connected to the output end of the first single-channel test result processing circuit 10, the other input pin thereof is connected to the output end of the second single-channel test result processing circuit 10, and the output pin thereof is connected to the next dual-channel test result processing circuit. The fifth chip U5 in this embodiment is an or gate model 74LS 32.
As shown in fig. 1 and fig. 2, the two-channel test result processing circuits 20 are combined two by two step, and finally, the output signals of all the channels are combined to the total channel test result processing circuit 30. In this embodiment, the eight single-channel test result processing circuits 10 are combined into four two-channel test result processing circuits 20 by two, the four two-channel test result processing circuits 20 are combined into two-level two-channel test result processing circuits by two, and the two-level two-channel test result processing circuits are combined into one total channel test result processing circuit 30. The output terminal of the total channel test result processing circuit 30 is connected to the probe station 50, and includes a seventh chip U7, one input pin of the seventh chip U7 is connected to the output terminal of one of the two-channel test result processing circuits 20 of the previous stage, the other input pin thereof is connected to the output terminal of the other one of the two-channel test result processing circuits 20 of the previous stage, and the output pin thereof is connected to the probe station 50. The seventh chip U7 in this embodiment is an or gate model 74LS 32.
As shown in fig. 1, the working principle of the present invention is: after the probe station 50 gives the start test signal SOT, the automatic test machine 40 starts testing the chips of each channel, after the test is completed, the automatic test machine 40 sends the test signal of each channel to the corresponding single-channel test result processing circuit 10, taking the first test channel as an example, when the test completion signal EOT _1 output by the automatic test machine 40 is at a low level, the test signal is sent to the first single-channel test result processing circuit 10, at this moment, the coil of the first relay K1 is electrified, the common end is in short circuit with the normally open contact, the first chip U1 is conducted, the single-channel test result processing circuit 10 outputs a low level, and the chip tested by the channel is a good product. When the test completion signal EOT _1 output from the automatic test machine 40 is at a high level, the single-channel test result processing circuit outputs a high level, and the chip tested by the channel is a defective product. The testing procedure of other testing channels is the same as that of the first testing channel. After the single-channel test result processing circuit 10 finishes processing the test result of each chip, it sends the test signal to the dual-channel test result processing circuit 20, taking the first dual-channel test result processing circuit 20 as an example, when two input ends of the fifth chip U5, that is, the single-channel test result processing circuit 10 of the first channel outputs a low level, and the single-channel test result processing circuit 10 of the second channel also outputs a low level, the fifth chip U5 outputs a low level, which indicates that the chips tested by the first channel and the second channel are both good. On the contrary, if the fifth chip U5 outputs a high level, it indicates that at least one of the chips tested by the first channel and the second channel is defective. The other two-channel test result processing circuits process the same as the first two-channel test result processing circuit 20. Until all the dual-channel test result processing circuits 20 are processed and sent to the total channel test result processing circuit 30, when all the dual-channel test result processing circuits 20 output low levels, the EOT signal output by the total channel test result processing circuit 30 is low level, when at least one of the dual-channel test result processing circuits outputs high level, the EOT signal output by the total channel test result processing circuit 30 is high level, then the EOT signal is sent to the probe station 50 by the total channel test result processing circuit 30, the probe station 50 accurately classifies the quality of the chips tested by each test channel according to the EOT signal and bin signals sent by the automatic testing machine 40, and therefore parallel testing of the multi-channel chips is achieved.
Although the present invention has been described in connection with the above embodiments, the scope of the present invention is not limited thereto, and modifications, replacements, and the like to the above members are all within the scope of the claims of the present invention without departing from the concept of the present invention.
Claims (10)
1. A test communication circuit capable of improving the resource utilization rate of an automatic tester is characterized in that the circuit is provided with an automatic tester (40) connected with and communicating with a probe station (50), the automatic tester (40) is provided with a plurality of test channels, each test channel of the automatic tester (40) is respectively connected with a single-channel test result processing circuit (10), output signals of two adjacent single-channel test result processing circuits (10) are combined to a double-channel test result processing circuit (20) in pairs, output signals of two adjacent double-channel test result processing circuits (20) are combined in pairs until output signals of all channels are combined to a main channel test result processing circuit (30), and the main channel test result processing circuit (30) is connected with and communicates with the probe station (50).
2. The test communication circuit for improving the utilization of the resources of the automatic test machine according to claim 1, wherein the automatic test machine (40) is provided with eight test channels.
3. The test communication circuit capable of improving the resource utilization rate of the automatic test machine according to claim 2, wherein the single-channel test result processing circuits (10) have the same structure, the first single-channel test result processing circuit (10) comprises a first relay K1, a first chip U1, a first resistor R1, a second resistor R2 and a first capacitor C1, the positive coil of the first relay K1 is connected to the power supply, the negative coil thereof is connected to the corresponding channel test signal output of the automatic test machine (40), the normally closed contact thereof is grounded, the normally open contact thereof is connected to the power supply through a first resistor R1, the common terminal thereof is connected to the anode of the first chip U1, the cathode and emitter of the first chip U1 are grounded, the collector thereof is respectively connected to one terminal of a second resistor R2 and one terminal of a first capacitor C1, the other terminal of the second resistor R2 is connected to the power supply, the other end of the first capacitor C1 is grounded.
4. The test communication circuit capable of improving the resource utilization rate of the automatic tester as claimed in claim 3, wherein the power supply is a 5V power supply, and the first chip U1 is a photocoupler.
5. The test communication circuit capable of improving the utilization rate of the resources of the automatic test machine according to claim 2, wherein the two-channel test result processing circuits (20) have the same structure, the first two-channel test result processing circuit (20) comprises a fifth chip U5, one input pin of the fifth chip U5 is connected to the output terminal of the first single-channel test result processing circuit (10), the other input pin of the fifth chip U5 is connected to the output terminal of the second single-channel test result processing circuit (10), and the output pin of the fifth chip U5 is connected to the next two-channel test result processing circuit.
6. The test communication circuit capable of improving the utilization rate of the resources of the automatic test machine according to claim 5, wherein the fifth chip U5 is an OR gate with a model number of 74LS 32.
7. The test communication circuit for improving the utilization of resources of an automatic test machine according to claim 2, wherein the total channel test result processing circuit (30) comprises a seventh chip U7, one input pin of the seventh chip U7 is connected to the output terminal of the first dual-channel test result processing circuit (20) at the previous stage, the other input pin thereof is connected to the output terminal of the second dual-channel test result processing circuit (20) at the previous stage, and the output pin thereof is connected to the probe station (50).
8. The circuit of claim 7, wherein the seventh chip U7 is an OR gate of type 74LS 32.
9. The test communication circuit for improving the utilization of the resources of the automatic test machine according to claim 1, wherein the automatic test machine (40) sends bin signals for mapping the test results of each test channel to the probe station (50).
10. The testing communication circuit capable of improving the utilization rate of the resources of the automatic testing machine according to claim 9, wherein the automatic testing machine (40) generates bin signals for mapping the test results of each test channel according to the test results of each test channel and a preset mapping relationship.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022243813.7U CN213091822U (en) | 2020-10-10 | 2020-10-10 | Test communication circuit capable of improving resource utilization rate of automatic tester |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022243813.7U CN213091822U (en) | 2020-10-10 | 2020-10-10 | Test communication circuit capable of improving resource utilization rate of automatic tester |
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| CN213091822U true CN213091822U (en) | 2021-04-30 |
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| CN202022243813.7U Active CN213091822U (en) | 2020-10-10 | 2020-10-10 | Test communication circuit capable of improving resource utilization rate of automatic tester |
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