CN105225955A - The manufacture method, semiconductor device and preparation method thereof of fin and sti structure - Google Patents
The manufacture method, semiconductor device and preparation method thereof of fin and sti structure Download PDFInfo
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- CN105225955A CN105225955A CN201410280093.8A CN201410280093A CN105225955A CN 105225955 A CN105225955 A CN 105225955A CN 201410280093 A CN201410280093 A CN 201410280093A CN 105225955 A CN105225955 A CN 105225955A
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Abstract
This application discloses the manufacture method of a kind of fin and sti structure, semiconductor device and preparation method thereof.The manufacture method of this fin and sti structure comprises: provide substrate; Substrate forms groove, and forms the dielectric layer that flushes with substrate top surface of upper surface in a groove; And remove part dielectric layer along the downward dry etching of exposed surface of dielectric layer, the inwall exposing groove forms fin and sti structure.In said method, adopt dry etching to remove part dielectric layer, be conducive to the damage avoiding wet etching to groove inner wall.Meanwhile, again dielectric layer is etched, to impel etching gas along the exposed surface directed etching downwards of dielectric layer after forming dielectric layer that upper surface flushes with substrate top surface in a groove.On this basis, after the etching of same time, the dielectric layer surface evenness in the sti structure formed is higher.Under the comprehensive function of two aspect factors, be conducive to the defect reducing fin and grid in FinFET.
Description
Technical field
The application relates to field of semiconductor manufacture, in particular to the manufacture method, semiconductor device and preparation method thereof of a kind of fin and sti structure.
Background technology
Along with the development of semiconductor technology, continued scale-down on the basis of always following Moore's Law as characteristic size of metal oxide semiconductor transistor (MOSFET) of one of its development mark, is also improved constantly as the circuit level of the integrated circuit of element, performance and power consumption by semiconductor device.In order to improve the speed of semiconductor device further, propose the nonplanar structure MOSFET being different from traditional plane MOSFET in the last few years, and fin formula field effect transistor (FinFET) is a class important in these nonplanar structures MOSFET.
In the manufacturing process of FinFET, usually form fin and shallow trench isolation from (STI) structure according to following steps: on substrate, form patterned hard mask successively, form groove along pattern etching substrate in hard mask; In employing chemical deposition normal direction groove after filled media layer, carry out thermal anneal process (RTA); Then the dielectric layer carrying out being planarized in groove is concordant with hard mask; After removing hard mask, adopt dilute hydrofluoric acid (DHF) to excute a law and etch or SiCoNi dry etching removal part dielectric layer, groove inner wall is exposed, forms fin and the sti structure of FinFET.
In the manufacturing process of above-mentioned FinFET, during dielectric layer in etched recesses, after hard mask and oxide layer etching are removed, the upper surface of dielectric layer is higher than the upper surface of substrate, when now DHF or SiCoNi etching being carried out to the dielectric layer in groove, the etch rate of dielectric layer periphery is faster than the etch rate at center, and this just very easily causes the dielectric layer surface in final sti structure to occur lug boss.There is pointed defect in the grid that these lug bosses be formed on dielectric layer can make the later stage be formed, thus make in application process, to occur the defect such as electric leakage, instability.Particularly in the process adopting DHF wet etching, also can destroy groove inner wall, make the surface roughness of the final fin formed too high, thus affect the stability of the FinFET formed.
Summary of the invention
The application aims to provide the manufacture method, semiconductor device and preparation method thereof of a kind of fin and sti structure, easily occurs protruding problem to solve sti structure dielectric layer surface in prior art.
To achieve these goals, according to an aspect of the application, provide the manufacture method of a kind of fin and sti structure, it comprises the following steps: provide substrate; Substrate forms groove, and forms the dielectric layer that flushes with substrate top surface of upper surface in a groove; And remove part dielectric layer along the downward dry etching of exposed surface of dielectric layer, the inwall exposing groove forms fin and sti structure.
Further, above-mentioned dry etching adopts SiCoNi etching method.
Further, in the step of above-mentioned dry etching, etching temperature is 20 ~ 30 DEG C, and in etching gas, the velocity ratio of ammonia and Nitrogen trifluoride is 1 ~ 3:1.
Further, above-mentioned at substrate formation groove, and the step forming the dielectric layer that upper surface flushes with substrate top surface in a groove comprises: form patterned hard mask over the substrate; Along the downward etched substrate of figure in hard mask, form groove; The transition medium layer of upper surface and hard mask upper surface flush is formed in described groove; Remove hard mask; Planarization transition medium layer, forms the dielectric layer that upper surface flushes with substrate top surface.
Further, the step forming the transition medium layer of upper surface and hard mask upper surface flush in a groove comprises: form the surface covering hard mask, and the preparation dielectric layer of the inside of filling groove; Planarization preparation dielectric layer, forms the transition medium layer of upper surface and hard mask upper surface flush.
Further, after the step forming preparation dielectric layer, also comprise the step of preparation dielectric layer being carried out to quick thermal annealing process.
Further, before the step forming patterned hard mask, step substrate being formed oxide skin(coating) is also included in; Along in the step of the downward etched substrate of pattern in hard mask, etch the oxide skin(coating) be positioned on substrate simultaneously; In the step removing hard mask, remove oxide skin(coating) simultaneously.
Further, formed in the step of preparation dielectric layer, the method forming preparation dielectric layer is advanced processing procedure sedimentation or fluid chemistry vapour deposition process.
Further, remove in the step of hard mask, adopt wet etching method, preferably employing temperature is the phosphoric acid etching of 120 ~ 160 DEG C.
According to the another aspect of the application, provide a kind of manufacture method of semiconductor device, comprise the step forming fin and sti structure, wherein, the step forming fin and sti structure adopts above-mentioned manufacture method.
According to the another aspect of the application, provide a kind of semiconductor device, comprise fin and sti structure, wherein, fin and sti structure adopt above-mentioned manufacture method to be formed.。
The application fin of the application and the manufacture method, semiconductor device and preparation method thereof of sti structure, dry etching is adopted to remove part dielectric layer, be conducive to the damage avoiding wet etching to groove inner wall, thus be conducive to the surface roughness reducing the fin formed.Meanwhile, again dielectric layer is etched, to guarantee to etch the exposed surface downwards directed etching of gas along dielectric layer after forming dielectric layer that upper surface flushes with substrate top surface in a groove.Under this directed corrasion in the same direction, the central part of dielectric layer is identical with the etch rate of outer part.On this basis, after the etching of same time, the dielectric layer surface evenness in the sti structure formed is higher.Under the comprehensive function of two aspect factors, be conducive to the defect reducing fin and grid in final FinFET, thus reduce electric leakage when FinFET uses, unstable defect, make it have good serviceability.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the processing step schematic flow sheet of a kind of manufacture method according to fin and sti structure in the application's execution mode of the application;
Fig. 2 to Fig. 4 shows a kind of matrix cross-sectional view formed according to each step of manufacture method of fin and sti structure in the application's execution mode;
Fig. 2 shows the generalized section of provided substrate;
Fig. 3 shows and form groove on the substrate shown in Fig. 2, and in groove, form the cross-sectional view of the matrix after the upper surface dielectric layer concordant with substrate surface;
Fig. 3-1 shows the cross-sectional view of the matrix to form oxide layer and hard mask on the substrate shown in Fig. 2 after;
Fig. 3-2 shows the cross-sectional view of the matrix forming groove on the matrix shown in Fig. 3-1;
Fig. 3-3 shows the cross-sectional view of the matrix after the groove shown in coverage diagram 3-2 and substrate formation preparation dielectric layer;
Fig. 3-3-1 shows the preparation dielectric layer shown in planarization Fig. 3-3, forms the cross-sectional view of the matrix after the upper surface transition medium layer concordant with hard mask upper surface;
Fig. 3-4 shows the cross-sectional view of the matrix after the hard mask shown in removal Fig. 3-3 and oxide layer;
Fig. 4 shows the cross-sectional view along the matrix after the exposed surface downward dry etching removal part dielectric layer of the dielectric layer shown in Fig. 3.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
Introducing as background technology part, adopt the manufacture method of fin and sti structure in existing FinFET, easily there is projection in sti structure dielectric layer surface, thus FinFET can be made to occur electric leakage, unstable defect.In order to address this problem, the application applicant provides the manufacture method of a kind of fin and sti structure, and as shown in Figure 1, it comprises the following steps: provide substrate; Substrate forms groove, and forms the dielectric layer that flushes with substrate top surface of upper surface in a groove; And remove part dielectric layer along the downward dry etching of exposed surface of dielectric layer, the inwall exposing groove forms fin and sti structure.
In the manufacture method that the application is above-mentioned, adopt dry etching to remove part dielectric layer, be conducive to the damage avoiding wet etching to groove inner wall, thus be conducive to the surface roughness reducing the fin formed., by forming the dielectric layer that upper surface flushes with substrate top surface in a groove, this dielectric layer is being etched, to guarantee to etch the exposed surface downwards directed etching of gas along dielectric layer meanwhile.Under this directed corrasion in the same direction, the central part of dielectric layer is identical with the etch rate of outer part.On this basis, after the etching of same time, the dielectric layer surface evenness in the sti structure formed is higher.Under the comprehensive function of two aspect factors, be conducive to the defect reducing fin and grid in final FinFET, thus reduce electric leakage when FinFET uses, unstable defect, make it have good serviceability.
Illustrative embodiments according to the application will be described in more detail below.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
Fig. 2 to Fig. 4 shows the manufacture method of fin and the sti structure provided according to the application one embodiment, the matrix cross-sectional view obtained after each step.Below in conjunction with Fig. 2 to Fig. 4, further illustrate the manufacture method of fin that the application provides and sti structure.
First, substrate 100 is as shown in Figure 2 provided.Wherein, substrate 100 can be monocrystalline silicon, silicon-on-insulator (SOI) or germanium silicon (SiGe) etc.Exemplarily, in the present embodiment, substrate 100 selects single crystal silicon material to form.
After substrate 100 is provided, provided substrate 100 forms groove 110, and in groove 110, form the upper surface dielectric layer 120 concordant with substrate 100 upper surface, and then form basal body structure as shown in Figure 3.Form groove 110 and in groove 110, form the upper surface dielectric layer 120 concordant with substrate 100 upper surface and adopt those skilled in the art institute customary way.One more preferred embodiment in, it comprises the following steps:
First on substrate 100 as shown in Figure 2, form patterned hard mask 200.The formation method of this patterned hard mask 200 can be chemical vapour deposition technique, and hard mask material can be the hard mask materials well-known to those skilled in the art such as silicon nitride, silica, silicon oxynitride.Exemplarily, in the present embodiment, hard mask material selects silicon nitride.In a kind of preferred execution mode, before the step forming hard mask, first on the surface of substrate 100, form oxide skin(coating) 300, then on oxide skin(coating) 300, form hard mask, and then form basal body structure (following steps are all described to be formed with oxide skin(coating) 300) as shown in figure 3-1.Then, basal body structure as shown in figure 3-1 carries out graphical treatment to hard mask 200 ', and then form patterned hard mask 200.In addition, oxide skin(coating) 300 can play the effect of protection substrate 100 in follow-up groove formation process.
In the step of the patterned hard mask 200 of above-mentioned formation, a kind of preferred mode comprises: form hard mask on the substrate 100 and (preferably first form oxide skin(coating), form hard mask again), hard mask forms photoresist layer, in photoresist layer, opening is carried out in the corresponding position for forming groove 110, then etches hard mask 200 along Open Side Down and then forms patterned hard mask 200.
After forming the step of patterned hard mask 200, along the downward etched substrate 100 of figure in patterned hard mask 200, form groove 110, and then form basal body structure as shown in figure 3-2.In this step, can the degree of depth of the groove 110 that etching is formed be determined according to the height of required fin, such as 1800 ~ 3000? between.And etching technics can be dry etching, those skilled in the art can arrange the technological parameter of etching according to actual process demand.
After the step forming groove 110, in groove 110, form the transition medium layer 120 ' of upper surface and hard mask 200 upper surface flush, and then form the basal body structure as shown in Fig. 3-3.In a preferred embodiment, the step forming the transition medium layer 120 ' of upper surface and hard mask 200 upper surface flush comprises: first form the surface covering hard mask 200, and the preparation dielectric layer 120 of the inside of filling groove 110 ", carry out forming the basal body structure as shown in Fig. 3-3-1.Then planarization preparation dielectric layer 120 ", form the transition medium layer 120 ' of upper surface and hard mask 200 upper surface flush, and then the basal body structure of formation as shown in Fig. 3-3,
At above-mentioned formation preparation dielectric layer 120 " step in adopt conventional chemical vapor method.In a preferred embodiment, formed preparation dielectric layer 120 " method be advanced processing procedure sedimentation (HARP) or fluid chemistry vapour deposition process (FCVD).One more preferred embodiment in, forming preparation dielectric layer 120 " step after, also comprise preparation dielectric layer 120 " carry out the step of quick thermal annealing process, in order to increase preparation dielectric layer 120 " density.And prepare dielectric layer 120 " material can select the dielectric layer material of this area routine, exemplarily, select silica in present embodiment as preparation dielectric layer 120 " material.
After the step of transition medium layer 120 ' forming upper surface and hard mask 200 upper surface flush, remove hard mask 200 (or when there is oxide layer, remove hard mask 200 and oxide layer 300), and then the basal body structure formed as shown in Figure 3-4 is in above-mentioned steps, the method removing hard mask 200 (and oxide layer 300) adopts those skilled in the art institute customary way.One preferred embodiment in, adopt wet etching method, preferably adopt temperature to be the phosphoric acid etching of 120 ~ 160 DEG C.When the phosphoric acid of 120 ~ 160 DEG C etches hard mask and oxide skin(coating), there is higher etching selection ratio and etch rate faster.
After removing the step of hard mask 200, planarization transition medium layer 120 ', forms the dielectric layer 120 of upper surface and substrate 100 upper surface flush, and then forms basal body structure as shown in Figure 3.
In the step of the dielectric layer 120 that above-mentioned formation upper surface is concordant with substrate 100 upper surface, respectively to the preparation dielectric layer 120 higher than hard mask ", hard mask 200 and oxide skin(coating) 300, to remove higher than the transition medium layer 120 ' of substrate 100, be conducive to avoiding simultaneously to the problem higher because of different the caused planarized surface roughness of each layer hardness that hard mask 200, oxide skin(coating) 300 easily cause when carrying out planarization with the transition medium layer 120 ' higher than substrate 100.
After the step completing the dielectric layer 120 forming upper surface and substrate 100 upper surface flush in groove 110, the downward dry etching of exposed surface along dielectric layer 120 removes part dielectric layer 120, the inwall exposing groove 110 forms fin 130 and sti structure 140, and then forms basal body structure as shown in Figure 4.Those skilled in the art can according to the height of the height selective etching of required fin 130, as etching
compared to wet etching, the etching selection ratio of dry etching is relatively higher, and this is conducive to preventing the inwall of groove 110 (sidewall of fin 130) to be damaged because etching, thus is conducive to ensureing that it has lower roughness.Simultaneously, between the upper surface of dielectric layer 120 to be etched and the upper surface flush of substrate 100, when etching gas contact medium layer 120, etching gas can only etch along the table face-down orientation of dielectric layer 120, therefore all has identical etch rate to the longitudinal component of dielectric layer 120.This is just conducive to the dielectric layer surface improved in the sti structure 140 that formed and has higher smoothness.Formed in the process of grid in the later stage, this more level and smooth sti structure 140 dielectric layer surface is conducive to reducing the pointed defect in grid.More complete grid and lower fin 130 sidewall of roughness are all conducive to the electrical leakage problems reducing semiconductor device, improve its serviceability.
In the step of the downward dry etching of the above-mentioned exposed surface along dielectric layer 120, adopt those skilled in the art's customary way.One preferred embodiment in, adopt SiCoNi etching method.Compared to the method for other dry etchings, the etching surface that SiCoNi etching method is formed has lower roughness.Those skilled in the art select concrete technological parameter according to etched dielectric layer material.More preferably, during SiCoNi etching method etching, etching temperature is 20 ~ 30 DEG C, and in etching gas, ammonia (NH3) and Nitrogen trifluoride (NF3) velocity ratio are 1 ~ 3:1.
The application applicant additionally provides a kind of manufacture method of semiconductor device, comprises the step forming fin and sti structure, the manufacture method that the step wherein forming fin and sti structure adopts the application above-mentioned provided.The fin adopting above-mentioned method to be formed and sti structure, the roughness of fin sidewall is lower, and the surface roughness of sti structure dielectric layer is lower.And then make the fin in made semiconductor device and the defect in grid less, thus make made semiconductor device have lower electrical leakage quantity, higher serviceability.
The application applicant additionally provides a kind of semiconductor device, comprises fin and sti structure, and the manufacture method that wherein fin and sti structure adopt the application above-mentioned is formed.The electrical leakage quantity of this semiconductor device is lower, has higher serviceability.
As can be seen from the above description, the application's the above embodiments achieve following technique effect:
1, the fin made by method that the application is above-mentioned, the roughness of its sidewall is lower;
2, the sti structure made by side that the application is above-mentioned, the roughness of its dielectric layer surface is lower, thus makes to have less pointed defect in the grid of follow-up formation;
3, the semiconductor device made by method that the application is above-mentioned, its electrical leakage quantity is less, and serviceability is higher.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (11)
1. a manufacture method for fin and sti structure, is characterized in that, comprises the following steps:
Substrate is provided;
Form groove over the substrate, and in described groove, form the dielectric layer that upper surface flushes with described substrate top surface; And
The downward dry etching of exposed surface along described dielectric layer removes the described dielectric layer of part, and the inwall exposing described groove forms described fin and described sti structure.
2. manufacture method according to claim 1, is characterized in that, described dry etching adopts SiCoNi etching method.
3. manufacture method according to claim 2, is characterized in that, in the step of described dry etching, etching temperature is 20 ~ 30 DEG C, and in etching gas, the velocity ratio of ammonia and Nitrogen trifluoride is 1 ~ 3:1.
4. manufacture method according to any one of claim 1 to 3, is characterized in that, described at substrate formation groove, and the step forming the dielectric layer that upper surface flushes with described substrate top surface in a groove comprises:
Form patterned hard mask over the substrate;
Etch described substrate downwards along figure in described hard mask, form described groove;
The transition medium layer of upper surface and described hard mask upper surface flush is formed in described groove;
Remove described hard mask;
Transition medium layer described in planarization, forms the described dielectric layer that upper surface flushes with described substrate top surface.
5. manufacture method according to claim 4, is characterized in that, the step forming the transition medium layer of upper surface and described hard mask upper surface flush in described groove comprises:
Form the surface covering described hard mask, and fill the preparation dielectric layer of the inside of described groove;
Prepare dielectric layer described in planarization, form the described transition medium layer of upper surface and described hard mask upper surface flush.
6. manufacture method according to claim 5, is characterized in that, after the step forming described preparation dielectric layer, also comprises the step of described preparation dielectric layer being carried out to quick thermal annealing process.
7. manufacture method according to claim 5, is characterized in that,
Before the step forming patterned hard mask, also comprise the step forming oxide skin(coating) over the substrate;
Etch in the step of described substrate downwards along pattern in described hard mask, etch the described oxide skin(coating) be positioned on described substrate simultaneously;
In the step removing described hard mask, remove described oxide skin(coating) simultaneously.
8. manufacture method according to claim 5, is characterized in that, is formed in the step of described preparation dielectric layer, and the method forming described preparation dielectric layer is advanced processing procedure sedimentation or fluid chemistry vapour deposition process.
9. manufacture method according to claim 6, is characterized in that, removes in the step of described hard mask, adopts wet etching method, and preferably employing temperature is the phosphoric acid etching of 120 ~ 160 DEG C.
10. a manufacture method for semiconductor device, comprises the step forming fin and sti structure, it is characterized in that, the step of described formation fin and sti structure adopts the manufacture method according to any one of claim 1 to 8.
11. 1 kinds of semiconductor device, comprise fin and sti structure, it is characterized in that, described fin and described sti structure adopt the manufacture method according to any one of claim 1 to 8 to be formed.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110148552A (en) * | 2019-04-15 | 2019-08-20 | 上海华力集成电路制造有限公司 | The manufacturing method of level 0 interlayer film |
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| CN102054741A (en) * | 2009-10-27 | 2011-05-11 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit structure |
| CN102918635A (en) * | 2010-05-27 | 2013-02-06 | 应用材料公司 | Selective etch for silicon films |
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| US20100230757A1 (en) * | 2009-03-16 | 2010-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid STI Gap-Filling Approach |
| CN102054741A (en) * | 2009-10-27 | 2011-05-11 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit structure |
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