CN109037068A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109037068A CN109037068A CN201710429642.7A CN201710429642A CN109037068A CN 109037068 A CN109037068 A CN 109037068A CN 201710429642 A CN201710429642 A CN 201710429642A CN 109037068 A CN109037068 A CN 109037068A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 93
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 84
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 76
- 238000005530 etching Methods 0.000 claims abstract description 67
- 238000002955 isolation Methods 0.000 claims abstract description 56
- 238000005516 engineering process Methods 0.000 claims abstract description 52
- 238000001039 wet etching Methods 0.000 claims abstract description 51
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 230000003647 oxidation Effects 0.000 claims abstract description 30
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
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- 239000010410 layer Substances 0.000 claims description 181
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- 238000001312 dry etching Methods 0.000 claims description 5
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- 229910003978 SiClx Inorganic materials 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical group F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical group OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, method includes: offer substrate, and the substrate includes adjacent device region and isolated area, is formed with discrete fin on the substrate, wherein the spacing of the adjacent fin is equal；Silicon oxide layer is formed on fin side wall；Etching removes the partial oxidation silicon layer on the segment thickness fin and the fin side wall of the isolated area；Using residual silicon oxide layer as exposure mask, the remaining fin of the isolated area is etched using wet-etching technology, forms pseudo- fin；Isolation structure is formed over the substrate, and the top of the isolation structure is lower than the top of the device region fin, and covers the top of the pseudo- fin.The present invention can increase the etching technics window of removal isolated area fin, and the remaining fin of the isolated area is etched using wet-etching technology, so as to reduce the plasma damage to adjacent first regions fin.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
In technical field of manufacturing semiconductors, with the development trend of super large-scale integration, integrated circuit feature ruler
Very little lasting reduction.For the reduction of meeting market's demand size, the channel length of MOSFET field-effect tube is also corresponding constantly to be shortened.So
And with the shortening of device channel length, device source electrode between drain electrode at a distance from also shorten therewith, therefore control of the grid to channel
Ability processed is deteriorated therewith, and the difficulty of grid voltage pinch off (pinch off) channel is also increasing, so that sub-threshold leakage
(subthreshold leakage) phenomenon, i.e., so-called short-channel effect (SCE:short-channel effects) are more held
Easily occur.
Therefore, for the reduction of better meeting market's demand size, semiconductor technology gradually starts from planar MOSFET crystal
Pipe to more high effect three-dimensional transistor transient, such as fin field effect pipe (FinFET).In FinFET, grid
Ultra-thin body (fin) can at least be controlled from two sides, compare planar MOSFET devices, control ability of the grid to channel
It is stronger, it can be good at inhibiting short-channel effect；And FinFET has relative to other devices with existing IC manufacturing
Preferably compatibility.
But the electric property of prior art semiconductor structure is to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, improves the electricity of semiconductor structure
Performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, it is described
Substrate includes adjacent device region and isolated area, is formed with discrete fin on the substrate, wherein between the adjacent fin
Away from equal；Silicon oxide layer is formed on the side wall of the fin；Etching removes the segment thickness fin of the isolated area and described
Partial oxidation silicon layer on fin side wall；Using residual silicon oxide layer as exposure mask, the isolated area is etched using wet-etching technology
Remaining fin, form pseudo- fin；Isolation structure is formed over the substrate, and the top of the isolation structure is lower than the device
The top of area's fin, and cover the top of the pseudo- fin.
Correspondingly, being formed by semiconductor structure using above-mentioned forming method the present invention also provides a kind of.
Compared with prior art, technical solution of the present invention has the advantage that
After forming silicon oxide layer on the side wall of fin, the segment thickness fin of etching removal isolated area and the fin side
Partial oxidation silicon layer on wall, then using residual silicon oxide layer as exposure mask, the surplus of the isolated area is etched using wet-etching technology
Remaining fin forms pseudo- fin.On the one hand, the part on the segment thickness fin and the fin side wall for etching the isolated area
In the step of silicon oxide layer, by rationally controlling the etch amount of the etching technics, and in the silicon oxide layer to the device
Under the protective effect of area's fin, while removing the isolated area segment thickness fin, reduce to the adjacent device region fin
Plasma damage caused by portion；On the other hand, the remaining fin of the isolated area is etched by using wet-etching technology
Scheme can be avoided the device region fin by plasma during continuing to etch the remaining fin of the isolated area
Bulk damage, and can be using the remaining silicon oxide layer as etch mask.Therefore, not formed silicon oxide layer and a step dry method are compared
The scheme of the isolated area fin is etched, the present invention can increase the etching technics window for etching the isolated area fin
(Process Window) reduces that is, while improving the removal effect of the isolated area fin to adjacent devices area fin
Caused by plasma damage, so as to improve the electric property of formed semiconductor structure.
In optinal plan, the partial oxidation silicon layer on the segment thickness fin and the fin side wall of the isolated area is etched
Afterwards, the height of the remaining fin of the isolated area isExtremelyThe etch amount setting of the etching technics is reasonable, with
Etch amount and the device region fin are weighed by two aspects of plasma damage, that is to say, that are etching the isolation
In the step of partial oxidation silicon layer on the segment thickness fin in area and the fin side wall, the present invention is etching as much as possible
While the isolated area fin, the plasma damage caused by adjacent devices area fin can be reduced, and advantageously reduce
The technology difficulty of subsequent wet etching technics, to be conducive to improve the removal effect of the isolated area fin.
In optinal plan, the partial oxidation silicon layer on the segment thickness fin and the fin side wall of the isolated area is etched
Afterwards, before the remaining fin that the isolated area is etched using wet-etching technology, further comprising the steps of: with residual silicon oxide layer is to cover
Film etches the remaining fin of the isolated area using dry etch process, forms initial groove in the remaining fin；Pass through
The dry etch process can further remove the isolation of segment thickness under the protective effect of residual silicon oxide layer
The remaining fin in area makes the subsequent height for forming pseudo- fin to be conducive to improve the removal effect of the isolated area fin
It is smaller.
In optinal plan, the technique for forming the silicon oxide layer is atom layer deposition process, and the silicon oxide layer is also formed
At the top of the fin and on the substrate of fin exposing, therefore during etching the isolated area fin, the oxidation
Silicon layer can play a protective role to the substrate of the isolated area, be conducive to reduce the etching loss that the substrate is subject to.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of semiconductor structure；
Fig. 2 to Fig. 9 is each step counter structure schematic diagram in the forming method first embodiment of semiconductor structure of the present invention；
Figure 10 to Figure 12 is each step counter structure signal in the forming method second embodiment of semiconductor structure of the present invention
Figure；
Figure 13 to Figure 16 is each step counter structure signal in the forming method 3rd embodiment of semiconductor structure of the present invention
Figure；
Figure 17 to Figure 20 is each step counter structure signal in the forming method fourth embodiment of semiconductor structure of the present invention
Figure.
Specific embodiment
It can be seen from background technology that the electric property of prior art semiconductor structure is to be improved.Its reason is analyzed to be:
In technical field of manufacturing semiconductors, with the continuous reduction of characteristic size, in order to effectively fill up more minor node
Photoetching technique blank, improve adjacent semiconductor figure between minimum spacing (pitch) and improve line width roughness
(Liner Width Roughness, LWR) and line edge roughness (Liner Edge Roughness, LER), autoregistration work
Skill is increasingly widely used in fin formation process, such as self-alignment duplex pattern (Self-aligned Double
Patterned, SADP) technique.
Wherein, it is designed according to practical domain (layout), the pattern density in each region of substrate is not identical, according to lining
Bottom surface pattern density is distinguished, and substrate includes graphics intensive area (Dense Area) and figure rarefaction (ISO Area).Accordingly
, the spacing (pitch) of adjacent fin is also not identical.
In conjunction with reference Fig. 1, a kind of structural schematic diagram of semiconductor structure is shown.The semiconductor structure includes substrate 10
And the discrete fin (not indicating) on the substrate 10.
By taking the semiconductor structure is the SRAM of 6T as an example, the fin includes the first fin for being used to form N-type device
11 and it is used to form the second fin 12 of P-type device, therefore the spacing (pitch) of adjacent first fin 11 and the second fin 12
Different from the spacing of two neighboring first fin 11, the spacing of two neighboring first fin 11 is also different.
When adjacent fin spacing difference, after generalling use self-alignment duplex pattern chemical industry skill formation hard mask layer, removal
The hard mask layer of partial region is performed etching using the remaining hard mask layer as exposure mask, forms substrate and fin；But in etching shape
Etching load effect (etch loading effect) is easy to appear during at the fin, so as to cause formed fin
The pattern symmetry in portion is poor, and the fin is easy the problem of being bent because of two lateral stresses asymmetry.
In order to solve the problems, such as to be currently suggested a kind of equidistant (Equal brought by adjacent fin spacing difference
Pitch) the scheme of fin.Specifically, it forms substrate using self-alignment duplex pattern chemical industry skill and is located on the substrate and divide
Vertical fin, the substrate include device region and isolated area, wherein the spacing of the adjacent fin is equal；Described in etching removal
The fin of isolated area.
But during etching removes the fin of the isolated area, the plasma of the etching technics is also easy to
Horizontal proliferation occurs, to be easy to cause plasma damage to adjacent device region fin, and with the progress of etching technics,
The plasma damage that the device region fin adjacent with the isolated area is subject to is more serious, and then causes to remove the isolated area fin
The technique in portion is restricted.
In order to solve the technical problem, after the present invention forms silicon oxide layer on the side wall of fin, etching removal isolation
The silicon oxide layer and fin of area's segment thickness, then using residual silicon oxide layer as exposure mask, institute is etched using wet-etching technology
The remaining fin of isolated area is stated, pseudo- fin is formed.Compared to isolated area fin described in not formed silicon oxide layer and a step dry etching
Scheme, the present invention can increase the etching technics window for etching the isolated area fin, that is, improve the isolated area fin
Removal effect while, reduce the plasma damage caused by adjacent devices area fin.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Fig. 9 is each step counter structure schematic diagram in the forming method first embodiment of semiconductor structure of the present invention.
With reference to Fig. 2, substrate 100 is provided, the substrate 100 includes adjacent device region I and isolated area II, the substrate
Discrete fin (not indicating) is formed on 100, wherein the spacing (Pitch) of the adjacent fin is equal.
The substrate 100 provides technique platform to be subsequently formed fin formula field effect transistor.
In the present embodiment, the substrate 100 of the device region I and isolated area II are respectively formed on discrete fin.Specifically,
Fin on the device region I substrate 100 is the first fin 110, and the fin on the isolated area II substrate 100 is
Second fin 120.
In the present embodiment, the scheme of equidistant (Equal Pitch) fin, i.e., the spacing phase of the adjacent fin are used
Deng.Since when forming the fin, the substrate 100 of the device region I and isolated area II are respectively formed on discrete fin, and
The spacing of the adjacent fin is equal, therefore can improve or avoid etching load effect in the forming process of the fin,
So that the fin have good characteristic size and pattern, improve the pattern symmetry of the fin, reduce the fin because
Two lateral stresses are asymmetric and the probability of bending (bending) phenomenon occur.
First fin 110 is effective fin (Effective Fin), and first fin 110 is for providing institute's shape
At the channel of fin formula field effect transistor.Second fin 120 is to sacrifice fin (Sacrificial Fin), also
It is to say, second fin 120 is fin to be etched, it is subsequent to etch second fin 120, so that the adjacent device
The spacing of part area I increases, and forms isolation structure on the isolated area II substrate 100 between the adjacent device region I.
In the present embodiment, it is illustrated so that the device region I and isolated area II are intervally arranged as an example.But the device region I
It is without being limited thereto with the positional relationship of isolated area II.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate can also be
Germanium, SiGe, silicon carbide, GaAs or gallium indium, the substrate can also be on the silicon substrates or insulator on insulator
Germanium substrate.The material of the substrate can choose the material for being suitable for process requirements or being easily integrated.
The material of the fin is identical as the material of the substrate 100.In the present embodiment, the material of the fin is silicon,
The material of i.e. described first fin 110 and the second fin 120 is silicon.In other embodiments, the material of the fin can be with
It is germanium, SiGe, silicon carbide, GaAs or gallium indium.
It should be noted that in order to reduce the spacing of the characteristic size of the fin and the adjacent fin, to mention
The integrated level of high formed semiconductor structure, forms the fin using multiple graphical technique.It is described multiple in the present embodiment
Patterning process is self-alignment duplex pattern (Self-Aligned Double Patterned, SADP) technique.
Specifically, the step of forming the substrate 100 and fin includes: offer initial substrate；In the initial substrate
Form patterned core layer (core)；Form the side wall film of conformal the covering core layer and initial substrate；Removal is located at institute
The side wall film at the top of core layer and in the initial substrate is stated, retains the side wall film of the core layer side wall as fin exposure mask
200 (as shown in Figure 2) of layer；Remove the core layer；It is exposure mask with the fin mask layer 200 after removing the core layer, carves
The initial substrate is lost, substrate 100 and multiple discrete fins on the substrate 100 are formed.
In other embodiments, the multiple graphical technique can also be the graphical (Self- of autoregistration quadruple
Aligned Quadruple Patterning, SAQP) technique.
In the present embodiment, after forming the substrate 100 and fin, retain the fin mask layer being located at the top of the fin
200.The material of the fin mask layer 200 is silicon nitride, subsequent when carrying out planarization process technique, the fin mask layer
200 top surfaces are used to define the stop position of planarization process technique, and play the role of at the top of the protection fin.
It should be noted that, along perpendicular on fin extending direction, the top dimension of the fin is less than in the present embodiment
Bottom size.
With reference to Fig. 3, silicon oxide layer 130 is formed on the side wall of the fin (not indicating).
The silicon oxide layer 130 is also used to etching for the etch mask as the second fin 120 described in subsequent etching
During second fin 120, play a protective role to first fin 110 adjacent with second fin 120, to subtract
It is small to plasma damage caused by adjacent first fin 110.
The material of the silicon oxide layer 130 is different from the material of the fin, and the material of the silicon oxide layer 130 is easy
In the material being removed, so as to reduce the technique of the subsequent removal silicon oxide layer 130 to the substrate 100 and remaining fin
The damage in portion；In addition, the material of the silicon oxide layer 130 is not also identical as the material of the fin mask layer 200, to avoid
The fin mask layer 200 is removed when the subsequent removal silicon oxide layer 130.
In the present embodiment, the technique for forming the silicon oxide layer 130 is atom layer deposition process.Therefore, in the fin
Side wall in the step of forming silicon oxide layer 130, the silicon oxide layer 130 is also formed at the top of the fin and the fin
On the substrate 100 that portion exposes.Correspondingly, the silicon oxide layer 130 can also be in subsequent etching process to the lining
Bottom 100 plays a protective role, and reduces the etching loss that the substrate 100 is subject to.
It should be noted that being formed with fin mask layer 200 at the top of the fin, therefore formed on the fin side wall
In the step of silicon oxide layer 130, the silicon oxide layer 130 is also located at 200 side wall of fin mask layer and top surface.
It should also be noted that, the thickness of the silicon oxide layer 130 is unsuitable too small, also should not be too large.If the oxidation
The thickness of silicon layer 130 is too small, then is difficult in subsequent etching processes as etch mask, and to the guarantor of first fin 110
It is poor to protect effect, is easy to cause first fin 110 adjacent with second fin 120 by plasma damage；Due to phase
The spacing of the adjacent fin is smaller, the silicon oxide layer if 130 thickness of the silicon oxide layer is excessive, between the adjacent fin
130 the problem of being easy to happen interconnection (Merge), to reduce the formation quality of the silicon oxide layer 130.For this purpose, this reality
Apply in example, the silicon oxide layer 130 with a thickness ofExtremely
In addition, in other embodiments, cushion oxide layer (Liner can also be formed on the side wall of the fin
Oxide), and using the cushion oxide layer as the silicon oxide layer.Specifically, by carrying out oxidation processes to the fin
Mode is to form the cushion oxide layer in the fin side wall.
In conjunction with reference Fig. 4 and Fig. 5, etching removes the segment thickness fin (not indicating) and the fin of the isolated area II
Partial oxidation silicon layer 130 on side wall.
Specifically, etching removes the second fin of segment thickness 120 and 120 side wall of the second fin of the isolated area II
On partial oxidation silicon layer 130.
By the second fin 120 of etched portions thickness, technique base is provided for remaining second fin 120 of subsequent removal
Plinth reduces the difficulty of subsequent etching processes, to improve the removal effect to second fin 120, makes subsequent described second
The surplus of fin 120 is smaller；In addition, subsequent can also avoid etching the residue for exposure mask with residual silicon oxide layer 130
When during the second fin 120, the residual silicon oxide layer 130 avoided the occurrence of on 120 side wall of the second fin collapses
The case where.
It should be noted that as shown in figure 4, in the second fin of segment thickness 120 for etching the isolated area II and described
Before partial oxidation silicon layer 130 on second fin, 120 side wall, further comprise the steps of: formed on the silicon oxide layer 130 it is flat
Layer 310, the flatness layer 310 cover 130 top of silicon oxide layer；Anti-reflection coating is formed on the flatness layer 310
320；Patterned photoresist layer 330 is formed in the anti-reflection coating 320, is had in the photoresist layer 330 and is exposed institute
State the figure opening (not indicating) at 320 top of isolated area II anti-reflection coating.
After forming the photoresist layer 330, further comprises the steps of: with the photoresist layer 330 as exposure mask, opened along the figure
Mouth etches the anti-reflection coating 320 and flatness layer 310 of the isolated area II.
The top surface of the flatness layer 310 is flat surface, to can make photoetching when forming the photoresist layer 330
The uniformity of glue material spin coating uniformity and consistency is improved, and then improves the graphical quality of the photoresist layer 330.This
In embodiment, the flatness layer 310 is the organic bottom antireflective coating (BottomAnti-reflective for mixing C
Coating, BARC).In other embodiments, the flatness layer can also be the carbon coating formed by spin coating proceeding.
The anti-reflection coating 320 is used in the photo-etching technological process for forming the photoresist layer 330, absorption reflect into
The light for entering the anti-reflection coating 320, reduces 320 surface of anti-reflection coating to the reflectivity of particular wavelength region light,
So as to improve standing wave effect, the quality of the photoresist layer 330 after exposure development is improved, so that the figure for improving photoetching process passes
Pass effect.In the present embodiment, the anti-reflection coating 320 is to mix the bottom antireflective coating of Si.
The photoresist layer 330, remaining anti-reflection coating 320 and remaining flatness layer 310 constitute three-decker (tri-
Layer mask layer), for the etch mask as the etching technics.
In the present embodiment, using plasma dry etch process etches the second fin of segment thickness of the isolated area II
Partial oxidation silicon layer 130 in portion 120 and 120 side wall of the second fin.
It should be noted that being joined in the present embodiment by the technique of plasma dry etch process described in reasonable set
Number, keeps the plasma dry etch process close to the etch rate of the silicon oxide layer 130 and the second fin 120, from
And make the partial oxidation silicon layer 130 on the second fin of segment thickness 120 and 120 side wall of the second fin of isolated area II can
To be removed by etching off in the same time；After the plasma dry etch process, the top of residual silicon oxide layer 130 and residue second
The top of fin 120 flushes.
The plasma dry etch process is unsuitable to the etch amount of second fin 120 too small, also should not be too large,
After the i.e. described plasma dry etch process, the height of remaining second fin 120 is unsuitable too small, also should not be too large.It is etching
During second fin 120, the plasma of the plasma dry etch process is easy to happen horizontal proliferation, from
And it is easy to cause plasma damage to first fin 110 adjacent with second fin 120, and to second fin
120 etch amount is bigger, and the plasma damage that first fin 110 is subject to is more serious, therefore the plasma dry
Etching technics should not be too large the etch amount of second fin 120；If etch amount is too small, subsequent etching work accordingly will increase
The technology difficulty of skill.
For this purpose, in the present embodiment, in the second fin of segment thickness 120 and second fin for etching the isolated area II
After partial oxidation silicon layer 130 on 120 side walls, the height of the second fin of residue 120 of the second area II isExtremelyThe height setting of remaining second fin 120 is reasonable, thus etching the same of second fin 120 as much as possible
When, reduce to plasma damage caused by adjacent first fin 110, and the technique for advantageously reducing subsequent etching processes is difficult
Degree, and then be conducive to improve the removal effect of second fin 120.
Correspondingly, according to the setting of 120 height of remaining second fin after the setting of etch rate and the etching technics,
The parameter of plasma dry etch process described in reasonable set.In the present embodiment, the plasma dry etch process
Parameter includes: that etching gas includes N2And H2Mixed gas or O2With the mixed gas of CO, the process time is 60 seconds to 600
Second, process pressure is 10 millitorrs to 50 millitorrs, and source power is 300 watts to 800 watts, and bias power is 50 watts to 300 watts.
As shown in figure 5, in the present embodiment, in the second fin of segment thickness 120 for etching the second area II and described
After partial oxidation silicon layer 130 on second fin, 120 side wall, the removal photoresist layer 330 and anti-reflective coating are further comprised the steps of:
Layer 320.
Specifically, using cineration technics or wet-etching technology, the photoresist layer 330 and anti-reflection coating 320 are removed.
Fig. 6 is referred to it should also be noted that, combining, in the present embodiment, is removing the photoresist layer 330 and anti-reflective coating
After layer 320, the removal flatness layer 310 is further comprised the steps of:.
In other embodiments, the flatness layer can also be retained after removing the photoresist layer and anti-reflection coating,
And the flatness layer is removed after subsequent etching processes.
It is exposure mask with residual silicon oxide layer 130 with reference to Fig. 7, the surplus of the isolated area II is etched using wet-etching technology
Remaining fin (not indicating) forms pseudo- fin 140.
By the wet-etching technology, further to remove remaining second fin 120, to be subsequent in the isolation
Isolation structure is formed on area's II substrate 100, and Process ba- sis is provided；In addition, by way of wet etching, it can be to avoid to described
First fin 110 causes plasma damage.
In the present embodiment, the parameter of the wet-etching technology includes: that etching solution is tetramethyl aqua ammonia (TMAH)
Solution, the mass concentration of the tetramethyl Dilute Ammonia Solution are 1% to 10%, and etch period is 2 seconds to 60 minutes, are etched molten
Liquid temperature is 25 DEG C to 80 DEG C.
The etching selection ratio (Etch Ratio) of the wet-etching technology is higher, that is to say, that the wet etching work
Skill is greater than the etch rate to the silicon oxide layer 130 to the etch rate of remaining second fin 120, to make the silica
Layer 130 plays the role of etch mask during the wet-etching technology.
It should be noted that the wet-etching technology can be along surplus due to the operational characteristic of the wet-etching technology
The lattice of the second fin 120 of remaininging carries out anisotropic etching, therefore after the wet-etching technology, second fin 120
Still there is residue, remaining second fin 120 forms groove 121 as the pseudo- fin 140, and in the pseudo- fin 140.Its
In, the pattern of the groove 121 is depending on the etch amount of the wet-etching technology.
Specifically, when etch amount is smaller, the groove 121 is ladder along the section shape perpendicular to fin extending direction
Shape；When etch amount is larger, the groove 121 is triangle along the section shape perpendicular to fin extending direction.The present embodiment
In, the section shape of the groove 121 is trapezoidal, and according to actual process demand, wet-etching technology described in reasonable set
Parameter.
In the present embodiment, after the wet-etching technology, the height of the puppet fin 140ExtremelyIt is i.e. described
The distance at the top of pseudo- fin 140 to 100 top of the substrate isExtremelyWherein, the height of the pseudo- fin 140
Depending on the etch amount of aforementioned dry plasma etch technique and the etch amount of the wet-etching technology.
121 bottom of groove is higher than 100 top of substrate or the substrate 100 is exposed in 121 bottom of the groove
Top or 121 bottom of the groove are located in the substrate 100.Specifically, the position of 121 bottom of groove is according to institute
Depending on the etch amount for stating wet-etching technology.
It should be noted that the surplus of second fin 120 is smaller after the wet-etching technology, i.e., it is described
The height and small volume of pseudo- fin 140, therefore the insulation of the formation quality and the isolation structure to subsequent isolation structure
The influence of effect is smaller, and the influence to subsequent formed semiconductor structure is also smaller.
Fig. 8 is referred to it should also be noted that, combining, after the wet-etching technology, further comprises the steps of: the remaining oxygen of removal
SiClx layer 130 (as shown in Figure 7)；After removing the residual silicon oxide layer 130, in the device region I fin portion surface and described
Pseudo- 140 surface of fin forms cushion oxide layer (not shown).
In the present embodiment, the technique for removing the residual silicon oxide layer 130 is wet-etching technology.The silicon oxide layer
130 material is silica, therefore etching solution used by the wet-etching technology is hydrofluoric acid solution.Wherein, described
The design parameter of wet-etching technology is depending on the thickness of the silicon oxide layer 130.
It is described to be formed by carrying out oxidation processes to first fin 110 and the pseudo- fin 140 in the present embodiment
Cushion oxide layer.
The effect of the cushion oxide layer includes: one side, during etching forms the substrate 100 and fin,
The etching technics is easy to cause to damage to the fin, by forming the scheme of the cushion oxide layer, can repair described
The damage on 140 surface of the first fin 110 and pseudo- fin, the lattice for removing 140 surface of first fin 110 and pseudo- fin lack
It falls into；On the other hand, by forming the scheme of the cushion oxide layer, first fin 110 can be repaired and pseudo- fin 140 is convex
Faceted portions out are played and are carried out at wedge angle sphering (Corner Rounding) to first fin 110 and pseudo- fin 140
The effect of reason avoids the apex angle point discharge problem of first fin 110 and pseudo- fin 140, is conducive to improve subsequent institute's shape
At the electric property of semiconductor structure.
In the present embodiment, the oxidation processes can also to 100 surface of substrate and 200 surface of fin mask layer into
Row oxidation, therefore, the cushion oxide layer is also located at 100 surface of substrate and 200 surface of fin mask layer.The lining
The material of bottom 100 and fin is silicon, and the material of the fin mask layer 200 is silicon nitride, correspondingly, being located at the substrate 100
The liner oxidation layer material on 140 surface of surface, first fin 110 and pseudo- fin is silica, is located at the fin exposure mask
The liner oxidation layer material on 200 surface of layer is silicon oxynitride.
It should be noted that in other embodiments, after forming the substrate and fin, in the fin portion surface and lining
When bottom surface forms cushion oxide layer using as the silicon oxide layer, correspondingly, after the wet-etching technology, described in reservation
Silicon oxide layer.
With reference to Fig. 9, isolation structure 101 is formed on the substrate 100, the top of the isolation structure 101 is lower than described
The top of device region I fin (not indicating), and cover the top of the pseudo- fin 140.
Isolation structure of the isolation structure 101 as semiconductor devices, for adjacent devices or adjacent first fin
110 play buffer action.In the present embodiment, the material of the isolation structure 101 is silica.In other embodiments, described
The material of isolation structure can also be silicon nitride or silicon oxynitride.
Specifically, the step of forming isolation structure 101 includes: that isolation film is formed on the substrate 100, it is described every
200 top of fin mask layer is covered from film；Using flatening process, removal is higher than 200 top of fin mask layer
Isolation film；Remove the fin mask layer 200；After removing the fin mask layer 200, the remaining isolation for carving segment thickness is returned
Film, the remaining isolation film is as isolation structure 101.
In the present embodiment, in order to improve the filling effect of the isolation film, using mobility chemical vapor deposition
(Flowable Chemical Vapor Deposition, FCVD) technique forms the isolation film, to make the isolation film
In space and the groove 121 (as shown in Figure 8) preferably between the adjacent fin of filling full phase, and reduce the isolation
Occur the probability of gap (Void) in film, and then keeps the compactness of formed isolation structure 101 preferable.
In the present embodiment, the flatening process is chemical mechanical milling tech, and the chemical mechanical milling tech stops
Stop bit is set to the top surface of the fin mask layer 200.
It should be noted that first fin 110, pseudo- fin 140 and 200 surface of fin mask layer are formed with liner oxygen
Change layer (not shown), therefore in the step of forming the isolation film, forms the isolation film in the cushion oxide layer；?
In the step of returning the remaining isolation film for carving segment thickness, the part cushion oxide layer is also removed.Specifically, it is higher than the isolation
The cushion oxide layer at 101 top of structure is removed.
In the present embodiment, the fin mask layer 200 is removed using wet-etching technology.The fin mask layer 200
Material is silicon nitride, correspondingly, etching solution used by the wet-etching technology is phosphoric acid solution.
It should also be noted that, controlling back the etch amount for carving the remaining isolation film according to actual process demand.This implementation
In example, after forming the isolation structure 101,110 height of the first fin for being exposed to 101 top of isolation structure is
Extremely
Correspondingly, being formed by semiconductor structure using above-mentioned forming method the present invention also provides a kind of.
With continued reference to Fig. 9, the semiconductor structure includes:
Substrate 100, the substrate 100 include adjacent device region I and isolated area II, shape on the device region I substrate 100
At there is the first fin 110, it is formed with pseudo- fin 140 on the isolated area II substrate 100, is formed in the puppet fin 140 recessed
Slot 121 (as shown in Figure 8), and lower than 110 top of the first fin at the top of the pseudo- fin 140；On the substrate 100
Isolation structure 101, the top of the isolation structure 101 is lower than the top of first fin 110, and covers the pseudo- fin
140 top.
In the present embodiment, the groove 121 is trapezoidal along the section shape perpendicular to fin extending direction.
To the specific descriptions of the semiconductor structure, accordingly retouching in forming method first embodiment of the present invention is please referred to
It states, details are not described herein.
In conjunction with reference to figures 10 to Figure 12, each step in the forming method second embodiment of semiconductor structure of the present invention is shown
Counter structure schematic diagram.
The present embodiment and forming method first embodiment something in common, details are not described herein by the present invention.The present embodiment and shape
At method first embodiment the difference is that: remaining second fin 420 (as shown in Figure 10) is etched using wet-etching technology
Afterwards, the section shape of the groove 421 (as shown in figure 11) formed in pseudo- fin 440 (as shown in figure 11) is triangle.
As shown in Figure 10 and Figure 11, on etching removal the second fin of segment thickness 420 and 420 side wall of the second fin
It is exposure mask with residual silicon oxide layer 430 after partial oxidation silicon layer 430, remaining second fin is etched using wet-etching technology
420, form pseudo- fin 440.
To the step of the partial oxidation silicon layer 430 on the second fin of etched portions thickness 420 and 420 side wall of the second fin
Suddenly and the specific descriptions of the wet-etching technology, the corresponding description of forming method first embodiment of the present invention is please referred to,
This is repeated no more.
It should be noted that further comprising the steps of: removal residual silicon oxide layer 430 (as schemed after the wet-etching technology
Shown in 11)；After removing the residual silicon oxide layer 430, on 440 surface of 410 surface of the first fin and the pseudo- fin
Form cushion oxide layer (not shown).
The specific descriptions of the step of the step of to removal residual silicon oxide layer 430 and the formation cushion oxide layer, can
With reference to the corresponding description of forming method first embodiment of the present invention, details are not described herein.
With reference to Figure 12, isolation structure 401 is formed on the substrate 400, the top of the isolation structure 401 is lower than described
The top of first fin 410, and cover the top of the pseudo- fin 440.
To the specific descriptions for the step of forming isolation structure 401, forming method first embodiment of the present invention is please referred to
Corresponding description, details are not described herein.
Correspondingly, being formed by semiconductor structure using above-mentioned forming method the present invention also provides a kind of.
2 are continued to refer to figure 1, the semiconductor structure includes:
Substrate 400, the substrate 400 include adjacent device region I and isolated area II, shape on the device region I substrate 400
At there is the first fin 410, it is formed with pseudo- fin 440 on the isolated area II substrate 400, is formed in the puppet fin 440 recessed
Slot 421 (as shown in figure 11), and lower than 410 top of the first fin at the top of the pseudo- fin 440；Positioned at the substrate 400
On isolation structure 401, the top of the isolation structure 401 is lower than the top of first fin 410, and covers the pseudo- fin
The top in portion 440.
In the present embodiment, the groove 421 is triangle along the section shape perpendicular to fin extending direction.
To the specific descriptions of the semiconductor structure, accordingly retouching in forming method second embodiment of the present invention is please referred to
It states, details are not described herein.
Figure 13 to Figure 16 is each step counter structure signal in the forming method 3rd embodiment of semiconductor structure of the present invention
Figure.
The present embodiment and forming method first embodiment something in common, details are not described herein by the present invention.The present embodiment and shape
At method first embodiment the difference is that: in conjunction with reference Figure 13, etching removes the segment thickness the of the second area II
After partial oxidation silicon layer 530 on two fins 520 and 520 side wall of the second fin, further comprise the steps of: with residual silicon oxide layer
530 be exposure mask, etches remaining second fin 520 using dry etch process, is formed in remaining second fin 520 initial
Groove 525.
Segment thickness is further removed under the protective effect of residual silicon oxide layer 530 by the dry etch process
Remaining second fin 520 etch subsequent wet to be conducive to improve the removal effect of second fin 520
The height that pseudo- fin is formed after technique is smaller.
In the present embodiment, by the technological parameter of dry etch process described in reasonable set, make the dry etch process
Etch rate to the silicon oxide layer 530 is greater than to the etch rate of remaining second fin 520, to make the silicon oxide layer
530 play the role of etch mask during the dry etch process, can accordingly reduce to adjacent first fin
540 cause the probability of plasma damage.Wherein, before the depth of the initial groove 525 is according to the dry etch process
Depending on the height of remaining second fin 520.
In the present embodiment, the parameter of the plasma dry etch process includes: that etching gas includes O2、CF4, HBr and
Cl2, the process time is 30 seconds to 300 seconds, and process pressure is 3 millitorrs to 12 millitorrs, and source power is 200 watts to 800 watts, biases function
Rate is 150 watts to 500 watts.
It should be noted that in the present embodiment, etching removal the second fin of segment thickness 520 and second fin 520
After partial oxidation silicon layer 530 on side wall, retain the flatness layer 610.Correspondingly, the flatness layer 610 is carved in the dry method
It during etching technique, can also further play a protective role to adjacent first fin 510, reduce by first fin
510 probability by plasma damage.
In the present embodiment, after the dry etch process, the flatness layer 610 is removed.
It is exposure mask with residual silicon oxide layer 530 with reference to Figure 14, remaining second fin is etched using wet-etching technology
520, form pseudo- fin 540.
In the present embodiment, after the wet-etching technology, groove 521 is formed in remaining second fin 520, and
Remaining second fin 520 is as the pseudo- fin 540.
To the specific descriptions of the wet-etching technology, accordingly retouching for forming method first embodiment of the present invention is please referred to
It states, details are not described herein.
In the present embodiment, the groove 521 is trapezoidal along the section shape perpendicular to fin extending direction.
In conjunction with reference Figure 15, it should be noted that after the wet-etching technology, further comprise the steps of: the remaining oxygen of removal
SiClx layer 530 (as shown in figure 14)；After removing the residual silicon oxide layer 530, on 510 surface of the first fin and described
Pseudo- 540 surface of fin forms cushion oxide layer (not shown).
The specific descriptions of the step of the step of to removal residual silicon oxide layer 530 and the formation cushion oxide layer, can
With reference to the corresponding description of forming method first embodiment of the present invention, details are not described herein.
With reference to Figure 16, after the wet-etching technology, isolation structure 501, the isolation are formed on the substrate 500
The top of structure 501 is lower than the top of first fin 510, and covers the top of the pseudo- fin 540.
To the specific descriptions for the step of forming isolation structure 501, forming method first embodiment of the present invention is please referred to
Corresponding description, details are not described herein.
Correspondingly, being formed by semiconductor structure using above-mentioned forming method the present invention also provides a kind of.
6 are continued to refer to figure 1, the semiconductor structure includes:
Substrate 500, the substrate 500 include adjacent device region I and isolated area II, shape on the device region I substrate 500
At there is the first fin 510, it is formed with pseudo- fin 540 on the isolated area II substrate 500, is formed in the puppet fin 540 recessed
Slot 521 (as shown in figure 15), and lower than 510 top of the first fin at the top of the pseudo- fin 540；Positioned at the substrate 500
On isolation structure 501, the top of the isolation structure 501 is lower than the top of first fin 510, and covers the pseudo- fin
The top in portion 540.
In the present embodiment, the groove 521 is trapezoidal along the section shape perpendicular to fin extending direction.
To the specific descriptions of the semiconductor structure, accordingly retouching in forming method 3rd embodiment of the present invention is please referred to
It states, details are not described herein.
In conjunction with reference Figure 17 to Figure 20, each step in the forming method fourth embodiment of semiconductor structure of the present invention is shown
Counter structure schematic diagram.
The present embodiment and forming method 3rd embodiment something in common, details are not described herein by the present invention.The present embodiment and shape
At method 3rd embodiment the difference is that: remaining second fin 720 (as shown in figure 17) is etched using wet-etching technology
Afterwards, (as shown in figure 18) section shape of groove 721 formed in pseudo- fin 740 (as shown in figure 18) is triangle.
As shown in Figure 17 and Figure 18, remaining second fin 720 is etched using dry etch process, in remaining second fin
It is exposure mask with residual silicon oxide layer 730, using wet-etching technology after forming initial groove 725 (as shown in figure 17) in portion 720
Remaining second fin 720 is etched, and forms groove 721 in remaining second fin 720, after wet-etching technology
Remaining second fin 520 is as pseudo- fin 740.Wherein, the depth of the initial groove 725 is according to the dry etching work
Before skill depending on the height of remaining second fin 520.
The specific descriptions of the step of to the dry etch process please refer to the phase of forming method 3rd embodiment of the present invention
It should describe, details are not described herein.To the specific descriptions of the wet-etching technology, please refers to forming method first of the present invention and implement
The corresponding description of example, details are not described herein.
It should be noted that after the dry etch process, removing described 710 (such as Figure 17 of flatness layer in the present embodiment
It is shown).
In the present embodiment, the groove 721 is triangle along the section shape perpendicular to fin extending direction.
In conjunction with reference Figure 19, it should be noted that after the wet-etching technology, further comprise the steps of: the remaining oxygen of removal
SiClx layer 730 (as shown in figure 18)；After removing the residual silicon oxide layer 730, on 710 surface of the first fin and described
Pseudo- 740 surface of fin forms cushion oxide layer (not shown).
The specific descriptions of the step of the step of to removal residual silicon oxide layer 730 and the formation cushion oxide layer, can
With reference to the corresponding description of forming method first embodiment of the present invention, details are not described herein.
With reference to Figure 20, isolation structure 701 is formed on the substrate 700, the top of the isolation structure 701 is lower than described
The top of first fin 710, and cover the top of the pseudo- fin 740.
The specific descriptions of the step of to formation isolation structure 701, please refer to forming method first embodiment of the present invention
Corresponding description, details are not described herein.
Correspondingly, being formed by semiconductor structure using above-mentioned forming method the present invention also provides a kind of.
With continued reference to Figure 20, the semiconductor structure includes:
Substrate 700, the substrate 700 include adjacent device region I and isolated area II, shape on the device region I substrate 700
At there is the first fin 710, it is formed with pseudo- fin 740 on the isolated area II substrate 700, is formed in the puppet fin 740 recessed
Slot 721 (as shown in figure 19), and lower than 710 top of the first fin at the top of the pseudo- fin 740；Positioned at the substrate 700
On isolation structure 701, the top of the isolation structure 701 is lower than the top of first fin 710, and covers the pseudo- fin
The top in portion 740.
In the present embodiment, the groove 721 is triangle along the section shape perpendicular to fin extending direction.
To the specific descriptions of the semiconductor structure, please refer to corresponding in aforementioned forming method fourth embodiment of the present invention
Description, details are not described herein.Compared to the scheme of isolated area fin described in not formed silicon oxide layer and a step dry etching, the present invention
The etching technics window for etching the isolated area fin can be increased, that is, improving the same of the removal effect of the isolated area fin
When, reduce the plasma damage caused by adjacent devices area fin, so as to improve the electricity of formed semiconductor structure
Performance.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (15)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate includes adjacent device region and isolated area, it is formed with discrete fin on the substrate,
In, the spacing of the adjacent fin is equal；
Silicon oxide layer is formed on the side wall of the fin；
Etching removes the partial oxidation silicon layer on the segment thickness fin and the fin side wall of the isolated area；
Using residual silicon oxide layer as exposure mask, the remaining fin of the isolated area is etched using wet-etching technology, forms pseudo- fin；
Isolation structure is formed over the substrate, and the top of the isolation structure is lower than the top of the device region fin, and covers
Cover the top of the pseudo- fin.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the technique for forming the silicon oxide layer
For atom layer deposition process；
In the step of forming silicon oxide layer on the side wall of the fin, the silicon oxide layer be also formed at the top of the fin with
And on the substrate of fin exposing.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the silicon oxide layer with a thickness ofExtremely
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that using plasma dry etching work
Skill, etching remove the partial oxidation silicon layer on the segment thickness fin and the fin side wall of the isolated area；
It includes N that the parameter of the gas ions dry etch process, which includes: etching gas,2And H2Mixed gas or O2With mixing for CO
Gas is closed, the process time is 60 seconds to 600 seconds, and process pressure is 10 millitorrs to 50 millitorrs, and source power is 300 watts to 800 watts, partially
Setting power is 50 watts to 300 watts.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that etching removes the portion of the isolated area
After dividing the partial oxidation silicon layer on thickness fin and the fin side wall, the height of the remaining fin of the isolated area is
Extremely
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the parameter of the wet-etching technology
Include: etching solution be tetramethyl Dilute Ammonia Solution, the mass concentration of the tetramethyl Dilute Ammonia Solution be 1% to
10%, etch period is 2 seconds to 60 minutes, and etching solution temperature is 25 DEG C to 80 DEG C.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that be formed in the puppet fin recessed
Slot, the groove along the section shape perpendicular to fin extending direction are triangle or trapezoidal.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the bottom portion of groove is higher than the lining
Perhaps the bottom portion of groove exposes the substrate top at the top of bottom or the bottom portion of groove is located in the substrate.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that the top of the puppet fin is to described
The distance of substrate top isExtremely
10. the forming method of semiconductor structure as described in claim 1, which is characterized in that etching removes the isolated area
After partial oxidation silicon layer on segment thickness fin and the fin side wall, the isolated area is etched using wet-etching technology
Before remaining fin, further comprise the steps of:
Using residual silicon oxide layer as exposure mask, the remaining fin of the isolated area is etched using dry etch process, in the residue
Initial groove is formed in fin.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that the dry etch process be etc.
Gas ions dry etch process；
The parameter of the plasma dry etch process includes: that etching gas includes O2、CF4, HBr and Cl2, the process time is
30 seconds to 300 seconds, process pressure was 3 millitorrs to 12 millitorrs, and source power is 200 watts to 800 watts, and bias power is 150 watts to 500
Watt.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that after the wet-etching technology,
It is formed before the isolation structure, is further comprised the steps of:
Remove the residual silicon oxide layer；
After removing the residual silicon oxide layer, liner oxidation is formed in the device region fin portion surface and the pseudo- fin portion surface
Layer.
13. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that remove the residual silicon oxide layer
Technique be wet-etching technology.
14. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the substrate and be located at
The technique of discrete fin is self-alignment duplex pattern chemical industry skill or autoregistration quadruple patterning process on the substrate.
15. a kind of as any one of claim 1 to 14 forming method is formed by semiconductor structure.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755514A (en) * | 2019-03-27 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111785772A (en) * | 2019-04-04 | 2020-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112397450A (en) * | 2019-08-12 | 2021-02-23 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN113394112A (en) * | 2021-05-31 | 2021-09-14 | 上海华力集成电路制造有限公司 | Truncation method applied to fin field effect transistor |
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| CN111785772A (en) * | 2019-04-04 | 2020-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112397450A (en) * | 2019-08-12 | 2021-02-23 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN112397450B (en) * | 2019-08-12 | 2023-09-12 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN113394112A (en) * | 2021-05-31 | 2021-09-14 | 上海华力集成电路制造有限公司 | Truncation method applied to fin field effect transistor |
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Application publication date: 20181218 |