CN113394112A - Truncation method applied to fin field effect transistor - Google Patents

Truncation method applied to fin field effect transistor Download PDF

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Publication number
CN113394112A
CN113394112A CN202110628762.6A CN202110628762A CN113394112A CN 113394112 A CN113394112 A CN 113394112A CN 202110628762 A CN202110628762 A CN 202110628762A CN 113394112 A CN113394112 A CN 113394112A
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CN
China
Prior art keywords
fin
dielectric layer
layer
semiconductor substrate
truncation
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Pending
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CN202110628762.6A
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Chinese (zh)
Inventor
邱靖尧
李镇全
刘立尧
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202110628762.6A priority Critical patent/CN113394112A/en
Publication of CN113394112A publication Critical patent/CN113394112A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The application discloses a truncation method applied to a fin field effect transistor, and relates to the field of semiconductor manufacturing. The method comprises the steps of providing a semiconductor substrate, wherein a fin body of a fin field effect transistor is formed on the semiconductor substrate; forming a first dielectric layer, wherein the first dielectric layer covers the top and the side of the fin body and the semiconductor substrate between the fin bodies; performing fin body cutting process for several times to remove unnecessary fin bodies; removing the first dielectric layer by a wet etching process; wherein, fin body cuts the technology every time and includes: forming a second dielectric layer on the surface of the first dielectric layer; defining a truncation area of the fin body through a photoetching process; removing the fin bodies corresponding to the cut-off regions through an etching process; removing the residual photoresist on the surface of the semiconductor substrate; removing the second dielectric layer by a wet etching process; the problem that the characteristic size of a fin body is reduced in the conventional fin field effect transistor truncation process is solved; the effect of ensuring that the characteristic size of the fin body still meets the performance requirement after the fin body is cut off is achieved.

Description

Truncation method applied to fin field effect transistor
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a truncation method applied to a fin field effect transistor.
Background
A Fin-Field-Effect Transistor (FinFET) is a complementary metal-oxide-semiconductor Transistor.
In the fin field effect transistor process, after the fin body is formed, unnecessary fin bodies need to be removed through a truncation process. At present, a truncation process defines a truncation area by adopting a photoetching mode, and then a fin body in the truncation area is removed by dry etching.
After the fin body in the truncation region is removed, the residual photoresist needs to be removed. However, a silicon oxide layer is formed on the surface of the fin body due to oxidation during the photoresist stripping process, and the silicon oxide layer on the surface of the fin body is lost during the cleaning process to remove by-products on the surface of the device, so that the Critical Dimension (CD) of the fin body is reduced, and the performance of the device is affected.
Disclosure of Invention
In order to solve the problems in the related art, the present application provides a clipping method applied to a fin field effect transistor. The technical scheme is as follows:
in one aspect, an embodiment of the present application provides a clipping method applied to a fin field effect transistor, where the method includes:
providing a semiconductor substrate, wherein a fin body of a fin field effect transistor is formed on the semiconductor substrate;
forming a first dielectric layer, wherein the first dielectric layer covers the top and the side of the fin body and the semiconductor substrate between the fin bodies;
performing fin body cutting process for several times to remove unnecessary fin bodies;
removing the first dielectric layer by a wet etching process;
wherein, fin body cuts the technology every time and includes:
forming a second dielectric layer on the surface of the first dielectric layer;
defining a truncation area of the fin body through a photoetching process;
removing the fin bodies corresponding to the cut-off regions through an etching process;
removing the residual photoresist on the surface of the semiconductor substrate;
and removing the second dielectric layer by a wet etching process.
Optionally, the first dielectric layer is a silicon nitride layer.
Optionally, the removing the first dielectric layer by a wet etching process includes:
and removing the first dielectric layer by using a phosphoric acid solution.
Optionally, the second dielectric layer is a silicon oxide layer.
Optionally, removing the second dielectric layer by wet etching includes:
and removing the second dielectric layer by using hydrofluoric acid solution and/or sulfuric acid solution.
Optionally, a hard mask layer is formed on the top of the fin.
Optionally, the hard mask layer is formed by sequentially stacking an oxide layer, a nitride layer, and an oxide layer.
Optionally, defining the truncation region of the fin body by a photolithography process includes:
coating spin-on carbon on the semiconductor substrate, wherein the spin-on carbon completely fills gaps between the fin bodies;
coating photoresist on the surface of the spin-coated carbon layer;
and exposing the semiconductor substrate by using a mask plate comprising the pattern of the truncation area, and defining the truncation area in the photoresist layer and the spin-on carbon layer after developing.
The technical scheme at least comprises the following advantages:
providing a semiconductor substrate with fin bodies, forming a first medium layer, covering the top and the side of the fin bodies and the semiconductor substrate among the fin bodies with the first medium layer, performing a fin body cutting process for a plurality of times, removing unnecessary fin bodies, and removing the first medium layer through a wet etching process; in the fin body cutting process, a second dielectric layer is formed on the surface of the first dielectric layer, unnecessary fin bodies are cut off through photoetching and etching processes, residual photoresist on the surface of the semiconductor substrate is removed, and the second dielectric layer is removed through a wet etching process; the problem that the characteristic size of a fin body is reduced in the conventional fin field effect transistor truncation process is solved; the effects of optimizing the process flow, increasing the whole process flow window and ensuring that the characteristic dimension of the fin body still meets the performance requirement after the fin body is cut off are achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a truncation method applied to a finfet according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a semiconductor substrate with fins formed thereon according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of an implementation of a truncation method applied to a finfet according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of an implementation of a truncation method applied to a finfet according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of an implementation of a truncation method applied to a finfet according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a device structure after a fin truncation process provided by an embodiment of the present application;
fig. 7 is a schematic diagram of an implementation of a truncation method applied to a finfet according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of an implementation of a truncation method applied to a finfet according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram of an implementation of a truncation method applied to a finfet according to an embodiment of the present disclosure;
fig. 10 is a schematic diagram of an implementation of a truncation method applied to a finfet according to an embodiment of the present disclosure;
wherein: 21, a semiconductor substrate; 22, a fin body; 23, an oxide layer; 24, a nitride layer; 25, an oxide layer; 20, a hard mask layer; 26, a first dielectric layer/silicon nitride layer; 27, a second dielectric layer/silicon oxide layer; 28, SOC; 29, photoresist; and 30, cutting off the area.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a truncation method applied to a finfet according to an embodiment of the present disclosure is shown. The method at least comprises the following steps:
in step 101, a semiconductor substrate is provided, on which a fin of a finfet is formed.
Optionally, a semiconductor substrate is provided, and a fin body of the fin field effect transistor is formed on the semiconductor substrate through photolithography and etching processes.
As shown in fig. 2, fins 22 are formed on a substrate 21 at intervals.
In step 102, a first dielectric layer is formed to cover the top and the side of the fin body and the semiconductor substrate between the fin bodies.
As shown in fig. 3, a first dielectric layer 26 is formed on the semiconductor substrate 21, and the first dielectric layer 26 is formed to cover the top and the side of the fin 22 and the surface of the semiconductor substrate between the fins 22.
In step 103, a fin truncation process is performed several times to remove unnecessary fins.
After the spaced fins 22 are formed on the semiconductor substrate by photolithography and etching, the unnecessary fins need to be cut off in a subsequent process.
The optional fins are additional fins relative to fins that must be present in the device structure.
The fin body truncation process is required to be carried out for a plurality of times in the fin field effect transistor, the positions of the fin bodies removed by the fin body truncation process each time are different, and the fin body truncation process each time comprises the following steps:
in step 1031, a second dielectric layer is formed on the surface of the first dielectric layer.
Because the characteristic dimension of the fin body is reduced due to the processes of photoetching, photoresist removal, cleaning and the like in the implementation process of the conventional cutting process, a first dielectric layer and a second dielectric layer are formed outside the fin body before photoetching in the fin body cutting process provided by the embodiment of the application, the material loss caused by the processes of photoresist removal, cleaning and the like is limited to the increased first dielectric layer and the increased second dielectric layer, the loss of silicon oxide forming the fin body in the cutting process is avoided, and the characteristic dimension of the fin body is reduced after the cutting process is further avoided.
As shown in fig. 4, a second dielectric layer 27 is formed on the surface of the first dielectric layer 26.
In step 1032, the truncated regions of the fins are defined by a photolithography process.
And defining a truncation region of the fin body through a photoetching process, wherein the fin body corresponding to the truncation region is an unnecessary fin body and needs to be removed.
It should be noted that, in the fin body truncation process, the position of the truncation region defined by the photolithography process is different each time.
In step 1033, the fin corresponding to the cut-off region is removed by an etching process.
Optionally, the fin body corresponding to the truncation region is removed by a dry etching process.
In step 1034, the residual photoresist on the surface of the semiconductor substrate is removed.
After the optional fin removal, the residual photoresist on the surface of the semiconductor substrate 21 is removed, as shown in fig. 5.
During the photoresist stripping process, a silicon oxide layer is formed on the surface of the fin 22, and a polymer (polymer) is formed on the semiconductor substrate 21.
In step 1035, the second dielectric layer is removed by a wet etch process.
And cleaning the polymer gathered on the semiconductor substrate by a wet etching process, and simultaneously removing the second dielectric layer in the wet cleaning process, wherein the first dielectric layer still covers the top and the side surfaces of the fin bodies and the semiconductor substrate between the fin bodies.
It should be noted that, if the fin cutting process needs to be performed more than 1 time, after step 102, steps 1031 to 1034 are repeatedly performed, and after all unnecessary fins are removed, step 104 is performed again.
In the cleaning process of the semiconductor substrate after the unnecessary fin bodies are removed by photoetching and etching, because the first dielectric layer is used for protecting the outside of the fin bodies, the material loss in the cleaning process is transferred to the first dielectric layer, and the loss of the fin bodies is reduced.
In step 104, the first dielectric layer is removed by a wet etching process.
And after the cutting of the unnecessary fin bodies is finished, removing the first dielectric layer through a wet etching process. When the first dielectric layer is removed, the selected wet etching solution has a high selection ratio to the first dielectric layer and the silicon oxide, that is, the rate of etching the first dielectric layer by the wet etching solution is greater than the rate of etching the silicon oxide by the wet etching solution.
As shown in fig. 6, the first dielectric layer is removed. The wet etching solution for removing the first dielectric layer is different from the wet etching solution for removing the second dielectric layer.
In summary, the truncation method applied to the fin field effect transistor provided by the embodiment of the present application forms the first dielectric layer by providing the semiconductor substrate on which the fin body is formed, the first dielectric layer covers the top and the side of the fin body and the semiconductor substrate between the fin bodies, performs the fin body truncation process for a plurality of times, removes unnecessary fin bodies, and removes the first dielectric layer by the wet etching process; in the fin body cutting process, a second dielectric layer is formed on the surface of the first dielectric layer, unnecessary fin bodies are cut off through photoetching and etching processes, residual photoresist on the surface of the semiconductor substrate is removed, and the second dielectric layer is removed through a wet etching process; the problem that the characteristic size of a fin body is reduced in the conventional fin field effect transistor truncation process is solved; the effects of optimizing the process flow, increasing the whole process flow window and ensuring that the characteristic dimension of the fin body still meets the performance requirement after the fin body is cut off are achieved.
Another embodiment of the present application provides a truncation method applied to a fin field effect transistor, wherein a first dielectric layer is a silicon nitride layer, and a second dielectric layer is a silicon oxide layer, the method including the steps of:
in step 201, a semiconductor substrate having a fin of a finfet formed thereon is provided.
In the process of forming the fin body, a hard mask layer is formed on the surface of the semiconductor substrate, and after the fin body is formed through photoetching and etching processes, the hard mask layer is also arranged on the top of the fin body.
Optionally, the hard mask layer is formed by sequentially stacking an oxide layer, a nitride layer, and an oxide layer.
As shown in fig. 2, spaced fins 22 are formed on a semiconductor substrate 21, a hard mask layer 20 is formed on top of the fins 22, and the hard mask layer 20 is formed by sequentially stacking an oxide layer 23, a nitride layer 24, and an oxide layer 25.
In step 202, a silicon nitride layer is formed.
As shown in fig. 3, a silicon nitride layer 26 is formed on the semiconductor substrate 21, and the silicon nitride layer 26 covers the hard mask layer 30 on the top of the fin 22, the sidewalls of the fin 22, and the surface of the semiconductor substrate between the fins 22.
In step 203, a fin truncation process is performed several times to remove unnecessary fins.
The number of times of performing the fin body truncation process is determined according to actual conditions, and the number is not limited in the embodiment of the application.
Each fin body cutting process comprises the following steps:
in step 2031, a silicon oxide layer is formed on the surface of the silicon nitride layer.
Since the silicon nitride layer is liable to cause the poisoning effect of the photoresist, before the photolithography process, an oxide layer is formed on the surface of the silicon nitride layer.
As shown in fig. 4, a silicon oxide layer 27 is formed on the surface of the silicon nitride layer 26.
In step 2032, a Spin On Carbon (SOC) is applied to the semiconductor substrate, which completely fills the gaps between the fins.
As shown in fig. 7, spin-on carbon 28 is coated on the semiconductor substrate 21, the spin-on carbon 28 fills the gaps between the fins 22, and the spin-on carbon 28 is higher than the hard mask layer 30.
In step 2033, a photoresist is applied to the surface of the spun-on carbon layer.
As shown in fig. 8, a photoresist layer 29 is formed on the surface of the spun-on carbon layer 28.
In step 2034, the semiconductor substrate is exposed using a reticle that includes a pattern of cut-off regions, and the cut-off regions are defined in the photoresist layer and the spun-on carbon layer after development.
As shown in fig. 9, after the development, the photoresist and the spin-on carbon corresponding to the cutting region 30 are removed, and the fin 22 corresponding to the cutting region 30 is an unnecessary gas to be cut.
In step 2035, the fin corresponding to the cut-off region is removed by an etching process.
As shown in fig. 10, the fin body corresponding to the truncation region 30 is removed by a dry etching process.
In step 2036, the residual photoresist on the surface of the semiconductor substrate is removed.
During the photoresist stripping process, polymer aggregation occurs on the surface of the semiconductor substrate.
In step 2037, the silicon oxide layer is removed using a hydrofluoric acid solution and/or a sulfuric acid solution.
And cleaning the semiconductor substrate by using hydrofluoric acid solution and/or sulfuric acid solution to remove the polymer on the surface of the semiconductor substrate and simultaneously remove the silicon oxide layer.
Because the silicon nitride layer is arranged below the silicon oxide layer, the fin body below the silicon nitride layer is not corroded by the corrosive solution.
It should be noted that, if the fin cutting process needs to be performed more than 1 time, after step 202, steps 2031 to 2034 are repeated, and after the unnecessary fins are completely removed, step 104 is performed again.
In step 204, the silicon nitride layer is removed using a phosphoric acid solution.
And after the cutting process of all the fin bodies is finished, cleaning the semiconductor substrate by using a phosphoric acid solution, and removing the silicon nitride layer on the semiconductor substrate. Because phosphoric acid has a high selection ratio to silicon nitride and silicon oxide, the loss amount of silicon oxide on the surface of the fin body is greatly reduced in the cleaning process, and the characteristic size of the fin body is ensured.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (8)

1. A truncation method applied to a fin field effect transistor (FinFET), the truncation method comprising:
providing a semiconductor substrate, wherein a fin body of a fin field effect transistor is formed on the semiconductor substrate;
forming a first dielectric layer, wherein the first dielectric layer covers the top and the side of the fin body and the semiconductor substrate between the fin bodies;
performing fin body cutting process for several times to remove unnecessary fin bodies;
removing the first dielectric layer by a wet etching process;
wherein, fin body cuts the technology every time and includes:
forming a second dielectric layer on the surface of the first dielectric layer;
defining a truncation area of the fin body through a photoetching process;
removing the fin bodies corresponding to the truncation regions through an etching process;
removing the residual photoresist on the surface of the semiconductor substrate;
and removing the second dielectric layer by a wet etching process.
2. The method of claim 1, wherein the first dielectric layer is a silicon nitride layer.
3. The method of claim 2, wherein removing the first dielectric layer by a wet etch process comprises:
and removing the first dielectric layer by using a phosphoric acid solution.
4. The method of claim 1 or 2, wherein the second dielectric layer is a silicon oxide layer.
5. The method of claim 4, wherein removing the second dielectric layer by wet etching comprises:
and removing the second dielectric layer by using hydrofluoric acid solution and/or sulfuric acid solution.
6. The method of claim 1, wherein a hard mask layer is formed on top of the fin.
7. The method of claim 6, wherein the hard mask layer comprises an oxide layer, a nitride layer, and an oxide layer stacked in sequence.
8. The method of claim 1, wherein defining the truncation region of the fin by a photolithographic process comprises:
coating spin-on carbon on the semiconductor substrate, wherein the spin-on carbon completely fills gaps among the fin bodies;
coating photoresist on the surface of the spin-coated carbon layer;
and exposing the semiconductor substrate by using a mask plate comprising a pattern of the truncation region, and defining the truncation region in the photoresist layer and the spin-on carbon layer after developing.
CN202110628762.6A 2021-05-31 2021-05-31 Truncation method applied to fin field effect transistor Pending CN113394112A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150249127A1 (en) * 2014-03-03 2015-09-03 Globalfoundries Inc. Methods of forming fins for finfet semiconductor devices and selectively removing some of the fins by performing a cyclical fin cutting process
US9559014B1 (en) * 2015-09-04 2017-01-31 International Business Machines Corporation Self-aligned punch through stopper liner for bulk FinFET
US9589958B1 (en) * 2016-01-22 2017-03-07 International Business Machines Corporation Pitch scalable active area patterning structure and process for multi-channel finFET technologies
CN106571336A (en) * 2015-10-12 2017-04-19 中芯国际集成电路制造(上海)有限公司 Method for forming fin field effect transistor
CN106653604A (en) * 2015-11-04 2017-05-10 中芯国际集成电路制造(上海)有限公司 Forming method of fin type field-effect tube
CN109037068A (en) * 2017-06-08 2018-12-18 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150249127A1 (en) * 2014-03-03 2015-09-03 Globalfoundries Inc. Methods of forming fins for finfet semiconductor devices and selectively removing some of the fins by performing a cyclical fin cutting process
US9559014B1 (en) * 2015-09-04 2017-01-31 International Business Machines Corporation Self-aligned punch through stopper liner for bulk FinFET
CN106571336A (en) * 2015-10-12 2017-04-19 中芯国际集成电路制造(上海)有限公司 Method for forming fin field effect transistor
CN106653604A (en) * 2015-11-04 2017-05-10 中芯国际集成电路制造(上海)有限公司 Forming method of fin type field-effect tube
US9589958B1 (en) * 2016-01-22 2017-03-07 International Business Machines Corporation Pitch scalable active area patterning structure and process for multi-channel finFET technologies
CN109037068A (en) * 2017-06-08 2018-12-18 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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