CN105206583A - SOI-based strained-Si-channel inverted-trapezoid-grid CMOS integrated device and preparation method thereof - Google Patents

SOI-based strained-Si-channel inverted-trapezoid-grid CMOS integrated device and preparation method thereof Download PDF

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CN105206583A
CN105206583A CN201510540303.7A CN201510540303A CN105206583A CN 105206583 A CN105206583 A CN 105206583A CN 201510540303 A CN201510540303 A CN 201510540303A CN 105206583 A CN105206583 A CN 105206583A
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nmos
pmos
grid
active regions
regions
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刘翔宇
王斌
胡辉勇
张鹤鸣
宋建军
舒斌
宣荣喜
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

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Abstract

The invention relates to an SOI-based strained-Si-channel inverted-trapezoid-grid CMOS integrated device and a preparation method thereof. The preparation method comprises: selecting an SOI substrate; growing a P type SiGe layer and an N type strained Si layer to form an NMOS active region and a PMOS active region; carrying out etching process to form an isolated groove; carrying out an ion implantation process on the surface of the NMOS active region to form a P type well region; carrying out photoetching on the surface of the NMOS active region to form an NMOS grid region pattern and carrying out processing by a particle beam etching process to form a first dual-trapezoid groove; carrying out photoetching on the surface of the PMOS active region to form a PMOS grid region pattern and carrying out processing by a particle beam etching process to form a second dual-trapezoid groove; growing an oxidation layer to form an NMOS gate dielectric material and a PMOS gate dielectric material; carrying out etching on the PMOS gate dielectric material and forming PMOS source and drain regions by using an ion implantation process and carrying out etching on the NMOS gate dielectric material and forming NMOS source and drain regions by using an ion implantation process; growing a grid material to form an NMOS grid electrode and a PMOS grid electrode; and carrying out metallization processing and carrying out drain lead, source lead, and grid lead photoetching to form an SOI-based strained-Si-channel inverted-trapezoid-grid CMOS integrated device.

Description

Based on strained Si channel inverted trapezoidal grid CMOS integrated device and the preparation method of SOI
Technical field
The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of strained Si channel inverted trapezoidal grid CMOS integrated device based on SOI and preparation method.
Background technology
Microelectronics is the physical phenomenon of research electronics in semiconductor and IC, physics law, disease is devoted to the application of these physical phenomenons, physics law, comprises device physics, device architecture, material preparation, integrated technique, Circuits and Systems design, the automatically a series of theory and technology problem such as test and encapsulation, assembling.The object of microelectronics research, except integrated circuit, also comprises integrated-optic device, integrated superconductive device etc.
Semiconductor studies the microminiaturized circuitry formed on solid (mainly semiconductor) material, the electronics branch of subsystem and system is the mainly motion in solid material of research electronics or ion and an application utilize it to realize the science of signal processing function.Semiconductor is integrated into object with realizing circuit and system, and the circuit that it realizes and system are also called integrated circuit and integrated system, are microminaturizations.The application technology of semiconductor is microelectric technique, and it is the key point of information technology.The space scale of semiconductor technology is normally in units of micron and nanometer.At present, the development level of semiconductor technology and industry size have become the important symbol of a national economic strength.
" Moore's Law " part to semiconductor industry development has an immense impact on: the transistor size in integrated circuit (IC) chip, within about every 18 months, double, performance is also doubled.Over more than 40 year, world semiconductor industry constantly develops according to this law all the time.But along with the continuous reduction of device feature size, after especially entering nano-scale, the development of microelectric technique more and more approaches the limit of material, technology and device, is faced with huge challenge.After device feature size narrows down to 65nm, the impact of the short channel effect in nano-scale device, high-field effect, quantum effect, parasitic parameter, the impact of the problems such as technological parameter error on performances such as device Leakage Current, pressure threshold characteristic, ON state/off-state currents is more and more outstanding, and the contradiction of circuit speed and power consumption also will be more serious.
In order to solve the problem, new material, new technology and new technology are employed, but effect is not very good.Such as: although tunnel-through diode current on/off ratio is very high, cost of manufacture is high, and ON state current is little; Grapheme material charge carrier has high mobility, but the too small problem of energy gap is never well solved.FinFET can effectively reduce Leakage Current, but complex process and device electricity promote limited efficiency.Therefore, how to make a kind of high performance CMOS integrated device just to become and important.
Summary of the invention
Therefore, for solving technological deficiency and the deficiency of prior art existence, the present invention proposes a kind of strained Si channel inverted trapezoidal grid CMOS integrated device based on SOI and preparation method.
Particularly, the preparation method of a kind of strained Si channel inverted trapezoidal grid CMOS integrated device based on SOI that the embodiment of the present invention proposes, comprising:
A () chooses SOI substrate;
B () be growing P-type SiGe layer and N-type strained si layer/in described SOI substrate, to form NMOS active area and PMOS active area;
C () adopts etching technics to form isolated groove between described NMOS active area and described PMOS active area;
D () adopts ion implantation technology to form P type trap zone in described NMOS surfaces of active regions;
E () forms NMOS gate regions figure in described NMOS surfaces of active regions photoetching, adopt particle beams etching technics to form the first double trapezoid groove; Form PMOS gate regions figure in described PMOS surfaces of active regions photoetching, adopt particle beams etching technics to form the second double trapezoid groove;
F () forms NMOS gate dielectric material and PMOS gate dielectric material in described NMOS surfaces of active regions and described PMOS surfaces of active regions growth oxide layer;
G () differs from graphics field, described NMOS gate regions in described PMOS surfaces of active regions and etches described PMOS gate dielectric material and adopt ion implantation technology to form PMOS source drain region, differ from graphics field, described NMOS gate regions etch described NMOS gate dielectric material and adopt ion implantation technology to form NMOS source-drain area in described NMOS surfaces of active regions;
H () grows grid material respectively in described first double trapezoid groove surfaces and described second double trapezoid groove surfaces and forms NMOS grid and PMOS grid; And
(i) metalized, and photoetching drain lead, source lead and grid lead, the final strained Si channel inverted trapezoidal grid CMOS integrated device formed based on SOI.
In addition, a kind of strained Si channel inverted trapezoidal grid CMOS integrated device based on SOI that another embodiment of the present invention proposes, is obtained by the preparation method of the strained Si channel inverted trapezoidal grid CMOS integrated device based on SOI of above-described embodiment.
In sum, preparation method's tool of the present embodiment has the following advantages:
1. the cmos device that prepared by the present invention employs identical channel material, reduces manufacturing cost and the technology difficulty of integrated circuit;
2. trapezoidal grid can be equivalent to the accumulation of infinite multiple small stair, and according to edge-crowding effect of current, the current density at step place can increase, thus reduces the current density at raceway groove place, obtain higher puncture voltage to make cmos circuit;
3. because grid structure is not planar structure, gate capacitance is no longer traditional capacity plate antenna, adds the grid-control ability of device, increases the puncture voltage of cmos circuit when OFF state, adds the reliability of cmos circuit;
4. the channel material that the present invention utilizes is strain Si material, improves several times, thus improve current drives and the frequency characteristic of cmos device relative to traditional Si material carrier mobility;
5. due to process proposed by the invention and existing Si integrated circuit processing technology compatibility, therefore, when any fund and equipment investment need not be added, strained Si channel cmos device and integrated circuit can be prepared, the significantly lifting of domestic integrated circuit working ability can be achieved.
By the detailed description below with reference to accompanying drawing, other side of the present invention and feature become obvious.But it should be known that this accompanying drawing is only the object design of explanation, instead of as the restriction of scope of the present invention, this is because it should with reference to additional claim.Should also be appreciated that, unless otherwise noted, unnecessaryly draw accompanying drawing to scale, they only try hard to structure described herein and flow process are described conceptually.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is preparation method's flow chart of a kind of strained Si channel inverted trapezoidal grid CMOS integrated device based on SOI of the embodiment of the present invention;
Fig. 2 a-Fig. 2 t is preparation method's schematic diagram of a kind of strained Si channel inverted trapezoidal grid CMOS integrated device based on SOI of the embodiment of the present invention; And
Fig. 3 is the device architecture schematic diagram of a kind of strained Si channel inverted trapezoidal grid CMOS integrated device based on SOI of the embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Embodiment one
Please participate in Fig. 1, Fig. 1 is preparation method's flow chart of a kind of strained Si channel inverted trapezoidal grid CMOS integrated device based on SOI of the embodiment of the present invention, and this preparation method comprises the steps:
A () chooses SOI substrate;
B () be growing P-type SiGe layer and N-type strained si layer/in described SOI substrate, to form NMOS active area and PMOS active area;
C () adopts etching technics to form isolated groove between described NMOS active area and described PMOS active area;
D () adopts ion implantation technology to form P type trap zone in described NMOS surfaces of active regions;
E () forms NMOS gate regions figure in described NMOS surfaces of active regions photoetching, adopt particle beams etching technics to form the first double trapezoid groove; Form PMOS gate regions figure in described PMOS surfaces of active regions photoetching, adopt particle beams etching technics to form the second double trapezoid groove;
F () forms NMOS gate dielectric material and PMOS gate dielectric material in described NMOS surfaces of active regions and described PMOS surfaces of active regions growth oxide layer;
G () differs from graphics field, described NMOS gate regions in described PMOS surfaces of active regions and etches described PMOS gate dielectric material and adopt ion implantation technology to form PMOS source drain region, differ from graphics field, described NMOS gate regions etch described NMOS gate dielectric material and adopt ion implantation technology to form NMOS source-drain area in described NMOS surfaces of active regions;
H () grows grid material respectively in described first double trapezoid groove surfaces and described second double trapezoid groove surfaces and forms NMOS grid and PMOS grid; And
(i) metalized, and photoetching drain lead, source lead and grid lead, the final strained Si channel inverted trapezoidal grid CMOS integrated device formed based on SOI.
Particularly, step (b) comprising:
(b1) in described SOI substrate, grow the SiGe layer of N-type content gradually variational;
(b2) in the SiGe layer superficial growth relaxed sige layer of described content gradually variational, in described relaxed sige layer, the concentration of Ge equals the concentration of the Ge at the SiGe layer top of described content gradually variational;
(b3) in described relaxed sige layer superficial growth strained si layer/, to form NMOS active area and PMOS active area.
Particularly, step (c) comprising:
(c1) photoetching process is utilized to form isolated area figure between described NMOS active area and described PMOS active area;
(c2) utilize etching technics, in described isolated area figure position, etching forms described isolated groove;
(c3) oxide is adopted to fill described isolated groove;
(c4) protective layer is formed at described oxide surface growing nitride;
(c5) utilize CMP (Chemical Mechanical Polishing) process to remove described nitride and remove the growth thickness that thickness is described nitride, or, utilize CMP (Chemical Mechanical Polishing) process to remove described nitride and described oxide and the described nitride of part retained above described isolated groove;
(c6) anisotropic etch process is utilized to etch described oxide, to form described isolated groove.
Particularly, step (d) comprising:
(d1) on described NMOS surfaces of active regions and table formation first barrier layer, described PMOS source district;
(d2) described first barrier layer of described NMOS surfaces of active regions is etched;
(d3) ion implantation technology is adopted to form described P trap at described NMOS surfaces of active regions implanting p-type ion;
(d4) described first barrier layer is removed.
Particularly, step (e) comprising:
(e1) the second barrier layer is formed in described NMOS surfaces of active regions and described PMOS surfaces of active regions;
(e2) form described NMOS gate regions figure in the photoetching of described NMOS surfaces of active regions, utilize particle beams etching technics to form described first double trapezoid groove in described NMOS surfaces of active regions in graphics field, described NMOS gate regions;
(e3) described second barrier layer is removed;
(e4) the 3rd barrier layer is formed in described NMOS surfaces of active regions and described PMOS surfaces of active regions;
(e5) form described PMOS gate regions figure in the photoetching of described PMOS surfaces of active regions, utilize particle beams etching technics to form described second double trapezoid groove in described PMOS surfaces of active regions in graphics field, described PMOS gate regions;
(e6) described 3rd barrier layer is removed.
Particularly, described particle beams etching technics is: adopt argon (Ar) particle as the particle beams, fixing line is 50mA, and bias condition is 400 ~ 700V.
Particularly, described gate dielectric material is Al 2o 3or HfO 2, described grid material is metal.
The embodiment of the present invention, CMOS integrated device is formed by adopting strained silicon (Si) raceway groove inverted trapezoidal bar high-voltage P MOS and nmos device on soi substrates, namely pass through growth strain SiGe (Si) layer on soi substrates and form the channel layer of nmos device and PMOS in CMOS integrated device, adopt the dry etching of anisotropic to etch two inverted ladder type grooves, achieve strained Si channel inverted trapezoidal grid high-voltage CMOS circuit.
It should be noted that, in the present embodiment, in step (e), the processing flow sequence of the first double trapezoid groove and the second double trapezoid groove does not limit, namely first can form the first trapezoidal groove and form the second trapezoidal groove again, also first can form the second trapezoidal groove and form the first trapezoidal groove again.In like manner, the formation NMOS grid in the formation NMOS source-drain area in step (g) and the order in PMOS source drain region and step (g) and the order of PMOS grid also do not limit.
In addition, first, second grade is just arranged for the ease of clear description.Namely be understandable that, the relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and does not require to exist between these entities or operation the relation or sequentially of any reality.
Embodiment two
Refer to Fig. 2 a-Fig. 2 t, Fig. 2 a-Fig. 2 t is preparation method's schematic diagram of a kind of strained Si channel inverted trapezoidal grid CMOS integrated device based on SOI of the embodiment of the present invention, on the basis of above-described embodiment one, be described in detail to prepare strained silicon (Si) the raceway groove inverted trapezoidal grid CMOS integrated device that conducting channel is 50nm, concrete steps are as follows:
S101, substrate are chosen.As shown in Figure 2 a, choose and be doped to 1 × 10 17cm -3~ 5 × 10 17cm -3top layer silicon (Si) thickness is silicon (Silicon-On-Insulator the is called for short SOI) substrate slice 201 in the dielectric substrate of 1 ~ 2 μm is original material;
S102, outer layer growth:
S1021, as shown in Figure 2 b, utilize the method for chemical vapor deposition (CVD), at 300 ~ 400 DEG C, SOI substrate sheet 201 grows SiGe (SiGe) the layer epitaxial loayer 202 of the thick N-type content gradually variational of one deck 1 ~ 2 μm, bottom Ge content is 0, top Ge content is 0.3 ~ 0.4, and its doping content is 1 × 10 18cm -3~ 5 × 10 18cm -3, the benefit done like this is the stability improving SiGe layer, not easily relaxation phenomena occurs;
S1022, as shown in Figure 2 c, utilize the method for CVD, the SiGe layer epitaxial loayer 202 of content gradually variational grows the P type relaxed sige layer 203 of one deck 100 ~ 200nm, and its doping content is 1 × 10 18cm -3~ 5 × 10 18cm -3, Ge content is 0.3 ~ 0.4, equal with the SiGe layer top Ge content of content gradually variational;
S1023, as shown in Figure 2 d, utilize the method for CVD, relaxed sige layer epitaxial loayer 203 grows N-type strained silicon (Si) layer 204 of one deck 20 ~ 30nm, and its doping content is 1 × 10 18cm -3~ 5 × 10 18cm -3, strain Si material, improves several times relative to traditional Si material carrier mobility, thus improves current drives and the frequency characteristic of cmos device;
The preparation of S103, isolated area:
As shown in Figure 2 e, photoetching shallow trench isolation region, utilizes dry etch process to S1031, etches in source and drain isolated area the shallow slot 205 that the degree of depth is 50 ~ 70nm, and because device is small size device for this reason, channel layer thickness is lower, and deep trench isolation error is too large;
S1032, as shown in figure 2f, utilize the method for CVD, at 750 ~ 850 DEG C, at the silicon dioxide (SiO of surface deposition 50 ~ 70nm 2) 206, fill up in shallow slot 205;
S1033, as shown in Figure 2 g, utilize the method for CVD at the silicon nitride (SiN) 207 of surface deposition 20 ~ 30nm;
S1034, as shown in fig. 2h, utilize CMP method, by the SiO of surface 20 ~ more than 30nm 2remove with SiN;
S1035, as shown in fig. 2i, utilize anisotropic dry etching to etch away the oxide layer of excess surface, form shallow-trench isolation;
The active area of S104, making NMOS:
S1041, as shown in figure 2j, utilize the method for chemical vapor deposition (CVD) at 750 ~ 850 DEG C, surface deposition one deck 20nm silicon nitride (SiN) 208;
S1042, photoetching NMOS active area, utilize the method for ion implantation, and implantation concentration is 1 × 10 12cm -3~ 10 × 10 12cm -3, energy is boron (B) ion of 100eV, and spreads 1 ~ 2 minute at 700 ~ 900 DEG C, and forming doping content is 1 × 10 18cm -3~ 5 × 10 18p trap;
Two inverted trapezoidal groove grids of S105, making NMOS and PMOS:
S1051, as shown in Fig. 2 k, utilize the method for chemical vapor deposition (CVD) at 750 ~ 850 DEG C, surface deposition one deck 20nm silicon nitride (SiN) 209;
S1052, photoetching NMOS gate regions, form litho pattern (as shown in Fig. 2 k), also can the mask plate of shape for this reason.Utilize particle beams lithographic technique, grid appointed area is etched, ideally institute's etched features should be rectangular recess, but due to the effect of etched recesses side wall, the etch rate at groove edge is less, so the figure etched under actual conditions should be inverted trapezoidal, and trapezoidal base angle size is relevant to the beam energy of bombardment, beam energy is larger, then trapezoidal base angle is more close to 90 °, utilize the particle beams for argon (Ar) particle, fixing line is 50mA, bias condition is the particle beams lithographic method of 400 ~ 700V, etch period is 0.5 ~ 1.5 minute, , etching two angles in NMOS gate regions is 75 ~ 85 °, the degree of depth is the inverted trapezoidal groove 210 of 10 ~ 15nm, and two grooves are at a distance of 10nm, groove top width is 5 ~ 8nm, the benefit done like this is: 1, and trapezoidal grid can be equivalent to the accumulation of infinite multiple small stair, and according to edge-crowding effect of current, the current density at step place can increase, thus reduces the current density at raceway groove place, obtains higher puncture voltage to make nmos device, 2, because grid structure is not planar structure, gate capacitance is no longer traditional capacity plate antenna, adds the grid-control ability of device, increases the puncture voltage of nmos device when OFF state, adds the reliability of cmos circuit,
S1053, as illustrated in figure 21, utilize the method for chemical vapor deposition (CVD) at 750 ~ 850 DEG C, surface deposition one deck 20nm silicon nitride (SiN) 211;
S1054, photoetching PMOS gate regions, form litho pattern (as illustrated in figure 21), also can the mask plate of shape for this reason.Utilize particle beams lithographic technique, grid appointed area is etched, ideally institute's etched features should be rectangular recess, but due to the effect of etched recesses side wall, the etch rate at groove edge is less, so the figure etched under actual conditions should be inverted trapezoidal, and trapezoidal base angle size is relevant to the beam energy of bombardment, beam energy is larger, then trapezoidal base angle is more close to 90 °, utilize the particle beams for argon (Ar) particle, fixing line is 50mA, bias condition is the particle beams lithographic method of 400 ~ 700V, etch period is 0.5 ~ 1.5 minute, etching two angles in PMOS gate regions is 75 ~ 85 °, the degree of depth is the inverted trapezoidal groove 212 of 10 ~ 15nm, and two grooves are at a distance of 10nm, groove top width is 5 ~ 8nm, the benefit done like this is: 1, and trapezoidal grid can be equivalent to the accumulation of infinite multiple small stair, and according to edge-crowding effect of current, the current density at step place can increase, thus reduces the current density at raceway groove place, obtains higher puncture voltage to make PMOS device, 2, because grid structure is not planar structure, gate capacitance is no longer traditional capacity plate antenna, adds the grid-control ability of device, increases the puncture voltage of PMOS device when OFF state, adds the reliability of cmos circuit,
S106, making PMOS and NMOS source-drain electrode:
S1061, etch away the SiN barrier layer of excess surface;
S1062, as shown in Fig. 2 m, utilizing the method for ALCVD at 200 ~ 250 DEG C, is the Al of 5 ~ 8nm in surface deposition a layer thickness 2o 3layer 213; The benefit done like this is: the grid-control ability that can improve device, enhances the electrology characteristic of device;
S1063, utilize the method for chemical vapor deposition (CVD) at 750 ~ 850 DEG C, surface deposition one deck 20nmSiN214;
S1064, as shown in Fig. 2 n, etching technics is utilized to etch away the surfaces of active regions assigned address of PMOS and SiN214 and Al of source and drain position 2o 3213;
S1065, employing ion implantation technology, carry out boron (B) to the source-drain area of PMOS and inject, form heavily doped source-drain area 215;
S1066, etch away the SiN barrier layer of excess surface;
S1067, utilize the method for chemical vapor deposition (CVD) at 750 ~ 850 DEG C, surface deposition one deck 20nmSiN216;
S1068, as shown in figure 2o, etching technics is utilized to etch away the surfaces of active regions assigned address of NMOS and SiN216 and Al of source and drain position 2o 3213;
S1069, employing ion implantation technology, carry out phosphorus (P) to the source-drain area of PMOS and inject, form heavily doped source-drain area 217.The SiN barrier layer of eating away excess surface is the N of 570 ~ 600 DEG C in temperature 2environment under, impurity is activated, 1 ~ 2 minute;
The electrode of S107, making PMOS and NMOS;
S1071, as illustrated in figure 2p, utilize the method for CVD at 750 ~ 850 DEG C, at surface deposition one deck 20nmSiN218;
S1072, the SiN218 utilizing etching technics to etch away appointed area form the source-drain area window of PMOS and NMOS;
S1073, as shown in figure 2q, utilizing the method for CVD, is the metal Al layer 219 of 4 ~ 6nm at 400 ~ 450 DEG C of deposition thicknesses; Ohm annealing 25 ~ 40 seconds is carried out at 225 ~ 300 DEG C; Etch away the SiN barrier layer of excess surface; Utilize the method for CVD, at 750 ~ 850 DEG C, at surface deposition one deck 20nmSiN220;
S1074, as shown in Fig. 2 r, utilize etching technics, etch away sections SiN220 forms the gate regions of PMOS and NMOS;
S1075, as shown in Fig. 2 s, utilize the method for CVD, depositing metal Ni221, preparation forms the grid of PMOS and NMOS;
S108, preparation CMOS integrated circuit;
S1081, as shown in Fig. 2 t, utilize etching technics, etch away the SiN barrier layer of excess surface, utilize the method for CVD, at 750 ~ 850 DEG C, in surface deposition layer of sin 222;
S1082, grid at PMOS and NMOS, lithography fair lead on source and drain region;
S1083, metalized
S1084, photoetching lead-in wire, form drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, and finally formed, constituting channel length is the strained Si channel CMOS integrated circuit of 50nm;
In above-described embodiment, the electron mobility of strain Si material is about 1.2 times of Si material, and hole mobility is about 1.3 times of Si material, and strain Si technique has and existing Si process compatible, carrier mobility high, can make CMOS ic core piece performance be improved significantly.
Embodiment three
Refer to Fig. 3, Fig. 3 is the device architecture schematic diagram of another kind based on the strained Si channel inverted trapezoidal grid CMOS integrated device of SOI of the embodiment of the present invention, this strain Si cmos device upwards comprises successively bottom substrate: SOI substrate, N-type SiGe (SiGe) layer of content gradually variational, N-type relaxation SiGe (SiGe) layer, P type strained silicon (Si) layer, the gate oxide that metal contact layer above nmos device and PMOS device source-drain area and the metal oxide below nmos device and PMOS device grid are formed, the metal gates of NMOS and PMOS, and the (not shown)s such as the lead-in wire of interconnection and passivation layer are formed between NMOS and PMOS be separated.Wherein, the grid of nmos device and PMOS device is two inverted trapezoidal groove grids as shown in Figure 3, and its technique is formed by the process preparation in above-described embodiment.Certainly, also comprise the isolated area between NMOS and PMOS, this isolated area is realized by shallow grooved-isolation technique (shallowtrenchisolation is called for short STI) technology.
In sum, apply specific case herein to set forth the principle of the strained Si channel inverted trapezoidal grid CMOS integrated device and preparation method that the present invention is based on SOI and execution mode, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention; all will change in specific embodiments and applications; in sum, this description should not be construed as limitation of the present invention, and protection scope of the present invention should be as the criterion with appended claim.

Claims (8)

1., based on a preparation method for the strained Si channel inverted trapezoidal grid CMOS integrated device of SOI, it is characterized in that, comprise step:
A () chooses SOI substrate;
B () be growing P-type SiGe layer and N-type strained si layer/in described SOI substrate, to form NMOS active area and PMOS active area;
C () adopts etching technics to form isolated groove between described NMOS active area and described PMOS active area;
D () adopts ion implantation technology to form P type trap zone in described NMOS surfaces of active regions;
E () forms NMOS gate regions figure in described NMOS surfaces of active regions photoetching, adopt particle beams etching technics to form the first double trapezoid groove; Form PMOS gate regions figure in described PMOS surfaces of active regions photoetching, adopt particle beams etching technics to form the second double trapezoid groove;
F () forms NMOS gate dielectric material and PMOS gate dielectric material in described NMOS surfaces of active regions and described PMOS surfaces of active regions growth oxide layer;
G () differs from graphics field, described NMOS gate regions in described PMOS surfaces of active regions and etches described PMOS gate dielectric material and adopt ion implantation technology to form PMOS source drain region, differ from graphics field, described NMOS gate regions etch described NMOS gate dielectric material and adopt ion implantation technology to form NMOS source-drain area in described NMOS surfaces of active regions;
H () grows grid material respectively in described first double trapezoid groove surfaces and described second double trapezoid groove surfaces and forms NMOS grid and PMOS grid; And
(i) metalized, and photoetching drain lead, source lead and grid lead, the final strained Si channel inverted trapezoidal grid CMOS integrated device formed based on SOI.
2. preparation method as claimed in claim 1, it is characterized in that, step (b) comprising:
(b1) in described SOI substrate, grow the SiGe layer of N-type content gradually variational;
(b2) in the SiGe layer superficial growth relaxed sige layer of described content gradually variational, in described relaxed sige layer, the concentration of Ge equals the concentration of the Ge at the SiGe layer top of described content gradually variational;
(b3) in described relaxed sige layer superficial growth strained si layer/, to form NMOS active area and PMOS active area.
3. preparation method as claimed in claim 1, it is characterized in that, step (c) comprising:
(c1) photoetching process is utilized to form isolated area figure between described NMOS active area and described PMOS active area;
(c2) utilize etching technics, in described isolated area figure position, etching forms described isolated groove;
(c3) oxide is adopted to fill described isolated groove;
(c4) protective layer is formed at described oxide surface growing nitride;
(c5) utilize CMP (Chemical Mechanical Polishing) process to remove described nitride and remove the growth thickness that thickness is described nitride, or, utilize CMP (Chemical Mechanical Polishing) process to remove described nitride and described oxide and the described nitride of part retained above described isolated groove;
(c6) anisotropic etch process is utilized to etch described oxide, to form described isolated groove.
4. preparation method as claimed in claim 1, it is characterized in that, step (d) comprising:
(d1) on described NMOS surfaces of active regions and table formation first barrier layer, described PMOS source district;
(d2) described first barrier layer of described NMOS surfaces of active regions is etched;
(d3) ion implantation technology is adopted to form described P trap at described NMOS surfaces of active regions implanting p-type ion;
(d4) described first barrier layer is removed.
5. preparation method as claimed in claim 1, it is characterized in that, step (e) comprising:
(e1) the second barrier layer is formed in described NMOS surfaces of active regions and described PMOS surfaces of active regions;
(e2) form described NMOS gate regions figure in the photoetching of described NMOS surfaces of active regions, utilize particle beams etching technics to form described first double trapezoid groove in described NMOS surfaces of active regions in graphics field, described NMOS gate regions;
(e3) described second barrier layer is removed;
(e4) the 3rd barrier layer is formed in described NMOS surfaces of active regions and described PMOS surfaces of active regions;
(e5) form described PMOS gate regions figure in the photoetching of described PMOS surfaces of active regions, utilize particle beams etching technics to form described second double trapezoid groove in described PMOS surfaces of active regions in graphics field, described PMOS gate regions;
(e6) described 3rd barrier layer is removed.
6. preparation method as claimed in claim 5, it is characterized in that, described particle beams etching technics is: adopt argon (Ar) particle as the particle beams, fixing line is 50mA, and bias condition is 400 ~ 700V.
7. preparation method as claimed in claim 1, it is characterized in that, described gate dielectric material is Al 2o 3or HfO 2, described grid material is metal.
8., based on a strained Si channel inverted trapezoidal grid CMOS integrated device of SOI, it is characterized in that, obtained by the method such as according to any one of claim 1-7.
CN201510540303.7A 2015-08-28 2015-08-28 SOI-based strained-Si-channel inverted-trapezoid-grid CMOS integrated device and preparation method thereof Pending CN105206583A (en)

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