CN104966716B - Different channel CMOS integrated device and preparation method thereof - Google Patents
Different channel CMOS integrated device and preparation method thereof Download PDFInfo
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- CN104966716B CN104966716B CN201510394327.6A CN201510394327A CN104966716B CN 104966716 B CN104966716 B CN 104966716B CN 201510394327 A CN201510394327 A CN 201510394327A CN 104966716 B CN104966716 B CN 104966716B
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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Abstract
The present invention relates to a kind of different channel CMOS integrated device and preparation method thereof, the preparation method includes:Choose SOI substrate；Continuous growing P-type strained ge layer and p-type strained si layer/on soi substrates, to form the channel layer of PMOS channel layer and NMOS respectively；Isolated groove is formed using etching technics on p-type strained si layer/surface, NMOS active areas and PMOS active areas are formed with separation；The strained silicon layer of PMOS surfaces of active regions is etched, and N-type ion is injected into PMOS active areas；PMOS source drain region is formed in PMOS active area specified location implanting p-type ion, NMOS source-drain areas are formed in NMOS active areas specified location injection N-type ion；PMOS grids are formed in PMOS surfaces of active regions and different from source-drain area opening position；NMOS gate is formed in NMOS surfaces of active regions and different from source-drain area opening position；Metalized, and photoetching drain lead, source lead and grid lead, ultimately form different channel CMOS integrated device.The embodiment of the present invention realizes the preparation of the different channel CMOS device of high-performance.
Description
Technical field
The invention belongs to semiconductor integrated circuit technical field, more particularly to a kind of different channel CMOS integrated device and its system
Preparation Method.
Background technology
New technology revolution is also known as modern technologies revolution, and also it is referred to as the third time skill after steam engine, electric power by someone
Art revolution.Letter using microelectric technique, electronic computer, laser, fiber optic communication, satellite communication and remote sensing technology as main contents
Breath technology turns into the frontier technology of new technology revolution.New technology revolution results from 1940's mid-term, and it is first in west
Developed capitalist countries rises, and is progressively radiated to other countries and area, until have swepting the globe, it is accompanied by contemporary science
The form of technology grows up, and extend to the every field of science and technology.
In place of " Moore's Law " that is had an immense impact on to semiconductor industry development：Number of transistors on IC chip
Mesh, double within about every 18 months, performance is also doubled.Over more than 40 years, world semiconductor industry is continuous according to this law all the time
Ground develops.But with the continuous reduction of device feature size, after nano-scale, the hair of microelectric technique
Exhibition increasingly approaches the limit of material, technology and device, is faced with huge challenge.When device feature size narrow down to 65nm with
Afterwards, the influence of the short channel effect in nano-scale device, high-field effect, quantum effect, parasitic parameter, technological parameter error etc. is asked
The influence inscribed to performances such as device Leakage Current, subthreshold behavior, ON state/off-state currents is more and more prominent, circuit speed and power consumption
Contradiction also will be more serious.
In order to solve the above problems, new material, new technology and new technology are employed, but effect is not very good.Such as：
Although tunnel-through diode current on/off ratio is very high, cost of manufacture is high, and ON state current is small；Grapheme material carrier has high
Mobility, but energy gap problem is never addressed well.It is leakage current that FinFET, which can effectively reduce,
But complex process and lifting effect it is limited.And strain Si material can effectively lift device performance and work with strain Ge materials
Skill easily realizes relatively, so as to so that CMOS ic cores piece performance be improved significantly.Therefore, a kind of high property how is made
Can CMOS integrated devices just become and its important.
The content of the invention
Therefore, to solve technological deficiency and deficiency existing for prior art, the present invention proposes that a kind of different channel CMOS integrates
Device and preparation method thereof.
Specifically, the preparation method for a kind of different channel CMOS integrated device that the embodiment of the present invention proposes, including：
(a) SOI substrate is chosen；
(b) continuous growing P-type strained ge layer and p-type strained si layer/in the SOI substrate, to form PMOS ditch respectively
The channel layer of channel layer and NMOS；
(c) isolated groove is formed using etching technics on the p-type strained si layer/surface, it is active to form NMOS with separation
Area and PMOS active areas；
(d) etch the strained silicon layer of the PMOS surfaces of active regions, and inject into the PMOS active areas N-type from
Son；
(e) PMOS source drain region is formed in the PMOS active areas specified location implanting p-type ion, it is active in the NMOS
Area's specified location injection N-type ion forms NMOS source-drain areas；
(f) PMOS grids are formed in the PMOS surfaces of active regions and different from source-drain area opening position；It is active in the NMOS
Area surface and different from source-drain area opening position formed NMOS gate；And
(g) metalized, and photoetching drain lead, source lead and grid lead, different channel CMOS collection is ultimately formed
Into device.
In addition, a kind of different channel CMOS integrated device that another embodiment of the present invention proposes, by the different ditch of above-described embodiment
The preparation method of road CMOS integrated devices is made.
From the foregoing, it will be observed that the embodiment of the present invention has the following advantages that：
1. the material that PMOS of the present invention is utilized is compressive strain Ge materials, improved relative to traditional Si material hole mobility
Several times, so as to improve the driving current of cmos device and frequency characteristic；
2. the material that NMOS of the present invention is utilized is tensile strain Si materials, have very relative to traditional Si material electronicses mobility
Big raising, so as to improve the driving current of cmos device and frequency characteristic；
3. cmos device prepared by the present invention has used different channel materials, strain Ge materials and strain have been given full play to
The characteristic of Si materials；
4. due to process proposed by the invention and existing Si integrated circuit processings process compatible, therefore, Ke Yi
In the case of without any fund of addition and equipment investment, different channel CMOS device and integrated circuit are prepared, the country can be achieved
Integrated circuit processing ability is substantially improved.
By the detailed description below with reference to accompanying drawing, other side of the invention and feature become obvious.But it should know
Road, the accompanying drawing is only the purpose design explained, not as the restriction of the scope of the present invention, because it should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to which scale accompanying drawing, they only try hard to concept
Ground illustrates structure and flow described herein.
Brief description of the drawings
Below in conjunction with accompanying drawing, the embodiment of the present invention is described in detail.
Fig. 1 is a kind of preparation method flow chart of different channel CMOS integrated device of the embodiment of the present invention；
Fig. 2 a- Fig. 2 y are a kind of preparation method schematic diagram of different channel CMOS integrated device of the embodiment of the present invention；
Fig. 3 is the preparation method flow chart of another different channel CMOS integrated device of the embodiment of the present invention；
Fig. 4 is a kind of device architecture schematic diagram of different channel CMOS integrated device of the embodiment of the present invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
Embodiment one
Fig. 1 please be participate in, Fig. 1 is a kind of preparation method flow chart of different channel CMOS integrated device of the embodiment of the present invention,
The preparation method comprises the following steps：
(a) SOI substrate is chosen；
(b) continuous growing P-type strained ge layer and p-type strained si layer/on soi substrates, to form PMOS channel layer respectively
With NMOS channel layer；
(c) on p-type strained si layer/surface using etching technics formed isolated groove, with separation formed NMOS active areas and
PMOS active areas；
(d) strained si layer/of PMOS surfaces of active regions is etched, and N-type ion is injected into PMOS active areas；
(e) PMOS source drain region is formed in PMOS active area specified location implanting p-type ion, in NMOS active area specific bits
Put place's injection N-type ion and form NMOS source-drain areas；
(f) PMOS grids are formed in PMOS surfaces of active regions and different from source-drain area opening position；In NMOS surfaces of active regions and
NMOS gate is formed different from source-drain area opening position；And
(g) metalized, and photoetching drain lead, source lead and grid lead, different channel CMOS collection is ultimately formed
Into device.
Specifically, before step (b), in addition to：
(x1) SiGe epitaxial layers are formed on soi substrates；
(x2) intrinsic layer si layer is formed on SiGe epitaxial layers；
(x3) SOI substrate, SiGe epitaxial layers and intrinsic layer si layer are aoxidized using dry-oxygen oxidation technique, and at annealing
Reason, form concentration SiGe layer.
Specifically, step (b) includes：
(b1) the growing P-type strained ge layer in concentration SiGe layer, and it is that compression strains Ge to strain Ge；
(b2) the growing P-type strained si layer/in p-type strained ge layer, and strain Si is tensile-stressed strain Si.
Specifically, step (c) includes：
(c1) isolated area figure is formed on p-type strained si layer/surface using photoetching process；
(c2) etching technics is utilized, etches to form isolation channel in isolated area figure position；
(c3) chemical vapor deposition method is utilized, isolation channel is filled using oxide, forms the isolation of CMOS integrated devices
Area.
Specifically, include in step (d)：
(d1) the first barrier layer is formed in NMOS active areas and PMOS surfaces of active regions；
(d2) the first barrier layer and the p-type strained si layer/of PMOS active regions are etched away using etching technics；
(d3) ion implantation technology is utilized, N-type ion is injected in PMOS active areas.
Specifically, before step (e), in addition to：
(y1) Al is formed in NMOS surfaces of active regions and PMOS surfaces of active regions2O3Or Cr2O3Layer, as NMOS gate oxidations
Layer and PMOS gate oxides；
(y2) the second barrier layer is formed in NMOS gate oxides and PMOS gate oxides surface.
Specifically, step (e) includes：
(e1) the second barrier layer and the gate oxide of PMOS active region designated areas are etched away using etching technics；
(e2) ion implantation technology is utilized, implanting p-type ion is to form PMOS source drain region in PMOS active areas；
(e3) the second barrier layer and the gate oxide of NMOS active region designated areas are etched away using etching technics；
(e4) ion implantation technology is utilized, N-type ion is injected in NMOS active areas to form NMOS source-drain areas.
Specifically, before step (f), in addition to：
(z1) the 3rd barrier layer is formed in NMOS active areas and PMOS surfaces of active regions；
(z2) etch away specified location above NMOS source-drain areas and PMOS source drain region using etching technics the 3rd stops
Layer, to form NMOS source and drain window and PMOS source ornamental perforated window mouth；
(z3) chemical vapor deposition method is utilized, source is formed in NMOS source and drain window and PMOS source drain region window deposition metal
Drain contacts.
Specifically, step (f) includes：
(f1) the 4th barrier layer is formed in NMOS active areas and PMOS surfaces of active regions；
(f2) etch the 4th barrier layer using etching technics and form NMOS gate window and PMOS gate windows；
(f3) chemical vapor deposition method is utilized, metal is deposited to be formed in NMOS gate window and PMOS gate windows
NMOS gate and PMOS grids.
The embodiment of the present invention has the following advantages that：
1. the material that PMOS of the present invention is utilized is compressive strain Ge materials, improved relative to traditional Si material hole mobility
Several times, so as to improve the driving current of cmos device and frequency characteristic；
2. the material that NMOS of the present invention is utilized is tensile strain Si materials, have very relative to traditional Si material electronicses mobility
Big raising, so as to improve the driving current of cmos device and frequency characteristic；
3. cmos device prepared by the present invention has used different channel materials, strain Ge materials and strain have been given full play to
The characteristic of Si materials；
4. due to process proposed by the invention and existing Si integrated circuit processings process compatible, therefore, Ke Yi
In the case of without any fund of addition and equipment investment, different channel CMOS device and integrated circuit are prepared, the country can be achieved
Integrated circuit processing ability is substantially improved.
Embodiment two
Refer to a kind of preparation for different channel CMOS integrated device that Fig. 2 a- Fig. 2 y, Fig. 2 a- Fig. 2 y are the embodiment of the present invention
Method schematic diagram, on the basis of above-described embodiment one, it is to prepare different channel CMOS integrated device of the conducting channel as 20nm
Example is described in detail, and comprises the following steps that：
S101, substrate are chosen.
As shown in Figure 2 a, choose and be doped to p-type, concentration is 1 × 1016cm-3~3 × 1016cm-3Top layer silicon (Si) thickness is
20~30nm, oxidated layer thickness are the silicon (Silicon-On-Insulator, abbreviation SOI) in 150~200nm dielectric substrate
Substrate slice 201 is original material.
S102, outer layer growth.
As shown in Figure 2 b, ultra-high vacuum CVD (Ultrahigh vacuum CVD, abbreviation UHVCVD) is utilized
Method, grow thick P-type silicon germanium (SiGe) epitaxial layer 202 of one layer of 70~80nm on soi substrates, doping concentration is 1 ×
1016cm-3, germanium (Ge) component is 0.1.
S103, intrinsic layer growth.As shown in Figure 2 c, using UHVCVD method, a thickness is grown on SiGe epitaxial layers
Spend intrinsic silicon (Si) layer 203 for 10~15nm.
It is prepared by S104, active area.Comprise the following steps that：
S1041, utilize standard cleaning technique cleaning intrinsic silicon (Si) layer 203 surface；
S1042, in the quartz ampoule of temperature-controllable, intrinsic silicon (Si) layer/SiGe (SiGe)/SOI stacked structures is carried out
Dry-oxygen oxidation, temperature are 1150~1200 DEG C, and the time is 150~180 minutes；
S1043, as shown in Figure 2 d, in nitrogen (N2) annealed in atmosphere, annealing temperature is gradually decreased to 900 by 1150 DEG C
DEG C, the time is 80~90 minutes, to obtain the SiGe layer 204 that Ge components are about 40%；Carry out dry-oxygen oxidation, temperature be 800~
900 DEG C, the time is 180~240 minutes；
S1044, as shown in Figure 2 e, in N2To be annealed in atmosphere, annealing temperature is 900 DEG C, and the time is 50~60 minutes,
To obtain the SiGe layer 205 that Ge components are about 70%~80%.
Above-mentioned steps S1041~S1044, which is advantageous in that, can effectively reduce dislocation, therefore strains in Ge channel materials and lack
Sunken density is low, and the different channel CMOS device performance of preparation is good.
S1045, the method using CVD, the p-type strained Germanium that a layer thickness is 10~20nm is grown in SiGe layer 205
(Ge) layer 206, doping concentration are 1 × 1017~3 × 1017cm-3, strain germanium material is compared to common silicon materials, carrier mobility
Rate has great lifting.
Using CVD method, p-type strained silicon (Si) layer 207 that a layer thickness is 10~20nm is grown in strained ge layer,
Doping concentration is 1 × 1017~3 × 1017cm-3, tensile strain silicon materials have larger compared to common silicon materials, electron transfer
Lifting.
S105, isolated area preparation：
S1051, as shown in figure 2f, photoetching shallow trench isolation region, using dry etch process, depth is etched in source and drain isolated area
The shallow slot 208 for 30~50nm is spent, because this device is small size device, channel layer thickness is relatively low, and deep trench isolation error is too big；
S1052, as shown in Figure 2 g, using CVD method, at 750~850 DEG C, the two of 30~50nm of surface deposition
Silica (SiO2) 209, it will be filled up in shallow slot；
S1053, as shown in fig. 2h, using CVD method 20~30nm of surface deposition silicon nitride (SiN) 210；
S1054, as shown in fig. 2i, using CMP method, by 20~more than 30nm of surface SiO2Removed with SiN；
S1055, as shown in figure 2j, the oxide layer of excess surface is etched away using anisotropic dry etching, formed shallow
Groove is isolated；
S106, the source-drain electrode for making PMOS and NMOS：
S1061, as shown in Fig. 2 k, using CVD method 20~30nm of surface deposition silicon nitride (SiN) 211；
S1062, as illustrated in figure 21, PMOS surface specified location is etched away i.e. at PMOS active areas using etching technics
SiN 211 and strained si layer/207, using ion implantation technology, phosphorus (P) injection, doping concentration 1 are carried out to PMOS active area
×1018~1 × 1019cm-3；
S1063, as shown in Fig. 2 m, etch away NMOS surface specified location i.e. at NMOS active areas using etching technics
SiN 211；
S1064, as shown in Fig. 2 n, using ALCVD method at 200~250 DEG C, surface deposition a layer thickness be 5~
8nm Al2O3212；This have the advantage that：The grid-control ability of device can be improved, enhances the electrology characteristic of device；
S1065, as shown in figure 2o, using CVD method at 750~850 DEG C, one layer of 20nm SiN of surface deposition
213；
S1066, as illustrated in figure 2p, PMOS surfaces of active regions specified location i.e. source and drain opening position is etched away using etching technics
SiN 213 and Al2O3212；
S1067, using ion implantation technology, boron (B) injection is carried out to PMOS source-drain area, heavily doped region 214 is formed, mixes
Miscellaneous concentration is 1 × 1019~5 × 1019cm-3；
S1069, etch away unnecessary SiN barrier layers；
S1070, as shown in figure 2q, using CVD method at 750~850 DEG C, one layer of 20nm SiN of surface deposition
215；
S1071, as shown in Fig. 2 r, etch away NMOS surfaces of active regions specified location i.e. source and drain opening position using etching technics
SiN 213 and Al2O3212；
S1072, using ion implantation technology, phosphorus (P) injection is carried out to NMOS source-drain area, forms heavily doped region 216；
S1073, the SiN barrier layers for etching away excess surface；
S108, the electrode for making PMOS and NMOS；
S1081, as shown in Fig. 2 s, using CVD method at 750~850 DEG C, one layer of 20nm SiN of surface deposition
217；
S1082, as shown in Fig. 2 t, the SiN 217 that designated area is etched away using etching technics forms PMOS and NMOS
Source-drain area window；
S1083, as shown in Fig. 2 u, using CVD method, in the W metal layer that 400~450 DEG C of deposition thicknesses are 4~6nm
218；Ohm is carried out at 225~300 DEG C to anneal 25~40 seconds；
S1084, etch away unnecessary SiN barrier layers；
S1085, as shown in Fig. 2 v, using CVD method at 750~850 DEG C, one layer of 20nm SiN of surface deposition
219；
S1086, as shown in Fig. 2 w, the SiN 219 that designated area is etched away using etching technics forms PMOS and NMOS
Gate window；
S1087, as shown in Fig. 2 x, using CVD method, deposit metal Al 220, prepare PMOS and NMOS grid；
S1088, etch away unnecessary SiN barrier layers；
S109, prepare CMOS integrated circuits；
S1091, as shown in Fig. 2 y, using etching technics, etch away the SiN barrier layers of excess surface, utilize CVD side
Method, at 750~850 DEG C, in surface deposition layer of sin 221；
S1082, the grid in PMOS and NMOS, lithography fair lead on source and drain region；
S1083, metalized；
S1084, photoetching leads, drain metal lead, source metal lead and gate metal lead are formed, is ultimately formed,
The different channel CMOS of the strain Ge channel PMOSs that constituting channel length is 20nm and strained Si channel NMOS compositions.
The preparation method of the different channel CMOS integrated device of the embodiment of the present invention, by being answered on soi substrates using enhanced
Become germanium (Ge) nmos device and form CMOS integrated devices, i.e., formed by growing N-type strained Germanium (Ge) layer on soi substrates
The active area of nmos device in CMOS integrated devices, and high performance strain is realized as grid using high work function material
Germanium (Ge) cmos device.
Embodiment three
Fig. 3 is referred to, Fig. 3 is the preparation method flow of another different channel CMOS integrated device of the embodiment of the present invention
Figure, on the basis of above-described embodiment, prepare strain Ge channel PMOSs and strained Si channel NMOS groups that conducting channel is 65nm
Into CMOS integrated devices, comprise the following steps that：
Step 1：Ge components are the preparation of 0.6 SiGe layer：
Choose p-type and be doped to 1 × 1016cm-3Top layer Si thickness is 20nm, SiO2The SOI substrate piece that thickness is 150nm is
Original material；
Using high vacuum chemical vapor deposition (UHVCVD) method, in the thick p-types of one layer of 60nm of Grown
SiGe epitaxial layers, doping concentration are 1 × 1016cm-3, Ge components are 0.1；
Using high vacuum chemical vapor deposition (UHVCVD) method, growth a layer thickness is on SiGe epitaxial layers
10nm intrinsic Si cap layers；
Utilize standard cleaning technique cleaning Si cap layers surface；
In the quartz ampoule of temperature-controllable, Si cap layers/SiGe layer/SOI stacked structures are subjected to dry-oxygen oxidation, temperature is
1150 DEG C, the time is 180 minutes；
To be annealed in N2 atmosphere, annealing temperature is gradually decreased to 900 DEG C by 1150 DEG C, and the time is 90 minutes, with
The SiGe layer for being about 40% to Ge components；
Dry-oxygen oxidation is carried out, temperature is 900 DEG C, and the time is 30 minutes；
Annealed in N2 atmosphere, annealing temperature is 900 DEG C, and the time is 80 minutes, is about 0.6 to obtain Ge components
SiGe layer；
, should using p-type of the method for chemical vapor deposition (CVD) in 10~20nm of surface deposition at 300~400 DEG C
Become Ge layers, doping concentration is 1~10 × 1017cm-3；
, should using p-type of the method for chemical vapor deposition (CVD) in 15~25nm of surface deposition at 500~700 DEG C
Become Si layers, doping concentration is 1~10 × 1017cm-3；
Step 2：The preparation of isolated area
Photoetching shallow trench isolation region, using dry etch process, the shallow slot that depth is 70nm is etched in source and drain isolated area；
Using the method for chemical vapor deposition (CVD) at 850 DEG C, surface deposition 70nm SiO2, will be filled out in shallow slot
It is full；
Using the method for chemical vapor deposition (CVD) at 850 DEG C, surface deposition 20nm SiN；
Using chemically mechanical polishing (CMP) method, by SiO more than surface 20nm2Removed with SiN；
The oxide layer of excess surface is etched away using anisotropic dry etching, forms shallow-trench isolation；
Step 3：PMOS and NMOS formation：
It is 10nm in surface deposition a layer thickness using the method for atomic layer chemical vapour deposition (ALCVD) at 400 DEG C
HfO2Layer；
Using the method for chemical vapor deposition (CVD) at 850 DEG C, surface deposition layer of sin, PMOS source is etched away
The SiN and HfO in drain region2；
Using ion implantation technology, boron injection is carried out to PMOS source-drain area, forms the source-drain area of heavy doping；
Etch away the SiN barrier layers of excess surface；
Using the method for chemical vapor deposition (CVD) at 850 DEG C, surface deposition layer of sin；
Etch away the SiN and HfO of NMOS source-drain area2, form source-drain area window；
Using ion implantation technology, phosphorus injection is carried out to NMOS source-drain area, forms the source-drain area of heavy doping；
The SiN barrier layers of eating away excess surface；
In the N that temperature is 600 DEG C2In the environment of, enter line activating to impurity, 60 seconds；
Etch away sections SiN forms NMOS and PMOS source-drain area window, deposits W metal；
Ohm is annealed 30 seconds at 300 DEG C；
Etch away the SiN barrier layers of excess surface；
Using the method for chemical vapor deposition (CVD) at 850 DEG C, surface deposition layer of sin, etch away sections SiN
Form PMOS and NMOS gate regions；
Metal Al is deposited, prepares PMOS and NMOS gate；
Step 4：Form CMOS integrated circuit steps：
Using chemical vapor deposition (CVD) method, at 850 DEG C, in surface deposition layer of sin；
In grid, lithography fair lead on source and drain region；
Metallization；
Splash-proofing sputtering metal, photoetching lead form drain electrode, source electrode and gate metal lead, and constituting channel length is 65nm's
CMOS integrated circuits.
Example IV
Fig. 4 is referred to, Fig. 4 is a kind of device architecture schematic diagram of different channel CMOS integrated device of the embodiment of the present invention,
The different channel CMOS device includes strain Si NMOS and strain Ge PMOS, and strain Si NMOS includes successively from below to up：
SOI substrate, concentration SiGe layer, p-type strained ge layer, p-type strained si layer/, the source and drain contact layer positioned at same layer and gate oxide with
And the NMOS gate on gate oxide；Strain Ge PMOS include successively from below to up：SOI substrate, concentration SiGe layer, p-type should
Become Ge layers, source and drain contact layer and gate oxide positioned at same layer and the PMOS grids on gate oxide, in addition, the different ditch
Road CMOS is additionally included in the (not shown)s such as the lead that interconnection is formed between the NMOS of separation and PMOS and passivation layer, certainly,
Also include the isolated area between NMOS and PMOS, the isolated area is by shallow grooved-isolation technique (shallow trench
Isolation, abbreviation STI) technology realization.
In summary, specific case used herein is to the different channel CMOS integrated device of the present invention and preparation method thereof
Principle and embodiment are set forth, and the explanation of above example is only intended to help the method and its core for understanding the present invention
Thought；Meanwhile for those of ordinary skill in the art, according to the thought of the present invention, in embodiment and application
Upper there will be changes, in summary, this specification content should not be construed as limiting the invention, protection model of the invention
Enclosing should be defined by appended claim.
Claims (8)
1. a kind of preparation method of different channel CMOS integrated device, it is characterised in that including step：
(a) SOI substrate is chosen；
The growing P-type SiGe epitaxial layers in the SOI substrate, doping concentration are 1 × 1016cm-3, Ge components are 0.1；
Using UHVCVD methods, intrinsic layer si layer is grown on the SiGe epitaxial layers；
(b) the intrinsic layer si layer surface is cleaned using standard cleaning technique；
In the quartz ampoule of temperature-controllable, intrinsic layer si layer/SiGe/SOI stacked structures is subjected to dry-oxygen oxidation, temperature is 1150~
1200 DEG C, the time is 150~180 minutes；
In N2Annealed in atmosphere, annealing temperature is gradually decreased to 900 DEG C by 1150 DEG C, and the time is 80~90 minutes, to obtain Ge
Component is 40% the first SiGe layer；Dry-oxygen oxidation is carried out, temperature is 800~900 DEG C, and the time is 180~240 minutes；In N2
Annealed in atmosphere, annealing temperature is 900 DEG C, and the time is 50~60 minutes, obtains second that Ge components are 70%~80%
SiGe layer, to form concentration SiGe layer；
Growth forms doping concentration as 1 × 10 in the concentration SiGe layer17~3 × 1017cm-3P-type compressive strain Ge layers with shape
Into PMOS channel layer；Growth forms doping concentration as 1 × 10 on the p-type compressive strain Ge layers17~3 × 1017cm-3P-type
Tensile-strained si layer is to form NMOS channel layer；
(c) isolated groove is formed using etching technics on the p-type tensile-strained si layer surface, NMOS active areas is formed with separation
With PMOS active areas；
(d) strained silicon layer of the PMOS surfaces of active regions is etched, and N-type ion is injected into the PMOS active areas；
(e) PMOS source drain region is formed in the PMOS active areas specified location implanting p-type ion, referred in the NMOS active areas
Determine opening position injection N-type ion and form NMOS source-drain areas；
(f) PMOS grids are formed in the PMOS surfaces of active regions and different from source-drain area opening position；In the NMOS active areas table
Face and different from source-drain area opening position formed NMOS gate；And
(g) metalized, and photoetching drain lead, source lead and grid lead, different channel CMOS integrator is ultimately formed
Part.
2. preparation method as claimed in claim 1, it is characterised in that step (c) includes：
(c1) isolated area figure is formed on the p-type tensile-strained si layer surface using photoetching process；
(c2) etching technics is utilized, etches to form isolation channel in the isolated area figure position；
(c3) chemical vapor deposition method is utilized, the isolation channel is filled using oxide, forms the CMOS integrated devices
Isolated area.
3. preparation method as claimed in claim 1, it is characterised in that step (d) includes：
(d1) the first barrier layer is formed in the NMOS active areas and the PMOS surfaces of active regions；
(d2) first barrier layer of the PMOS active regions and the p-type tensile strain Si are etched away using etching technics
Layer；
(d3) ion implantation technology is utilized, N-type ion is injected in the PMOS active areas.
4. preparation method as claimed in claim 1, it is characterised in that before step (e), in addition to：
(y1) Al is formed in the NMOS surfaces of active regions and the PMOS surfaces of active regions2O3Or Cr2O3Layer, as NMOS grid oxygens
Change layer and PMOS gate oxides；
(y2) the second barrier layer is formed in the NMOS gate oxides and the PMOS gate oxides surface.
5. preparation method as claimed in claim 4, it is characterised in that step (e), including：
(e1) second barrier layer of the PMOS active regions designated area and the grid are etched away using etching technics
Oxide layer；
(e2) ion implantation technology is utilized, implanting p-type ion is to form the PMOS source drain region in the PMOS active areas；
(e3) second barrier layer of the NMOS active regions designated area and the grid are etched away using etching technics
Oxide layer；
(e4) ion implantation technology is utilized, N-type ion is injected in the NMOS active areas to form the NMOS source-drain areas.
6. preparation method as claimed in claim 1, it is characterised in that before step (f), in addition to：
(z1) the 3rd barrier layer is formed in the NMOS active areas and the PMOS surfaces of active regions；
(z2) etched away using etching technics above the NMOS source-drain areas and the PMOS source drain region described in specified location
3rd barrier layer, to form NMOS source and drain window and PMOS source ornamental perforated window mouth；
(z3) chemical vapor deposition method is utilized, in the NMOS source and drain window and the PMOS source drain region window deposition metal shape
Into source and drain contact layer.
7. preparation method as claimed in claim 1, it is characterised in that step (f) includes：
(f1) the 4th barrier layer is formed in the NMOS active areas and the PMOS surfaces of active regions；
(f2) etch the 4th barrier layer using etching technics and form NMOS gate window and PMOS gate windows；
(f3) chemical vapor deposition method is utilized, metal is deposited with shape in the NMOS gate window and the PMOS gate windows
Into the NMOS gate and the PMOS grids.
8. a kind of different channel CMOS integrated device, it is characterised in that as the method system as any one of claim 1-7
.
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| CN1973374A (en) * | 2004-06-10 | 2007-05-30 | 飞思卡尔半导体公司 | Semiconductor device with multiple semiconductor layers |
| CN102446853A (en) * | 2010-09-30 | 2012-05-09 | 中国科学院微电子研究所 | Strained semiconductor channel formation method and semiconductor device |
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| CN102446853A (en) * | 2010-09-30 | 2012-05-09 | 中国科学院微电子研究所 | Strained semiconductor channel formation method and semiconductor device |
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