CN105190585B - 基于操作速度的数据总线反相(dbi)编码 - Google Patents
基于操作速度的数据总线反相(dbi)编码 Download PDFInfo
- Publication number
- CN105190585B CN105190585B CN201480012359.9A CN201480012359A CN105190585B CN 105190585 B CN105190585 B CN 105190585B CN 201480012359 A CN201480012359 A CN 201480012359A CN 105190585 B CN105190585 B CN 105190585B
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- CN
- China
- Prior art keywords
- data bus
- bus inversion
- data
- dbi
- algorithm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/287—Multiplexed DMA
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Mobile Radio Communication Systems (AREA)
- Communication Control (AREA)
- Information Transfer Systems (AREA)
- Dc Digital Transmission (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361791865P | 2013-03-15 | 2013-03-15 | |
| US61/791,865 | 2013-03-15 | ||
| US14/202,783 US9529749B2 (en) | 2013-03-15 | 2014-03-10 | Data bus inversion (DBI) encoding based on the speed of operation |
| US14/202,783 | 2014-03-10 | ||
| PCT/US2014/023508 WO2014150529A1 (en) | 2013-03-15 | 2014-03-11 | Data bus inversion (dbi) encoding based on the speed of operation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105190585A CN105190585A (zh) | 2015-12-23 |
| CN105190585B true CN105190585B (zh) | 2018-04-13 |
Family
ID=51533777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480012359.9A Active CN105190585B (zh) | 2013-03-15 | 2014-03-11 | 基于操作速度的数据总线反相(dbi)编码 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US9529749B2 (enExample) |
| EP (1) | EP2972927B1 (enExample) |
| JP (1) | JP6130043B2 (enExample) |
| KR (1) | KR101759816B1 (enExample) |
| CN (1) | CN105190585B (enExample) |
| WO (1) | WO2014150529A1 (enExample) |
Families Citing this family (36)
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| US9529749B2 (en) | 2013-03-15 | 2016-12-27 | Qualcomm Incorporated | Data bus inversion (DBI) encoding based on the speed of operation |
| US9252802B2 (en) * | 2014-02-07 | 2016-02-02 | Qualcomm Incorporated | Encoding for partitioned data bus |
| US9614703B2 (en) * | 2015-03-30 | 2017-04-04 | Qualcomm Incorporated | Circuits and methods providing high-speed data link with equalizer |
| US10345836B1 (en) | 2015-08-21 | 2019-07-09 | Rambus Inc. | Bidirectional signaling with asymmetric termination |
| CN107131921B (zh) * | 2016-02-26 | 2020-12-11 | 高准公司 | 用于计量电子器件的低功率模式 |
| US10243916B2 (en) | 2016-04-07 | 2019-03-26 | Cisco Technology, Inc. | Control plane based technique for handling multi-destination traffic in overlay networks |
| US9922686B2 (en) | 2016-05-19 | 2018-03-20 | Micron Technology, Inc. | Apparatuses and methods for performing intra-module databus inversion operations |
| US10008287B2 (en) | 2016-07-22 | 2018-06-26 | Micron Technology, Inc. | Shared error detection and correction memory |
| US10373657B2 (en) * | 2016-08-10 | 2019-08-06 | Micron Technology, Inc. | Semiconductor layered device with data bus |
| US10126979B2 (en) | 2016-10-04 | 2018-11-13 | Qualcomm Incorporated | Bus encoding using metadata |
| US11323298B2 (en) * | 2016-10-28 | 2022-05-03 | Telefonaktiebolaget Lm Ericsson (Publ) | DBI protection for data link |
| KR20180057028A (ko) | 2016-11-21 | 2018-05-30 | 에스케이하이닉스 주식회사 | 데이터 반전 회로 |
| WO2018127764A1 (en) * | 2017-01-06 | 2018-07-12 | Telefonaktiebolaget Lm Ericsson (Publ) | Explicit configuration of paging and control channel in system information |
| US10146719B2 (en) * | 2017-03-24 | 2018-12-04 | Micron Technology, Inc. | Semiconductor layered device with data bus |
| KR20190029227A (ko) * | 2017-09-12 | 2019-03-20 | 에스케이하이닉스 주식회사 | 데이터 전송 회로, 이를 이용하는 반도체 장치 및 반도체 시스템 |
| US10599606B2 (en) | 2018-03-29 | 2020-03-24 | Nvidia Corp. | 424 encoding schemes to reduce coupling and power noise on PAM-4 data buses |
| US11159153B2 (en) | 2018-03-29 | 2021-10-26 | Nvidia Corp. | Data bus inversion (DBI) on pulse amplitude modulation (PAM) and reducing coupling and power noise on PAM-4 I/O |
| US11966348B2 (en) | 2019-01-28 | 2024-04-23 | Nvidia Corp. | Reducing coupling and power noise on PAM-4 I/O interface |
| US10657094B2 (en) | 2018-03-29 | 2020-05-19 | Nvidia Corp. | Relaxed 433 encoding to reduce coupling and power noise on PAM-4 data buses |
| US10664432B2 (en) | 2018-05-23 | 2020-05-26 | Micron Technology, Inc. | Semiconductor layered device with data bus inversion |
| US10585817B2 (en) | 2018-05-29 | 2020-03-10 | Seagate Technology Llc | Method of signal integrity and power integrity analysis for address bus |
| US10623200B2 (en) | 2018-07-20 | 2020-04-14 | Nvidia Corp. | Bus-invert coding with restricted hamming distance for multi-byte interfaces |
| US10964702B2 (en) | 2018-10-17 | 2021-03-30 | Micron Technology, Inc. | Semiconductor device with first-in-first-out circuit |
| US10861508B1 (en) | 2019-11-11 | 2020-12-08 | Sandisk Technologies Llc | Transmitting DBI over strobe in nonvolatile memory |
| KR20210076606A (ko) | 2019-12-16 | 2021-06-24 | 삼성전자주식회사 | SoC, 메모리 장치, 전자 장치 및 전자 장치의 데이터 저장 방법 |
| KR102888450B1 (ko) * | 2020-06-02 | 2025-11-18 | 삼성전자 주식회사 | 메모리 장치 및 이를 포함하는 메모리 시스템 |
| US11756592B2 (en) | 2020-09-29 | 2023-09-12 | Samsung Electronics Co., Ltd. | Memory device supporting DBI interface and operating method of memory device |
| US11237729B1 (en) | 2020-10-13 | 2022-02-01 | Sandisk Technologies Llc | Fast bus inversion for non-volatile memory |
| US12347508B2 (en) | 2021-02-12 | 2025-07-01 | Nvidia Corp. | Error detection pin encoding scheme to avoid maximum transitions and further improve signal integrity on high speed graphic memory interfaces |
| US11720516B2 (en) | 2021-08-15 | 2023-08-08 | Apple Inc. | Methods for data bus inversion |
| US11749374B1 (en) * | 2022-02-22 | 2023-09-05 | Winbond Electronics Corp. | Memory device |
| US11836107B2 (en) | 2022-03-01 | 2023-12-05 | Apple Inc. | Power consumption control based on random bus inversion |
| US12135607B2 (en) | 2022-03-18 | 2024-11-05 | Nvidia Corp. | Hardware-efficient PAM-3 encoder and decoder |
| US12132590B2 (en) | 2022-03-18 | 2024-10-29 | Nvidia, Corp. | Hardware-efficient PAM-3 encoder and decoder |
| CN114816661B (zh) * | 2022-03-31 | 2025-06-13 | 浙江艾克斯精灵人工智能科技有限公司 | 基于云应用的数据处理方法、存储介质以及计算机终端 |
| US12235757B2 (en) | 2022-05-18 | 2025-02-25 | Samsung Electronics Co., Ltd. | Memory systems and controllers for generating a command address and methods of operating same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1993948A (zh) * | 2004-06-04 | 2007-07-04 | 高通股份有限公司 | 高数据速率接口设备和方法 |
| CN101897119A (zh) * | 2007-12-14 | 2010-11-24 | 莫塞德技术公司 | 具有多个装置的系统中的时钟再生和时序方法以及具有可变数据对准的存储器控制器 |
| CN102142270A (zh) * | 2009-12-22 | 2011-08-03 | 三星电子株式会社 | 半导体器件、关联的控制器、包括其的系统以及操作方法 |
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| US6407680B1 (en) | 2000-12-22 | 2002-06-18 | Generic Media, Inc. | Distributed on-demand media transcoding system and method |
| KR20050069789A (ko) | 2003-12-31 | 2005-07-05 | 엘지전자 주식회사 | 유/무선 네트워크 장치의 인코딩 비율 조정 장치와 방법 |
| KR100643498B1 (ko) | 2005-11-21 | 2006-11-10 | 삼성전자주식회사 | 반도체 메모리에서의 데이터 버스 반전 회로 및 데이터버스 반전 방법 |
| US7456760B2 (en) | 2006-09-11 | 2008-11-25 | Apple Inc. | Complexity-aware encoding |
| US7522073B1 (en) | 2007-11-30 | 2009-04-21 | Qimonda North America Corp. | Self-adapted bus inversion |
| US7616133B2 (en) | 2008-01-16 | 2009-11-10 | Micron Technology, Inc. | Data bus inversion apparatus, systems, and methods |
| US8606982B2 (en) * | 2008-03-10 | 2013-12-10 | Qimonda Ag | Derivative logical output |
| JP5588976B2 (ja) * | 2008-06-20 | 2014-09-10 | ラムバス・インコーポレーテッド | 周波数応答バス符号化 |
| US8181101B2 (en) | 2009-01-30 | 2012-05-15 | International Business Machines Corporation | Data bus system, its encoder/decoder and encoding/decoding method |
| EP2454672B1 (en) | 2009-07-13 | 2015-01-21 | Rambus Inc. | Encoding data using combined data mask and data bus inversion |
| US8879654B2 (en) | 2010-03-10 | 2014-11-04 | Micron Technology, Inc. | Communication interface with configurable encoding based on channel termination |
| US8706958B2 (en) * | 2011-09-01 | 2014-04-22 | Thomas Hein | Data mask encoding in data bit inversion scheme |
| US8726139B2 (en) | 2011-12-14 | 2014-05-13 | Advanced Micro Devices, Inc. | Unified data masking, data poisoning, and data bus inversion signaling |
| US9529749B2 (en) * | 2013-03-15 | 2016-12-27 | Qualcomm Incorporated | Data bus inversion (DBI) encoding based on the speed of operation |
-
2014
- 2014-03-10 US US14/202,783 patent/US9529749B2/en active Active
- 2014-03-11 JP JP2016501269A patent/JP6130043B2/ja active Active
- 2014-03-11 EP EP14717281.1A patent/EP2972927B1/en active Active
- 2014-03-11 CN CN201480012359.9A patent/CN105190585B/zh active Active
- 2014-03-11 WO PCT/US2014/023508 patent/WO2014150529A1/en not_active Ceased
- 2014-03-11 KR KR1020157028506A patent/KR101759816B1/ko active Active
-
2016
- 2016-11-28 US US15/362,385 patent/US9798693B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1993948A (zh) * | 2004-06-04 | 2007-07-04 | 高通股份有限公司 | 高数据速率接口设备和方法 |
| CN101897119A (zh) * | 2007-12-14 | 2010-11-24 | 莫塞德技术公司 | 具有多个装置的系统中的时钟再生和时序方法以及具有可变数据对准的存储器控制器 |
| CN102142270A (zh) * | 2009-12-22 | 2011-08-03 | 三星电子株式会社 | 半导体器件、关联的控制器、包括其的系统以及操作方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US9529749B2 (en) | 2016-12-27 |
| US20170075854A1 (en) | 2017-03-16 |
| KR101759816B1 (ko) | 2017-07-31 |
| KR20150132296A (ko) | 2015-11-25 |
| EP2972927A1 (en) | 2016-01-20 |
| WO2014150529A1 (en) | 2014-09-25 |
| JP2016514441A (ja) | 2016-05-19 |
| US20140281075A1 (en) | 2014-09-18 |
| JP6130043B2 (ja) | 2017-05-17 |
| US9798693B2 (en) | 2017-10-24 |
| CN105190585A (zh) | 2015-12-23 |
| EP2972927B1 (en) | 2017-08-02 |
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