CN105188214A - Segmented linear constant-current light emitting diode (LED) driving circuit - Google Patents

Abstract

The invention belongs to the technical field of an electronic circuit, in particular relates to a segmented linear constant-current light emitting diode (LED) driving circuit. In the main structure of the circuit, the output end of a reference voltage generation module is connected with positive input ends of operational amplifiers respectively; the output end of a rectification module is connected with an LED unit; the output end of the LED unit is connected with drains of N-channel metal oxide semiconductor (NMOS) power tubes; sources of the NMOS power tubes are all grounded through a detection resistor RS; the output end of each operational amplifier is connected with a grid of each NMOS power tube; reverse input ends of the operational amplifiers are all grounded through the detection resistor RS; the input end of a state detection module is connected with a sampling resistor, and the output end of the state detection module is connected with the input end of an enable signal module; and the output end of the enable signal module is connected with enable signal ends of the operational amplifiers. The segmented linear constant-current LED driving circuit has the advantages that the operational amplifiers are closed by controlling the enable ends of the operational amplifiers corresponding to the power tubes, and the average working current consumption of a driving chip is substantially reduced.

Description

A segmented linear constant current LED drive circuit

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to a segmented linear constant current LED driving circuit.

Background technique

Light-emitting diode LED is a device that can work normally and emit light under a forward voltage of several volts. According to the optical characteristics of LED, as the forward current increases, the LED spectrum will change, and the LED luminous flux will increase accordingly. , that is, the brightness increases. In order to control the luminous brightness and spectrum of the LED, a stable current is usually required. The LED drive circuit can be divided into switch drive and linear constant current drive according to the working principle. The MOS tube in the switch drive circuit works in a high-frequency switch state and the whole circuit is relatively complicated. The adjustment tube of the drive circuit in the linear constant current drive circuit works in a continuous state instead of a switch state in the saturation and cut-off regions, and the required There are fewer peripheral components than switch drivers. The latter is directly driven by alternating current, and in order to achieve higher power factor and higher efficiency, a segmented linear constant current LED drive circuit is produced.

In each cycle of the current segmented linear constant current LED drive circuit, since the power tube is segmented, and the driving operational amplifier is always working in the cycle, it causes waste of power consumption.

Contents of the invention

What the present invention aims to solve is to propose a segmented linear constant current LED drive circuit for the above problems.

To achieve the above object, the present invention adopts the following technical solutions:

A segmented linear constant current LED drive circuit, including a rectifier module, a reference voltage generation module, a power tube module and an LED module, is characterized in that it also includes a state detection module, an operational amplifier module, an enabling signal module, a resistance module and Detection resistor RS; the LED module includes a plurality of LED units connected in series; the operational amplifier module includes a plurality of operational amplifiers; the power tube module includes a plurality of NMOS power tubes; the resistance module shown includes a plurality of sampling resistor units; The number of the LED unit, operational amplifier, sampling resistance unit and NMOS power transistor is equal; the output terminal of the reference voltage generation module is respectively connected to the positive input terminal of each operational amplifier; the output terminal of the rectification module is connected to the first The input terminal of an LED unit, the output terminal of each LED unit is connected to the drain of an NMOS power tube, and the input terminal of each LED unit is connected to a sampling resistor unit; the sources of all NMOS tube power tubes pass through the detection resistor RS is then grounded; the output terminal of each operational amplifier is connected to the grid of an NMOS power transistor; the reverse input terminals of all operational amplifiers are grounded after passing through the detection resistor RS; the input terminal of the state detection module is connected to the sampling resistor unit, and its output terminal Connect the input end of enable signal touch; The output end of described enable signal module connects the enable signal end of each operational amplifier respectively; The output end quantity of described state detection module is equal to the quantity of enable signal detection module output end, And there is an equal and one-to-one correspondence with the number of operational amplifiers.

Further, the number of the operational amplifiers is 4, which are respectively the first operational amplifier, the second operational amplifier, the third operational amplifier and the fourth operational amplifier; then the state detection module includes 4 input terminals and 4 output terminals, so that The energy signal module includes 4 input terminals and 4 output terminals; the resistance module includes 4 sampling resistance units, which are divided into a first resistance sampling unit composed of a first resistance R1 and a second resistance R2 connected in series, a third resistance R3 The second resistance sampling unit formed in series with the fourth resistance R4, the third resistance sampling unit formed in series with the fifth resistance R5 and the sixth resistance R6, the fourth resistance sampling unit formed in series with the seventh resistance R7 and the eighth resistance R8;

The first input terminal of the state detection module is connected to the connection point of the first resistor R1 and the second resistor R2, the second input terminal is connected to the connection point of the third resistor R3 and the fourth resistor R4, and the third input terminal is connected to the fifth resistor The connection point of R5 and the sixth resistor R6, the fourth input terminal thereof is connected to the connection point of the seventh resistor R7 and the eighth resistor R8.

The enabling signal module is composed of a first two-input NAND gate AND1, a second two-input NAND gate AND3, a third two-input NAND gate AND6, a fourth two-input NAND gate AND7, a fifth two-input NAND gate AND8, the sixth and second input NAND gate AND9, the seventh and second input NAND gate AND10, the eighth and second input NAND gate AND11, the ninth and second input NAND gate AND12, the twelfth input NAND gate AND13, the first and third Input NAND gate AND2, second three-input AND gate AND4, four-input NAND gate NAND5, three-input NOR gate NOR1, two-input NOR gate NOR2, first two-input OR gate OR3, second two-input OR gate OR4 , the third two-input OR gate OR5, the fourth two-input OR gate OR6, the first NOT gate NOT1, the second NOT gate NOT2, the third NOT gate NOT3, the fourth NOT gate NOT4, the fifth NOT gate NOT5, the sixth NOT gate Gate NOT6 and D flip-flop constitute; the first input end of the first two-input NAND gate AND1, the first input end of the first three-input NAND gate AND2, the first input end of the second two-input NAND gate AND3, The connection point of the first input end of the second three-input AND gate AND4 and the first input end of the four-input NAND gate NAND5 is the first input end of the enabling signal module, connected to the first output end of the state detection module; three input or The first input end of the gate NOR1, the second input end of the first three-input NAND gate AND2, the second input end of the second two-input NAND gate AND3, the second input end of the second three-input AND gate AND4 and four The connection point of the second input terminal of the input NAND gate NAND5 is the second input terminal of the enable signal module, which is connected to the second output terminal of the state detection module; the second input terminal of the three-input OR gate NOR1, the two-input NOR gate NOR2 The connection point of the first input end of the second three-input AND gate AND4 and the third input end of the four-input NAND gate NAND5 is the third input end of the enable signal module, connected to the third input end of the state detection module Output end; the connection point of the third input end of three-input OR gate NOR1, the second input end of two-input NOR gate NOR2, the input end of the first NOT gate NOT1 and the fourth input end of four-input NAND gate NAND5 is to make The fourth input terminal of the energy signal module is connected to the fourth output terminal of the state detection module; the output terminal of the three-input OR gate NOR1 is connected to the first input terminal of the third two-input NAND gate AND6; the third two-input NAND gate AND6 The second input terminal of the second input terminal is connected to the output terminal of the second NOT gate NOT2, and its output terminal is connected to the first input terminal of the first two-input OR gate OR3; the output terminal of the first two-input OR gate OR3 is the first input terminal of the enable signal module The output terminal is connected to the enable signal terminal of the first operational amplifier; the input terminal of the second NOT gate NOT2 is connected to the Q output terminal of the D flip-flop; the second input terminal of the first two-input OR gate OR3 is connected to the fourth two-input NAND The output end of the gate AND7; the first input end of the fourth two-input NAND gate AND7 is connected to the Q output end of the D output end, and its second input end is connected to the output end of the first two-input NAND gate AND1; the first two-input AND NOT gate AND1 The second input terminal is connected to the output terminal of the two-input NOR gate NOR2; the first input terminal of the fifth two-input NAND gate AND8 is connected to the output terminal of the first two-input NAND gate AND1, and its second input terminal is connected to the second NOT gate. The output end of gate NOT2, its output end connects the first input end of the second two-input OR gate OR4; The second input end of the second two-input OR gate OR4 connects the output end of the sixth two-input NAND gate AND9, and its output End is the second output terminal of the enabling signal module, which is connected to the enabling signal terminal of the second operational amplifier; the input terminal of the second NOT gate NOT2 is connected to the Q output terminal of the D flip-flop; the sixth second input NAND gate AND9 of the first One input terminal is connected to the Q output terminal of the D flip-flop, and its second input terminal is connected to the output terminal of the first three-input NAND gate AND2; the third input terminal of the first three-input NAND gate AND2 is connected to the first NOT1 of the NAND gate Output terminal; the first input terminal of the seventh two-input NAND gate AND10 is connected to the output terminal of the second two-input NAND gate AND3, its second input terminal is connected to the output terminal of the fourth NOT gate NOT4, and its output terminal is connected to the third The first input end of the two-input OR gate OR5; the second input end of the third, third, two-input OR gate OR5 is connected to the output end of the eighth second-input NAND gate AND11, and its output end is the third output of the enable signal module terminal, connected to the enabling signal terminal of the third operational amplifier; the input terminal of the fourth NOT gate is connected to the Q output terminal of the D flip-flop; the first input terminal of the eighth second-input NAND gate AND11 is connected to the Q output of the D flip-flop terminal, its second input terminal is connected to the output terminal of the second three-input AND gate AND4; the first input terminal of the ninth and second input NAND gate AND12 is connected to the output terminal of the second three-input AND gate AND4, and its second input terminal is connected to The output terminal of the fifth NOT gate NOT5, its output terminal is connected to the first input terminal of the fourth two-input OR gate OR6, and the second input terminal of the fourth two-input OR gate OR6 is connected to the output terminal of the twelfth input NAND gate AND13 , its output terminal is the fourth output terminal of the enable signal module, which is connected to the enable signal terminal of the fourth operational amplifier; the input terminal of the fifth NOT gate NOT5 is connected to the Q output terminal of the D flip-flop; the twelfth input NAND gate The first input terminal of AND13 is connected to the Q output terminal of the D flip-flop, and its second input terminal is connected to the output terminal of the sixth NOT gate NO6; the input terminal of the sixth NOT gate NOT6 is connected to the output terminal of the four-input NAND gate NAND5; D The set terminal of the flip-flop is connected to the output terminal of the four-input NAND gate NAND5, and its D input terminal and the clock signal terminal are grounded.

The beneficial effect of the present invention is that when the power tube has no current passing through, the enabling terminal of the driving operational amplifier corresponding to the power tube is controlled to turn off the operational amplifier, which significantly reduces the average operating current consumption of the driving chip and reduces the power consumption of the driving chip , which improves the circuit efficiency.

Description of drawings

Fig. 1 is a schematic block diagram of the principle of a segmented linear constant current LED drive circuit of the present invention;

Fig. 2 is a schematic structural diagram of a state detection module;

Fig. 3 is a schematic diagram of the effect of the state detection unit;

Fig. 4 is a schematic diagram of initialization module structure;

Fig. 5 is a schematic diagram of the control effect of the enable signal of the operational amplifier in the present invention.

Detailed ways

Below in conjunction with accompanying drawing and embodiment, describe technical solution of the present invention in detail:

A segmented linear constant current LED drive circuit of the present invention, as shown in Figure 1, includes a rectifier module, a reference voltage generation module, a power tube module and an LED module, and is characterized in that it also includes a state detection module and an operational amplifier module , an enabling signal module, a resistance module and a detection resistor RS; the LED module includes a plurality of LED units connected in series; the operational amplifier module includes a plurality of operational amplifiers; the power tube module includes a plurality of NMOS power tubes; The resistance module includes a plurality of sampling resistance units; the number of the LED unit, the operational amplifier, the sampling resistance unit and the NMOS power transistor is equal; the output end of the reference voltage generation module is respectively connected to the positive input end of each operational amplifier; The output terminal of the rectifier module is connected to the input terminal of the first LED unit, the output terminal of each LED unit is connected to the drain of an NMOS power transistor, and the input terminal of each LED unit is connected to a sampling resistor unit; all NMOS transistors The source of the power tube is grounded after passing through the detection resistor RS; the output terminal of each operational amplifier is connected to the grid of an NMOS power tube; the reverse input terminals of all operational amplifiers are grounded after passing through the detection resistor RS; the input of the state detection module Terminal connection sampling resistance unit, its output terminal connection enables the input end of signal touch; The output end of described enabling signal module connects the enabling signal end of each operational amplifier respectively; The number of output ends of the energy signal detection module is equal, and the number of operational amplifiers is equal and corresponding to each other.

Example

In this example, the number of operational amplifiers is 4, which are respectively the first operational amplifier, the second operational amplifier, the third operational amplifier and the fourth operational amplifier; then the state detection module includes 4 input terminals and 4 output terminals, and the enable signal The module includes 4 input terminals and 4 output terminals; the resistance module includes 4 sampling resistance units, which are divided into a first resistance sampling unit composed of a first resistance R1 and a second resistance R2 connected in series, a third resistance R3 and a second resistance sampling unit. The second resistance sampling unit composed of four resistors R4 in series, the third resistance sampling unit composed of the fifth resistance R5 and the sixth resistance R6 in series, the fourth resistance sampling unit composed of the seventh resistance R7 and the eighth resistance R8 in series, state detection The first input terminal of the module is connected to the connection point of the first resistor R1 and the second resistor R2, its second input terminal is connected to the connection point of the third resistor R3 and the fourth resistor R4, and its third input terminal is connected to the fifth resistor R5 and The connection point of the sixth resistor R6, the fourth input terminal of which is connected to the connection point of the seventh resistor R7 and the eighth resistor R8;

As shown in Figure 4, the enabling signal module is composed of the first two-input NAND gate AND1, the second two-input NAND gate AND3, the third two-input NAND gate AND6, the fourth two-input NAND gate AND7, the second two-input NAND gate AND7, The fifth and second input NAND gate AND8, the sixth and second input NAND gate AND9, the seventh and second input NAND gate AND10, the eighth and second input NAND gate AND11, the ninth and second input NAND gate AND12, the twelfth input NAND gate Gate AND13, the first three-input NAND gate AND2, the second three-input AND gate AND4, the four-input NAND gate NAND5, the three-input NOR gate NOR1, the two-input NOR gate NOR2, the first two-input OR gate OR3, the second The second two-input OR gate OR4, the third two-input OR gate OR5, the fourth two-input OR gate OR6, the first NOT gate NOT1, the second NOT gate NOT2, the third NOT gate NOT3, the fourth NOT gate NOT4, the fifth NOT gate Gate NOT5, the sixth NOT gate NOT6 and D flip-flops; the first input end of the first two-input NAND gate AND1, the first input end of the first three-input NAND gate AND2, the second two-input NAND gate AND3 The connection point of the first input end of the first input end of the second three-input AND gate AND4, and the first input end of the four-input NAND gate NAND5 is the first input end of the enabling signal module, connected to the first input end of the state detection module Output terminal: the first input terminal of the three-input OR gate NOR1, the second input terminal of the first three-input NAND gate AND2, the second input terminal of the second two-input NAND gate AND3, the second three-input NAND gate AND4 The connection point of the second input terminal and the second input terminal of the four-input NAND gate NAND5 is the second input terminal of the enable signal module, which is connected to the second output terminal of the state detection module; the second input terminal of the three-input OR gate NOR1, The connection point of the first input end of the two-input NOR gate NOR2, the third input end of the second three-input AND gate AND4 and the third input end of the four-input NAND gate NAND5 is the third input end of the enabling signal module, connected The third output end of the state detection module; the third input end of the three-input OR gate NOR1, the second input end of the two-input NOR gate NOR2, the input end of the first NOT gate NOT1 and the fourth input end of the four-input NAND gate NAND5 The connection point of the input terminal is the fourth input terminal of the enable signal module, which is connected to the fourth output terminal of the state detection module; the output terminal of the three-input OR gate NOR1 is connected to the first input terminal of the third two-input NAND gate AND6; the third The second input end of the two-input NAND gate AND6 is connected to the output end of the second NOT gate NOT2, and its output end is connected to the first input end of the first two-input OR gate OR3; the output end of the first two-input OR gate OR3 is to make The first output terminal of the signal module is connected to the enable signal terminal of the first operational amplifier; the input terminal of the second NOT gate NOT2 is connected to the Q output terminal of the D flip-flop; the second input terminal of the first two-input OR gate OR3 is connected to The output terminal of the fourth two-input NAND gate AND7; the first input terminal of the fourth two-input NAND gate AND7 is connected to the Q output terminal of the D output terminal, and its second input terminal is connected to the output terminal of the first two-input NAND gate AND1 ;The first and second input NAND The second input terminal of the gate AND1 is connected to the output terminal of the two-input NOR gate NOR2; the first input terminal of the fifth two-input NAND gate AND8 is connected to the output terminal of the first two-input NAND gate AND1, and its second input terminal is connected to The output terminal of the second NOT gate NOT2, its output terminal is connected to the first input terminal of the second two-input OR gate OR4; the second input terminal of the second two-input OR gate OR4 is connected to the output terminal of the sixth two-input NAND gate AND9 , its output terminal is the second output terminal of the enabling signal module, which is connected to the enabling signal terminal of the second operational amplifier; the input terminal of the second NOT gate NOT2 is connected to the Q output terminal of the D flip-flop; the sixth and second input NAND gate The first input terminal of AND9 is connected to the Q output terminal of the D flip-flop, and its second input terminal is connected to the output terminal of the first three-input NAND gate AND2; the third input terminal of the first three-input NAND gate AND2 is connected to the first NOT The output terminal of gate NOT1; the first input terminal of the seventh two-input NAND gate AND10 is connected to the output terminal of the second two-input NAND gate AND3, and its second input terminal is connected to the output terminal of the fourth NOT gate NOT4, and its output terminal Connect the first input end of the third two-input OR gate OR5; the second input end of the third third two-input OR gate OR5 is connected to the output end of the eighth second input NAND gate AND11, and its output end is the enable signal module The third output end is connected to the enable signal end of the third operational amplifier; the input end of the fourth NOT gate NOT4 is connected to the Q output end of the D flip-flop; the first input end of the eighth second input NAND gate AND11 is connected to the D flip-flop The Q output terminal of Q, its second input terminal is connected with the output terminal of the second three-input AND gate AND4; the first input terminal of the ninth and second input NAND gate AND12 is connected with the output terminal of the second three-input AND gate AND4, and its second The input terminal is connected to the output terminal of the fifth NOT gate, its output terminal is connected to the first input terminal of the fourth two-input OR gate OR6, and the second input terminal of the fourth two-input OR gate OR6 is connected to the twelfth input NAND gate AND13 The output terminal of the output terminal is the fourth output terminal of the enable signal module, which is connected to the enable signal terminal of the fourth operational amplifier; the input terminal of the fifth NOT gate is connected to the Q output terminal of the D flip-flop; the twelfth input The first input terminal of the NAND gate AND13 is connected to the Q output terminal of the D flip-flop, and its second input terminal is connected to the output terminal of the sixth NOT gate NO6; the input terminal of the sixth NOT gate NOT6 is connected to the output of the four-input NAND gate NAND5 terminal; the set terminal of the D flip-flop is connected to the output terminal of the four-input NAND gate NAND5, and its D input terminal and the clock signal terminal are grounded.

This example works as follows:

As shown in FIG. 2 , the status detection module specifically includes a status detection unit 1-4. The state detection unit 1 inputs the potential VRS of the first sampling resistance unit, and outputs signal A; the state detection unit 2 inputs the potential VRS of the second sampling resistance unit, and outputs signal B; the state detection unit 3 inputs the potential VRS of the third sampling resistance unit, and outputs signal C ; The state detection unit 4 inputs the potential VRS of the fourth sampling resistor unit, and outputs the signal D.

Figure 3 is a schematic diagram of the effect of the state detection unit 1-4. As shown in the figure, when the LED input potential is >V1, A is high level; when the input potential is <V1, A is low level; when the input potential is >V2, B is high level; when the input potential is <V2 When the input potential is >V3, C is high level; when the input potential is <V3, C is low level; when the input potential is >V4, D is high level; when the input potential is < When V4, D is low level.

As shown in Figure 5, the EN block generates the op amp enable signal. The EN module inputs the ABCD signal of the status detection module, and outputs EN1-EN4 enable signals. The EN module consists of two-input AND gates AND1, AND3, AND6-AND13, three-input AND gate AND2, four-input NAND gate NAND5, three-input NOR gate NOR1, two-input NOR gate NOR2, two-input OR gate OR3- OR6, NOT gate NOT1-NOT6, D flip-flop DFF1 form. Among them, NOR1 inputs B, C, D, and outputs to AND6; NOR2 outputs C, D, and outputs to AND1; the other end of AND1 inputs A, and AND1 outputs to AND7 and ADN8; NOT1 inputs D, and outputs to AND2; the other two inputs of AND2 The two inputs of AND3 are A and B respectively, and the output of AND3 is connected to AND10; the three inputs of AND4 are A, B and C respectively; the outputs are to AND11 and AND12; the four inputs of NAND5 are A, B, C, and D are output to the set terminal S' of DFF1, and connected to NOT6 at the same time; the D terminal and CLK terminal of DFF1 are grounded, and the output Q terminal is connected to NOT2-NOT5, AND7, AND9, AND11, AND13 as a selection signal; The outputs of AND6 and AND7 are used as the two inputs of OR3, and OR3 finally outputs the EN1 signal; the outputs of AND8 and AND9 are used as the two inputs of OR4, and OR4 finally outputs the EN2 signal; the outputs of AND10 and AND11 are used as the two inputs of OR5, and OR5 finally Output EN1 signal; the outputs of AND12 and AND12 are used as two inputs of OR6, and OR6 finally outputs EN4 signal. The output Q of DFF1 is used as a flag bit and is a selection signal of the two-to-one data selector.

When Q is low level, EN1=B’C’D’EN2=AC’D’EN3=ABEN4=ABC;

When Q=high level, EN1=AC’D’EN2=ABD’EN3=ABCEN4=ABCD.

As shown in Figure 5, it is a schematic diagram of the control effect of the operational amplifier enabling signal in the present invention, wherein the solid line is the waveform of the enabling signal EN1-EN4 of the driving operational amplifier, and the dotted line is the enabling signal of the traditional segmented current drive, as can be seen Compared with the traditional technology, the invention significantly reduces the working time of the driving chip.

Claims (2)

1. a piece-wise linear constant current LED drive circuit, comprise rectification module, reference voltage generation module, power tube module and LED module, it is characterized in that, also comprise state detection module, operational amplifier module, enable signal module, resistive module and detection resistance RS; Described LED module comprises the LED unit of multiple series connection; Described operational amplifier module comprises multiple operational amplifier; Described power tube module comprises multiple NMOS power tube; Shown resistive module comprises multiple sampling resistor unit; The quantity of described LED unit, operational amplifier, sampling resistor unit and NMOS power tube is equal; The output of described reference voltage generation module is connected with the positive input of each operational amplifier respectively; The input of output termination first LED unit of described rectification module, the drain electrode of an output termination NMOS power tube of each LED unit, the input of each LED unit connects a sampling resistor unit; The source electrode of all NMOS tube power tubes is all by ground connection after detection resistance RS; The grid of an output termination NMOS power tube of each operational amplifier; The reverse input end of all operational amplifiers is all by ground connection after detection resistance RS; The input termination sampling resistor unit of state detection module, it exports the input that termination enable signal is touched; The output of described enable signal module connects the enable signal end of each operational amplifier respectively; The output quantity of described state detection module is equal with the quantity of enable signal detection module output, and and one_to_one corresponding equal with the quantity of operational amplifier.

2. a kind of piece-wise linear constant current LED drive circuit according to claim 1, is characterized in that, the quantity of described operational amplifier is 4, is respectively the first operational amplifier, the second operational amplifier, the 3rd operational amplifier and four-operational amplifier; Then state detection module comprises 4 inputs and 4 outputs, and enable signal module comprises 4 inputs and 4 outputs; Described resistive module comprises 4 sampling resistor unit, divides for by the 3rd resistance sampling unit, the 7th resistance R7 and the 8th resistance R8 that the second resistance sampling unit, the 5th resistance R5 and the 6th resistance R6 that the first resistance sampling unit, the 3rd resistance R3 and the 4th resistance R4 that the first resistance R1 and the second resistance R2 is in series are in series are in series the 4th resistance sampling unit in series;

The first input end of state detection module connects the tie point of the first resistance R1 and the second resistance R2, the tie point of its second input termination the 3rd resistance R3 and the 4th resistance R4, the tie point of its 3rd input termination the 5th resistance R5 and the 6th resistance R6, its four-input terminal connects the tie point of the 7th resistance R7 and the 8th resistance R8;

Described enable signal module is by the one or two input nand gate AND1, two or two input nand gate AND3, three or two input nand gate AND6, four or two input nand gate AND7, five or two input nand gate AND8, six or two input nand gate AND9, seven or two input nand gate AND10, eight or two input nand gate AND11, 92 input nand gate AND12, 12 input nand gate AND13, one or three input nand gate AND2, second three value and gate AND4, four input nand gate NAND5, three input NOR gate NOR1, two input NOR gate NOR2, one or two input or door OR3, two or two input or door OR4, three or two input or door OR5, four or two input or door OR6, first not gate NOT1, second not gate NOT2, 3rd not gate NOT3, 4th not gate NOT4, 5th not gate NOT5, 6th not gate NOT6 and d type flip flop are formed, the tie point of the first input end of the first input end of the one or two input nand gate AND1, the first input end of the one or three input nand gate AND2, the two or two input nand gate AND3, the first input end of the second three value and gate AND4, the first input end of four input nand gate NAND5 is the first input end of enable signal module, connects the first output of state detection module, the tie point of second input of the first input end of three inputs or door NOR1, second input of the one or three input nand gate AND2, second input of the two or two input nand gate AND3, second input of the second three value and gate AND4 and four input nand gate NAND5 is the second input of enable signal module, connects the second output of state detection module, the tie point of second input of three inputs or door NOR1, the 3rd input of two the input first input end of NOR gate NOR2, the 3rd input of the second three value and gate AND4 and four input nand gate NAND5 is the 3rd input of enable signal module, connects the 3rd output of state detection module, the tie point of the 3rd input of three inputs or door NOR1, the four-input terminal of two input second input of NOR gate NOR2, the input of the first not gate NOT1 and four input nand gate NAND5 is the four-input terminal of enable signal module, connects the 4th output of state detection module, the first input end of output termination the three or the two input nand gate AND6 of three inputs or door NOR1, the output of the second input termination second not gate NOT2 of the three or two input nand gate AND6, it exports the first input end of termination the or two input or door OR3, the output of the one or two input or door OR3 is the first output of enable signal module, connects the enable signal end of the first operational amplifier, the Q output of the input termination d type flip flop of the second not gate NOT2, the output of second input termination the four or the two input nand gate AND7 of the one or two input or door OR3, the first input end of the four or two input nand gate AND7 connects the Q output of D output, the output of its second input termination the or two input nand gate AND1, the second input termination two of the one or two input nand gate AND1 inputs the output of NOR gate NOR2, the first input end of the five or two input nand gate AND8 connects the output of the one or two input nand gate AND1, the output of its second input termination second not gate NOT2, and it exports the first input end of termination the two or two input or door OR4, the output of second input termination the six or the two input nand gate AND9 of the two or two input or door OR4, its output is the second output of enable signal module, connects the enable signal end of the second operational amplifier, the Q output of the input termination d type flip flop of the second not gate NOT2, the first input end of the six or two input nand gate AND9 connects the Q output of d type flip flop, the output of its second input termination the or three input nand gate AND2, the output of the 3rd input termination first not gate NOT1 of the one or three input nand gate AND2, the first input end of the seven or two input nand gate AND10 connects the output of the two or two input nand gate AND3, the output of its second input termination the 4th not gate NOT4, and it exports the first input end of termination the three or two input or door OR5, the output of second input termination the eight or the two input nand gate AND11 of the three the 32 inputs or door OR5, its output is the 3rd output of enable signal module, connects the enable signal end of the 3rd operational amplifier, the Q output of the input termination d type flip flop of the 4th not gate NOT4, the first input end of the eight or two input nand gate AND11 connects the Q output of d type flip flop, the output of its second input termination second three value and gate AND4, the first input end of the 92 input nand gate AND12 connects the output of the second three value and gate AND4, the output of its second input termination the 5th not gate NOT5, it exports the first input end of termination the four or two input or door OR6, the output of second input termination the 12 input nand gate AND13 of the four or two input or door OR6, its output is the 4th output of enable signal module, connects the enable signal end of four-operational amplifier, the Q output of the input termination d type flip flop of the 5th not gate NOT5, the first input end of the 12 input nand gate AND13 connects the Q output of d type flip flop, the output of its second input termination the 6th not gate NO6, the output of the input termination four input nand gate NAND5 of the 6th not gate NOT6, the output of the set termination four input nand gate NAND5 of d type flip flop, its D input and clock signal terminal ground connection.