CN105188214A - Segmented linear constant-current light emitting diode (LED) driving circuit - Google Patents

Abstract

The invention belongs to the technical field of an electronic circuit, in particular relates to a segmented linear constant-current light emitting diode (LED) driving circuit. In the main structure of the circuit, the output end of a reference voltage generation module is connected with positive input ends of operational amplifiers respectively; the output end of a rectification module is connected with an LED unit; the output end of the LED unit is connected with drains of N-channel metal oxide semiconductor (NMOS) power tubes; sources of the NMOS power tubes are all grounded through a detection resistor RS; the output end of each operational amplifier is connected with a grid of each NMOS power tube; reverse input ends of the operational amplifiers are all grounded through the detection resistor RS; the input end of a state detection module is connected with a sampling resistor, and the output end of the state detection module is connected with the input end of an enable signal module; and the output end of the enable signal module is connected with enable signal ends of the operational amplifiers. The segmented linear constant-current LED driving circuit has the advantages that the operational amplifiers are closed by controlling the enable ends of the operational amplifiers corresponding to the power tubes, and the average working current consumption of a driving chip is substantially reduced.

Description

A kind of piece-wise linear constant current LED drive circuit

Technical field

The invention belongs to electronic circuit technology field, relate to a kind of piece-wise linear constant current LED drive circuit specifically.

Background technology

LED is a kind of just can normally work under the forward voltage of several volts and luminous device, and by the known increase along with forward current of the optical characteristics of LED, LED light spectrum will change, and LED light flux increases thereupon, and namely brightness increases.For the luminosity of control LED and spectrum etc. need a stable electric current usually.LED drive circuit can be divided into switch drive and linear constant current to drive by operation principle.Metal-oxide-semiconductor in switch driving circuit is operated in HF switch state and whole circuit is comparatively complicated, in linear constant current drive circuit, the Correctional tube of drive circuit is operated in continuous state, instead of be operated in saturated and on off state that is cut-off region, and required peripheral components is fewer than switch drive.Wherein the latter is alternating current Direct driver, and is reach higher power factor and higher efficiency, creates piece-wise linear constant current LED drive circuit.

Current piece-wise linear constant current LED drive circuit, within each cycle, because power tube is segmentation conducting, and drives operational amplifier to work all the time within the cycle, therefore causes the waste of power consumption.

Summary of the invention

To be solved by this invention, be exactly for the problems referred to above, propose a kind of piece-wise linear constant current LED drive circuit.

For achieving the above object, the present invention adopts following technical scheme:

A kind of piece-wise linear constant current LED drive circuit, comprise rectification module, reference voltage generation module, power tube module and LED module, it is characterized in that, also comprise state detection module, operational amplifier module, enable signal module, resistive module and detection resistance RS; Described LED module comprises the LED unit of multiple series connection; Described operational amplifier module comprises multiple operational amplifier; Described power tube module comprises multiple NMOS power tube; Shown resistive module comprises multiple sampling resistor unit; The quantity of described LED unit, operational amplifier, sampling resistor unit and NMOS power tube is equal; The output of described reference voltage generation module is connected with the positive input of each operational amplifier respectively; The input of output termination first LED unit of described rectification module, the drain electrode of an output termination NMOS power tube of each LED unit, the input of each LED unit connects a sampling resistor unit; The source electrode of all NMOS tube power tubes is all by ground connection after detection resistance RS; The grid of an output termination NMOS power tube of each operational amplifier; The reverse input end of all operational amplifiers is all by ground connection after detection resistance RS; The input termination sampling resistor unit of state detection module, it exports the input that termination enable signal is touched; The output of described enable signal module connects the enable signal end of each operational amplifier respectively; The output quantity of described state detection module is equal with the quantity of enable signal detection module output, and and one_to_one corresponding equal with the quantity of operational amplifier.

Further, the quantity of described operational amplifier is 4, is respectively the first operational amplifier, the second operational amplifier, the 3rd operational amplifier and four-operational amplifier; Then state detection module comprises 4 inputs and 4 outputs, and enable signal module comprises 4 inputs and 4 outputs; Described resistive module comprises 4 sampling resistor unit, divides for by the 3rd resistance sampling unit, the 7th resistance R7 and the 8th resistance R8 that the second resistance sampling unit, the 5th resistance R5 and the 6th resistance R6 that the first resistance sampling unit, the 3rd resistance R3 and the 4th resistance R4 that the first resistance R1 and the second resistance R2 is in series are in series are in series the 4th resistance sampling unit in series;

The first input end of state detection module connects the tie point of the first resistance R1 and the second resistance R2, the tie point of its second input termination the 3rd resistance R3 and the 4th resistance R4, the tie point of its 3rd input termination the 5th resistance R5 and the 6th resistance R6, its four-input terminal connects the tie point of the 7th resistance R7 and the 8th resistance R8.

Described enable signal module is by the one or two input nand gate AND1, two or two input nand gate AND3, three or two input nand gate AND6, four or two input nand gate AND7, five or two input nand gate AND8, six or two input nand gate AND9, seven or two input nand gate AND10, eight or two input nand gate AND11, 92 input nand gate AND12, 12 input nand gate AND13, one or three input nand gate AND2, second three value and gate AND4, four input nand gate NAND5, three input NOR gate NOR1, two input NOR gate NOR2, one or two input or door OR3, two or two input or door OR4, three or two input or door OR5, four or two input or door OR6, first not gate NOT1, second not gate NOT2, 3rd not gate NOT3, 4th not gate NOT4, 5th not gate NOT5, 6th not gate NOT6 and d type flip flop are formed, the tie point of the first input end of the first input end of the one or two input nand gate AND1, the first input end of the one or three input nand gate AND2, the two or two input nand gate AND3, the first input end of the second three value and gate AND4, the first input end of four input nand gate NAND5 is the first input end of enable signal module, connects the first output of state detection module, the tie point of second input of the first input end of three inputs or door NOR1, second input of the one or three input nand gate AND2, second input of the two or two input nand gate AND3, second input of the second three value and gate AND4 and four input nand gate NAND5 is the second input of enable signal module, connects the second output of state detection module, the tie point of second input of three inputs or door NOR1, the 3rd input of two the input first input end of NOR gate NOR2, the 3rd input of the second three value and gate AND4 and four input nand gate NAND5 is the 3rd input of enable signal module, connects the 3rd output of state detection module, the tie point of the 3rd input of three inputs or door NOR1, the four-input terminal of two input second input of NOR gate NOR2, the input of the first not gate NOT1 and four input nand gate NAND5 is the four-input terminal of enable signal module, connects the 4th output of state detection module, the first input end of output termination the three or the two input nand gate AND6 of three inputs or door NOR1, the output of the second input termination second not gate NOT2 of the three or two input nand gate AND6, it exports the first input end of termination the or two input or door OR3, the output of the one or two input or door OR3 is the first output of enable signal module, connects the enable signal end of the first operational amplifier, the Q output of the input termination d type flip flop of the second not gate NOT2, the output of second input termination the four or the two input nand gate AND7 of the one or two input or door OR3, the first input end of the four or two input nand gate AND7 connects the Q output of D output, the output of its second input termination the or two input nand gate AND1, the second input termination two of the one or two input nand gate AND1 inputs the output of NOR gate NOR2, the first input end of the five or two input nand gate AND8 connects the output of the one or two input nand gate AND1, the output of its second input termination second not gate NOT2, and it exports the first input end of termination the two or two input or door OR4, the output of second input termination the six or the two input nand gate AND9 of the two or two input or door OR4, its output is the second output of enable signal module, connects the enable signal end of the second operational amplifier, the Q output of the input termination d type flip flop of the second not gate NOT2, the first input end of the six or two input nand gate AND9 connects the Q output of d type flip flop, the output of its second input termination the or three input nand gate AND2, the output of the 3rd input termination first not gate NOT1 of the one or three input nand gate AND2, the first input end of the seven or two input nand gate AND10 connects the output of the two or two input nand gate AND3, the output of its second input termination the 4th not gate NOT4, and it exports the first input end of termination the three or two input or door OR5, the output of second input termination the eight or the two input nand gate AND11 of the three the 32 inputs or door OR5, its output is the 3rd output of enable signal module, connects the enable signal end of the 3rd operational amplifier, the Q output of the input termination d type flip flop of the 4th not gate NOT4, the first input end of the eight or two input nand gate AND11 connects the Q output of d type flip flop, the output of its second input termination second three value and gate AND4, the first input end of the 92 input nand gate AND12 connects the output of the second three value and gate AND4, the output of its second input termination the 5th not gate NOT5, it exports the first input end of termination the four or two input or door OR6, the output of second input termination the 12 input nand gate AND13 of the four or two input or door OR6, its output is the 4th output of enable signal module, connects the enable signal end of four-operational amplifier, the Q output of the input termination d type flip flop of the 5th not gate NOT5, the first input end of the 12 input nand gate AND13 connects the Q output of d type flip flop, the output of its second input termination the 6th not gate NO6, the output of the input termination four input nand gate NAND5 of the 6th not gate NOT6, the output of the set termination four input nand gate NAND5 of d type flip flop, its D input and clock signal terminal ground connection.

Beneficial effect of the present invention is, when power tube no current passes through, control driving operational amplifier Enable Pin corresponding to this power tube and close operational amplifier, significantly reduce the average operating current consumption of driving chip, reduce the power consumption of driving chip, improve circuit efficiency.

Accompanying drawing explanation

Fig. 1 is a kind of piece-wise linear constant current LED drive circuit schematic block diagram of the present invention;

Fig. 2 is state detection module structural representation;

Fig. 3 is state detection unit effect schematic diagram;

Fig. 4 is initialization module structural representation;

Fig. 5 is operational amplifier enable signal control effects schematic diagram in the present invention.

Embodiment

Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:

A kind of piece-wise linear constant current LED drive circuit of the present invention, as shown in Figure 1, comprise rectification module, reference voltage generation module, power tube module and LED module, it is characterized in that, also comprise state detection module, operational amplifier module, enable signal module, resistive module and detection resistance RS; Described LED module comprises the LED unit of multiple series connection; Described operational amplifier module comprises multiple operational amplifier; Described power tube module comprises multiple NMOS power tube; Shown resistive module comprises multiple sampling resistor unit; The quantity of described LED unit, operational amplifier, sampling resistor unit and NMOS power tube is equal; The output of described reference voltage generation module is connected with the positive input of each operational amplifier respectively; The input of output termination first LED unit of described rectification module, the drain electrode of an output termination NMOS power tube of each LED unit, the input of each LED unit connects a sampling resistor unit; The source electrode of all NMOS tube power tubes is all by ground connection after detection resistance RS; The grid of an output termination NMOS power tube of each operational amplifier; The reverse input end of all operational amplifiers is all by ground connection after detection resistance RS; The input termination sampling resistor unit of state detection module, it exports the input that termination enable signal is touched; The output of described enable signal module connects the enable signal end of each operational amplifier respectively; The output quantity of described state detection module is equal with the quantity of enable signal detection module output, and and one_to_one corresponding equal with the quantity of operational amplifier.

Embodiment

In this example, the quantity of operational amplifier is 4, is respectively the first operational amplifier, the second operational amplifier, the 3rd operational amplifier and four-operational amplifier, then state detection module comprises 4 inputs and 4 outputs, and enable signal module comprises 4 inputs and 4 outputs, described resistive module comprises 4 sampling resistor unit, divide for by the first resistance R1 and the second resistance R2 the first resistance sampling unit in series, the second resistance sampling unit that 3rd resistance R3 and the 4th resistance R4 is in series, the 3rd resistance sampling unit that 5th resistance R5 and the 6th resistance R6 is in series, the 4th resistance sampling unit that 7th resistance R7 and the 8th resistance R8 is in series, the first input end of state detection module connects the tie point of the first resistance R1 and the second resistance R2, the tie point of its second input termination the 3rd resistance R3 and the 4th resistance R4, the tie point of its 3rd input termination the 5th resistance R5 and the 6th resistance R6, its four-input terminal connects the tie point of the 7th resistance R7 and the 8th resistance R8,

As shown in Figure 4, described enable signal module is by the one or two input nand gate AND1, two or two input nand gate AND3, three or two input nand gate AND6, four or two input nand gate AND7, five or two input nand gate AND8, six or two input nand gate AND9, seven or two input nand gate AND10, eight or two input nand gate AND11, 92 input nand gate AND12, 12 input nand gate AND13, one or three input nand gate AND2, second three value and gate AND4, four input nand gate NAND5, three input NOR gate NOR1, two input NOR gate NOR2, one or two input or door OR3, two or two input or door OR4, three or two input or door OR5, four or two input or door OR6, first not gate NOT1, second not gate NOT2, 3rd not gate NOT3, 4th not gate NOT4, 5th not gate NOT5, 6th not gate NOT6 and d type flip flop are formed, the tie point of the first input end of the first input end of the one or two input nand gate AND1, the first input end of the one or three input nand gate AND2, the two or two input nand gate AND3, the first input end of the second three value and gate AND4, the first input end of four input nand gate NAND5 is the first input end of enable signal module, connects the first output of state detection module, the tie point of second input of the first input end of three inputs or door NOR1, second input of the one or three input nand gate AND2, second input of the two or two input nand gate AND3, second input of the second three value and gate AND4 and four input nand gate NAND5 is the second input of enable signal module, connects the second output of state detection module, the tie point of second input of three inputs or door NOR1, the 3rd input of two the input first input end of NOR gate NOR2, the 3rd input of the second three value and gate AND4 and four input nand gate NAND5 is the 3rd input of enable signal module, connects the 3rd output of state detection module, the tie point of the 3rd input of three inputs or door NOR1, the four-input terminal of two input second input of NOR gate NOR2, the input of the first not gate NOT1 and four input nand gate NAND5 is the four-input terminal of enable signal module, connects the 4th output of state detection module, the first input end of output termination the three or the two input nand gate AND6 of three inputs or door NOR1, the output of the second input termination second not gate NOT2 of the three or two input nand gate AND6, it exports the first input end of termination the or two input or door OR3, the output of the one or two input or door OR3 is the first output of enable signal module, connects the enable signal end of the first operational amplifier, the Q output of the input termination d type flip flop of the second not gate NOT2, the output of second input termination the four or the two input nand gate AND7 of the one or two input or door OR3, the first input end of the four or two input nand gate AND7 connects the Q output of D output, the output of its second input termination the or two input nand gate AND1, the second input termination two of the one or two input nand gate AND1 inputs the output of NOR gate NOR2, the first input end of the five or two input nand gate AND8 connects the output of the one or two input nand gate AND1, the output of its second input termination second not gate NOT2, and it exports the first input end of termination the two or two input or door OR4, the output of second input termination the six or the two input nand gate AND9 of the two or two input or door OR4, its output is the second output of enable signal module, connects the enable signal end of the second operational amplifier, the Q output of the input termination d type flip flop of the second not gate NOT2, the first input end of the six or two input nand gate AND9 connects the Q output of d type flip flop, the output of its second input termination the or three input nand gate AND2, the output of the 3rd input termination first not gate NOT1 of the one or three input nand gate AND2, the first input end of the seven or two input nand gate AND10 connects the output of the two or two input nand gate AND3, the output of its second input termination the 4th not gate NOT4, and it exports the first input end of termination the three or two input or door OR5, the output of second input termination the eight or the two input nand gate AND11 of the three the 32 inputs or door OR5, its output is the 3rd output of enable signal module, connects the enable signal end of the 3rd operational amplifier, the Q output of the input termination d type flip flop of the 4th not gate NOT4, the first input end of the eight or two input nand gate AND11 connects the Q output of d type flip flop, the output of its second input termination second three value and gate AND4, the first input end of the 92 input nand gate AND12 connects the output of the second three value and gate AND4, the output of its second input termination the 5th not gate NOT5, it exports the first input end of termination the four or two input or door OR6, the output of second input termination the 12 input nand gate AND13 of the four or two input or door OR6, its output is the 4th output of enable signal module, connects the enable signal end of four-operational amplifier, the Q output of the input termination d type flip flop of the 5th not gate NOT5, the first input end of the 12 input nand gate AND13 connects the Q output of d type flip flop, the output of its second input termination the 6th not gate NO6, the output of the input termination four input nand gate NAND5 of the 6th not gate NOT6, the output of the set termination four input nand gate NAND5 of d type flip flop, its D input and clock signal terminal ground connection.

The operation principle of this example is:

As shown in Figure 2, state detection module specifically comprises state detection unit 1-4.State detection unit 1 inputs the first sampling resistor unit voltage VRS, output signal A; State detection unit 2 inputs the second sampling resistor unit voltage VRS, output signal B; State detection unit 3 inputs the 3rd sampling resistor unit voltage VRS, output signal C; State detection unit 4 inputs the 4th sampling resistor unit voltage VRS, output signal D.

If Fig. 3 is state detection unit 1-4 effect schematic diagram.As shown in the figure, when LED inputs current potential >V1, A is high level; When inputting current potential <V1, A is low level; When inputting current potential >V2, B is high level; When inputting current potential <V2, B is low level; When inputting current potential >V3, C is high level; When inputting current potential <V3, C is low level; When inputting current potential >V4, D is high level; When inputting current potential <V4, D is low level.

As shown in Figure 5, EN module produces operational amplifier enable signal.The ABCD signal of EN module input state detection module, exports EN1-EN4 enable signal.Described EN module inputs NOR gate NOR1, two by two inputs and door AND1, AND3, AND6-AND13, three value and gate AND2, four input nand gate NAND5, three and inputs NOR gate NOR2, two and to input or door OR3-OR6, not gate NOT1-NOT6, d type flip flop DFF1 are formed.Wherein NOR1 inputs B, C, D, outputs to AND6; NOR2 exports C, D, outputs to AND1; The input of the AND1 other end A, AND1 output to AND7 and ADN8; NOT1 inputs D, outputs to AND2; Two other of AND2 is input as A, B, and AND2 outputs to AND9; AND3 two input is respectively A, B, and AND3 exports and connects AND10; AND4 tri-input is respectively A, B, C; Output to AND11 and AND12; Four inputs of NAND5 are respectively A, B, C, D, output to the set end S ' of DFF1, are connected to NOT6 simultaneously; The D end of DFF1, CLK hold ground connection, export Q end and are connected to NOT2-NOT5, AND7, AND9, AND11, AND13 as selection signal; The output of AND6 and AND7 is as two inputs of OR3, and OR3 finally exports EN1 signal; The output of AND8 and AND9 is as two inputs of OR4, and OR4 finally exports EN2 signal; The output of AND10 and AND11 is as two inputs of OR5, and OR5 finally exports EN1 signal; The output of AND12 and AND12 is as two inputs of OR6, and OR6 finally exports EN4 signal.The output Q of DFF1 is the selection signal of alternative data selector as flag bit.

When Q is low level, EN1=B ' C ' D ' EN2=AC ' D ' EN3=ABEN4=ABC;

When Q=high level, EN1=AC ' D ' EN2=ABD ' EN3=ABCEN4=ABCD.

As shown in Figure 5, for being operational amplifier enable signal control effects schematic diagram in the present invention, wherein solid line is for driving operational amplifier enable signal EN1-EN4 waveform, dotted line is the enable signal that traditional existing property of segmentation drives, and visible the present invention significantly reduces the operating time of driving chip relative to conventional art.

Claims (2)

1. a piece-wise linear constant current LED drive circuit, comprise rectification module, reference voltage generation module, power tube module and LED module, it is characterized in that, also comprise state detection module, operational amplifier module, enable signal module, resistive module and detection resistance RS; Described LED module comprises the LED unit of multiple series connection; Described operational amplifier module comprises multiple operational amplifier; Described power tube module comprises multiple NMOS power tube; Shown resistive module comprises multiple sampling resistor unit; The quantity of described LED unit, operational amplifier, sampling resistor unit and NMOS power tube is equal; The output of described reference voltage generation module is connected with the positive input of each operational amplifier respectively; The input of output termination first LED unit of described rectification module, the drain electrode of an output termination NMOS power tube of each LED unit, the input of each LED unit connects a sampling resistor unit; The source electrode of all NMOS tube power tubes is all by ground connection after detection resistance RS; The grid of an output termination NMOS power tube of each operational amplifier; The reverse input end of all operational amplifiers is all by ground connection after detection resistance RS; The input termination sampling resistor unit of state detection module, it exports the input that termination enable signal is touched; The output of described enable signal module connects the enable signal end of each operational amplifier respectively; The output quantity of described state detection module is equal with the quantity of enable signal detection module output, and and one_to_one corresponding equal with the quantity of operational amplifier.

2. a kind of piece-wise linear constant current LED drive circuit according to claim 1, is characterized in that, the quantity of described operational amplifier is 4, is respectively the first operational amplifier, the second operational amplifier, the 3rd operational amplifier and four-operational amplifier; Then state detection module comprises 4 inputs and 4 outputs, and enable signal module comprises 4 inputs and 4 outputs; Described resistive module comprises 4 sampling resistor unit, divides for by the 3rd resistance sampling unit, the 7th resistance R7 and the 8th resistance R8 that the second resistance sampling unit, the 5th resistance R5 and the 6th resistance R6 that the first resistance sampling unit, the 3rd resistance R3 and the 4th resistance R4 that the first resistance R1 and the second resistance R2 is in series are in series are in series the 4th resistance sampling unit in series;

The first input end of state detection module connects the tie point of the first resistance R1 and the second resistance R2, the tie point of its second input termination the 3rd resistance R3 and the 4th resistance R4, the tie point of its 3rd input termination the 5th resistance R5 and the 6th resistance R6, its four-input terminal connects the tie point of the 7th resistance R7 and the 8th resistance R8;

Described enable signal module is by the one or two input nand gate AND1, two or two input nand gate AND3, three or two input nand gate AND6, four or two input nand gate AND7, five or two input nand gate AND8, six or two input nand gate AND9, seven or two input nand gate AND10, eight or two input nand gate AND11, 92 input nand gate AND12, 12 input nand gate AND13, one or three input nand gate AND2, second three value and gate AND4, four input nand gate NAND5, three input NOR gate NOR1, two input NOR gate NOR2, one or two input or door OR3, two or two input or door OR4, three or two input or door OR5, four or two input or door OR6, first not gate NOT1, second not gate NOT2, 3rd not gate NOT3, 4th not gate NOT4, 5th not gate NOT5, 6th not gate NOT6 and d type flip flop are formed, the tie point of the first input end of the first input end of the one or two input nand gate AND1, the first input end of the one or three input nand gate AND2, the two or two input nand gate AND3, the first input end of the second three value and gate AND4, the first input end of four input nand gate NAND5 is the first input end of enable signal module, connects the first output of state detection module, the tie point of second input of the first input end of three inputs or door NOR1, second input of the one or three input nand gate AND2, second input of the two or two input nand gate AND3, second input of the second three value and gate AND4 and four input nand gate NAND5 is the second input of enable signal module, connects the second output of state detection module, the tie point of second input of three inputs or door NOR1, the 3rd input of two the input first input end of NOR gate NOR2, the 3rd input of the second three value and gate AND4 and four input nand gate NAND5 is the 3rd input of enable signal module, connects the 3rd output of state detection module, the tie point of the 3rd input of three inputs or door NOR1, the four-input terminal of two input second input of NOR gate NOR2, the input of the first not gate NOT1 and four input nand gate NAND5 is the four-input terminal of enable signal module, connects the 4th output of state detection module, the first input end of output termination the three or the two input nand gate AND6 of three inputs or door NOR1, the output of the second input termination second not gate NOT2 of the three or two input nand gate AND6, it exports the first input end of termination the or two input or door OR3, the output of the one or two input or door OR3 is the first output of enable signal module, connects the enable signal end of the first operational amplifier, the Q output of the input termination d type flip flop of the second not gate NOT2, the output of second input termination the four or the two input nand gate AND7 of the one or two input or door OR3, the first input end of the four or two input nand gate AND7 connects the Q output of D output, the output of its second input termination the or two input nand gate AND1, the second input termination two of the one or two input nand gate AND1 inputs the output of NOR gate NOR2, the first input end of the five or two input nand gate AND8 connects the output of the one or two input nand gate AND1, the output of its second input termination second not gate NOT2, and it exports the first input end of termination the two or two input or door OR4, the output of second input termination the six or the two input nand gate AND9 of the two or two input or door OR4, its output is the second output of enable signal module, connects the enable signal end of the second operational amplifier, the Q output of the input termination d type flip flop of the second not gate NOT2, the first input end of the six or two input nand gate AND9 connects the Q output of d type flip flop, the output of its second input termination the or three input nand gate AND2, the output of the 3rd input termination first not gate NOT1 of the one or three input nand gate AND2, the first input end of the seven or two input nand gate AND10 connects the output of the two or two input nand gate AND3, the output of its second input termination the 4th not gate NOT4, and it exports the first input end of termination the three or two input or door OR5, the output of second input termination the eight or the two input nand gate AND11 of the three the 32 inputs or door OR5, its output is the 3rd output of enable signal module, connects the enable signal end of the 3rd operational amplifier, the Q output of the input termination d type flip flop of the 4th not gate NOT4, the first input end of the eight or two input nand gate AND11 connects the Q output of d type flip flop, the output of its second input termination second three value and gate AND4, the first input end of the 92 input nand gate AND12 connects the output of the second three value and gate AND4, the output of its second input termination the 5th not gate NOT5, it exports the first input end of termination the four or two input or door OR6, the output of second input termination the 12 input nand gate AND13 of the four or two input or door OR6, its output is the 4th output of enable signal module, connects the enable signal end of four-operational amplifier, the Q output of the input termination d type flip flop of the 5th not gate NOT5, the first input end of the 12 input nand gate AND13 connects the Q output of d type flip flop, the output of its second input termination the 6th not gate NO6, the output of the input termination four input nand gate NAND5 of the 6th not gate NOT6, the output of the set termination four input nand gate NAND5 of d type flip flop, its D input and clock signal terminal ground connection.