CN105188216B - A kind of piece-wise linear constant current LED drive circuit - Google Patents
A kind of piece-wise linear constant current LED drive circuit Download PDFInfo
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- CN105188216B CN105188216B CN201510564489.XA CN201510564489A CN105188216B CN 105188216 B CN105188216 B CN 105188216B CN 201510564489 A CN201510564489 A CN 201510564489A CN 105188216 B CN105188216 B CN 105188216B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
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- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Abstract
The invention belongs to electronic circuit technology field, more particularly to a kind of piece-wise linear constant current LED drive circuit.The output end that circuit of the invention is mainly reference voltage generation module is connected with the positive input of operational amplifier respectively；The output termination LED unit of the rectification module, the drain electrode of the output termination NMOS power tubes of LED unit；The source electrode of NMOS tube power tube after detection resistance RS by being grounded；Output one grid of NMOS power tubes of termination of each operational amplifier；The reverse input end of all operational amplifiers after detection resistance RS by being grounded；The input termination sampling resistor of state detection module, the input of its output termination clock signal generating module；The output termination of clock signal generating module enables signaling module, enables signaling module control operational amplifier.Beneficial effects of the present invention are that by controlling, the power tube is corresponding to drive operational amplifier Enable Pin to close operational amplifier, significantly reduces the average operating current consumption of driving chip.
Description
Technical field
The invention belongs to electronic circuit technology field, more particularly to a kind of piece-wise linear constant current LED drive circuit.
Background technology
LED be it is a kind of under several volts of forward voltage can normal work and luminous device, by
The optical characteristics of LED understands that LED light spectrum will change, and LED light flux increases therewith, i.e., with the increase of forward current
Brightness increases.Luminosity and spectrum for control LED etc. generally need an electric current for stabilization.LED drive circuit presses work
Principle can be divided into switch drive and linear constant current drives.Metal-oxide-semiconductor in switch driving circuit is operated in HF switch state and whole
Individual circuit is complex, and the adjustment pipe of drive circuit is operated in continuous state in linear constant current drive circuit, rather than being operated in
The on off state of saturation and cut-off region, and required peripheral components are fewer than switch drive.Latter of which is directly driven for alternating current
It is dynamic, and be to reach power factor and efficiency higher higher, generate piece-wise linear constant current LED drive circuit.
Current piece-wise linear constant current LED drive circuit within each cycle, due to power tube be segmentation conducting, and
Drive operational amplifier to be worked all the time within the cycle, thus result in the waste of power consumption.
The content of the invention
It is to be solved by this invention, aiming above mentioned problem, propose a kind of piece-wise linear constant current LED drive circuit.
To achieve the above object, the present invention is adopted the following technical scheme that：
A kind of piece-wise linear constant current LED drive circuit, including rectification module, reference voltage generation module, power pipe die
Block and LED module, it is characterised in that also including state detection module, clock signal generating module, operational amplifier module, make
Can signaling module, initialization module, the first sampling resistor RA, the second sampling resistor RB, the input OR gates of detection resistance RS and two；Institute
Stating LED module includes the LED unit of multiple series connection；The operational amplifier module includes multiple operational amplifiers；The power
Tube module includes multiple NMOS power tubes；The quantity of the LED unit, operational amplifier and NMOS power tubes is equal；The ginseng
The output end for examining voltage generating module is connected with the positive input of each operational amplifier respectively；The output of the rectification module
First input of LED unit of termination, output one drain electrode of NMOS power tubes of termination of each LED unit；It is all of
The source electrode of NMOS tube power tube after detection resistance RS by being grounded；The output of each operational amplifier terminates a NMOS power
The grid of pipe；The reverse input end of all operational amplifiers after detection resistance RS by being grounded；The rectification module and first
The tie point of LED unit is grounded after passing sequentially through the first sampling resistor RA and the second sampling resistor RB；The state detection module
Input termination the first sampling resistor RA and the second sampling resistor RB tie point, its output termination clock signal generating module
Input；The output termination two of the clock signal generating module is input into the first input end of OR gate；The second of two input OR gates
The output end of input termination initialization module, its output termination enables the clock signal input terminal of signaling module；Enable signal mode
The output end of the input termination initialization module of block, its reset signal terminates the reset signal output end of initialization module, and its is defeated
Go out the enable signal end that end connects each operational amplifier respectively；The quantity and operation amplifier for enabling signaling module output end
The quantity of device is equal and corresponds.
Further, the quantity of the operational amplifier be 4, respectively the first operational amplifier, the second operational amplifier,
3rd operational amplifier and four-operational amplifier；Then the state monitoring module includes 8 output ends, respectively with clock signal
8 inputs of generation module are sequentially connected；The clock signal generating module is by the first buffer, the second buffer, the 3rd
Buffer, the 4th buffer, the 5th buffer, hex buffer, the 7th buffer, the 8th buffer, first resistor R1, second
Resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, first
Electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electric capacity C6, the 7th electric capacity C7, the 8th
Electric capacity C8, the first not gate NOT1, the second not gate NOT2, the 3rd not gate NOT3, the 4th not gate NOT4, the 5th not gate NOT5, the 6th
Not gate NOT6, the 7th not gate NOT7, the 8th not gate NOT8, first and door AND1, second with door AND2, the 3rd and door AND3, the
Four with door AND4, the 5th and door AND5, the 6th with door AND6, the 7th and door AND7, the 8th and door AND8, the first OR gate OR1, the
Two OR gate OR2, the 3rd OR gate OR3, the 4th OR gate OR4, the 5th OR gate OR5, the 6th OR gate OR6 and the 7th OR gate OR7；First delays
The input and first for rushing device are the first input end of clock signal generating module with the first input end of door AND1；First buffering
The output end of device is followed by the input of the first not gate NOT1 by first resistor R1；First resistor R1 and the first not gate NOT1 is input into
The tie point at end after the first electric capacity C1 by being grounded；The output termination first of the first not gate NOT1 and second input of door AND1
End；First first input end that the first OR gate OR1 is terminated with the output of door AND1；The input of the second buffer and second and door
The first input end of AND2 is the second input of clock signal generating module；The output end of the second buffer passes through second resistance
R2 is followed by the input of the second not gate NOT2；The tie point of second resistance R2 and the second not gate NOT2 inputs passes through the second electric capacity
It is grounded after C2；The output termination second of the second not gate NOT2 and second input of door AND2；The output end of second and door AND2
Connect second input of the first OR gate OR1；The first input end of the 5th OR gate OR5 of output termination of the first OR gate OR1；3rd delays
The input and the 3rd for rushing device are the 3rd input of clock signal generating module with the first input end of door AND3；3rd buffering
The output end of device is followed by the input of the 3rd not gate NOT3 by 3rd resistor R3；3rd resistor R3 and the 3rd not gate NOT3 is input into
The tie point at end after the 3rd electric capacity C3 by being grounded；The output termination the 3rd of the 3rd not gate NOT3 and second input of door AND3
End；3rd first input end that the second OR gate OR2 is terminated with the output of door AND3；The input and the 4th and door of the 4th buffer
The first input end of AND4 is the 4th input of clock signal generating module；The output end of the 4th buffer passes through the 4th resistance
R4 is followed by the input of the 4th not gate NOT4；The tie point of the 4th resistance R4 and the 4th not gate NOT4 inputs passes through the 4th electric capacity
It is grounded after C4；The output termination the 4th of the 4th not gate NOT4 and second input of door AND4；The output end of the 4th and door AND4
Connect second input of the second OR gate OR2；Second input of the 5th OR gate OR5 of output termination of the second OR gate OR2；5th or
The first input end of the 7th OR gate OR7 of output termination of door OR5；The input of the 5th buffer and the 5th and the first of door AND5
Input is the 5th input of clock signal generating module；The output end of the 5th buffer is followed by the 5th by the 5th resistance R5
The input of not gate NOT5；The tie point of the 5th resistance R5 and the 5th not gate NOT5 inputs after the 5th electric capacity C5 by being grounded；
The output termination the 5th of the 5th not gate NOT5 and second input of door AND5；5th terminates the 3rd OR gate with the output of door AND5
The first input end of OR3；The input of hex buffer and the 6th is clock signal generation mould with the first input end of door AND6
6th input of block；The output end of hex buffer is followed by the input of the 6th not gate NOT6 by the 6th resistance R6；6th
The tie point of resistance R6 and the 6th not gate NOT6 inputs after the 6th electric capacity C6 by being grounded；The output termination of the 6th not gate NOT6
Second input of the 6th and door AND6；6th the second input that the 3rd OR gate OR3 is terminated with the output of door AND6；3rd or
The first input end of the 6th OR gate OR6 of output termination of door OR3；The input of the 7th buffer and the 7th and the first of door AND7
Input is the 7th input of clock signal generating module；The output end of the 7th buffer is followed by the 7th by the 7th resistance R7
The input of not gate NOT7；The tie point of the 7th resistance R7 and the 7th not gate NOT7 inputs after the 7th electric capacity C7 by being grounded；
The output termination the 7th of the 7th not gate NOT7 and second input of door AND7；7th terminates the 4th OR gate with the output of door AND7
The first input end of OR；The input of the 8th buffer and the 8th is clock signal generating module with the first input end of door AND8
The 8th input；The output end of the 8th buffer is followed by the input of the 8th not gate NOT8 by the 8th resistance R8；8th electricity
The tie point of resistance R8 and the 8th not gate NOT8 inputs after the 8th electric capacity C8 by being grounded；The output termination the of the 8th not gate NOT8
Second input of eight and door AND8；8th the second input that the 4th OR gate OR4 is terminated with the output of door AND8；4th OR gate
Second input of the 6th OR gate OR6 of output termination of OR4；Second output of the 7th OR gate R7 of output termination of the 6th OR gate O6
End；The output end of the 7th OR gate OR7 is the output end of clock signal generating module.
Further, the initialization module is by the 9th resistance R9, the tenth resistance R10, the first PMOS MP1, second
PMOS MP2, the 3rd PMOS MP3, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube
MN4 and the 9th electric capacity C9 is constituted；The 9th electric capacity C9 and the tenth resistance R10 connects, another termination power of the 9th electric capacity C9,
The other end ground connection of the tenth resistance R10；The grid of the first NMOS tube MN1 connects being connected to for the 9th electric capacity C9 and the tenth resistance R10,
Its drain electrode is followed by power supply by the 9th resistance R9, its source ground；The source electrode of the first PMOS MP1 connects power supply, and its grid connects
The tie point that one NMOS tube MN1 drains with the 9th resistance R9, its drain electrode connects the drain electrode of the second NMOS tube MN2；Second NMOS tube MN2
Grid connect the first NMOS tube MN1 drain electrodes and the tie point of the 9th resistance R9, its source ground；The source electrode of the second PMOS MP2
Power supply is connect, its grid connects the tie point of the drain electrode of the first PMOS and the drain electrode of the second NMOS tube, its drain electrode connects the 3rd NMOS tube MN3's
Drain electrode；The grid of the 3rd NMOS tube MN3 connects the tie point of the drain electrode of the first PMOS and the drain electrode of the second NMOS tube, its source ground；
The source electrode of the 3rd PMOS MP3 connects power supply, and its grid connects the connection of the second PMOS MP2 drain electrodes and the 3rd NMOS tube MN3 drain electrodes
Point, its drain electrode connects the drain electrode of the 4th NMOS tube MN4；The grid of the 4th NMOS tube MN4 connects the second PMOS MP2 drain electrodes and the 3rd
The tie point of NMOS tube MN3 drain electrodes, its source ground；Second PMOS MP2 drain electrodes, the 3rd NMOS tube MN3 drain electrodes, the 3rd PMOS
The tie point of pipe MP3 grids and the 4th NMOS tube MN4 grids is the reset signal output end of initialization module, the 3rd PMOS
It is the output end of initialization module that MP3 drains with the tie point of the 4th NMOS tube MN4 drain electrodes.
Further, the enable signaling module is by the first d type flip flop, the second d type flip flop, 3d flip-flop, the 4th D
Trigger, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, the 8th d type flip flop, the 8th OR gate OR8, the 9th OR gate
OR9, the tenth OR gate OR10 and the 11st OR gate OR11 are constituted；The clock signal input terminal interconnection of all d type flip flops is simultaneously defeated with two
Enter the output end connection of OR gate；The output end of the D input termination initialization modules of the first d type flip flop, its Q output meets the 2nd D
The D inputs of trigger；The Q output of the second d type flip flop connects the D inputs of 3d flip-flop；The Q outputs of scattered d type flip flop
Terminate the D inputs of four d flip-flop；The Q output of four d flip-flop connects the D inputs of the 5th d type flip flop；5th D is triggered
The Q output of device connects the D inputs of the 6th d type flip flop；The Q output of the 6th d type flip flop connects the D inputs of the 7th d type flip flop；
The Q output of the 7th d type flip flop connects the D inputs of the 8th d type flip flop；The first input end of the 8th OR gate OR8 connects D triggerings
The tie point of device Q output and the second d type flip flop D inputs, its second input termination the second d type flip flop Q output and the 3rd D
The tie point of trigger D inputs, its 3rd input the 7th d type flip flop Q output of termination and the 8th d type flip flop D inputs
Tie point, the Q output of its 4th input the 8th d type flip flop of termination, its output end output first enables signal and connects the first fortune
Calculate the enable signal end of amplifier；The first input end of the 9th OR gate OR9 connects the second d type flip flop Q output and 3d flip-flop
The tie point of the tie point of D inputs, its second input termination 3d flip-flop Q output and four d flip-flop D inputs,
The tie point of its 3rd input termination the 6th d type flip flop Q output and the 7th d type flip flop D inputs, its 4th input terminates the
The tie point of seven d type flip flop Q outputs and the 8th d type flip flop D inputs, its output end output second enables signal and connects second
The enable signal end of operational amplifier；The first input end of the tenth OR gate OR10 connects 3d flip-flop Q output and the 4th D is touched
The tie point of device D inputs is sent out, the company of its second input termination four d flip-flop Q output and the 5th d type flip flop D inputs
The tie point of contact, its 3rd input the 5th d type flip flop Q output of termination and the 6th d type flip flop D inputs, its 4th input
The tie point of the 6th d type flip flop Q output and the 7th d type flip flop D inputs is terminated, its output end output the 3rd enables signal simultaneously
Connect the enable signal end of the 3rd operational amplifier；The first input end of the 11st OR gate OR11 connect four d flip-flop Q output with
The tie point of the 5th d type flip flop D inputs, the second input termination the 5th d type flip flop Q output and the 6th d type flip flop D inputs
Tie point, its output end output the 4th enables signal and connects the enable signal end of four-operational amplifier.
Beneficial effects of the present invention are, when power tube no current passes through, control the corresponding driving computing of the power tube to put
Big device Enable Pin closes operational amplifier, significantly reduces the average operating current consumption of driving chip, reduces driving chip
Power consumption, improve circuit efficiency.
Brief description of the drawings
Fig. 1 is a kind of piece-wise linear constant current LED drive circuit schematic block diagram of the invention；
Fig. 2 is state detection module structural representation；
Fig. 3 is state detection unit effect diagram；
Fig. 4 is the structural representation of clock generation module；
Fig. 5 is initialization module structural representation；
Fig. 6 is the structural representation for enabling signaling module；
Fig. 7 is operational amplifier enable signal control effect schematic diagram in the present invention.
Specific embodiment
With reference to the accompanying drawings and examples, technical scheme is described in detail：
A kind of piece-wise linear constant current LED drive circuit of the invention, as shown in figure 1, including rectification module, reference voltage
Generation module, power tube module and LED module, it is characterised in that also including state detection module, clock signal generating module,
Operational amplifier module, enable signaling module, initialization module, the first sampling resistor RA, the second sampling resistor RB, detection resistance
The input OR gates of RS and two；The LED module includes the LED unit of multiple series connection；The operational amplifier module includes multiple fortune
Calculate amplifier；The power tube module includes multiple NMOS power tubes；The LED unit, operational amplifier and NMOS power tubes
Quantity it is equal；The output end of the reference voltage generation module is connected with the positive input of each operational amplifier respectively；
Output first input of LED unit of termination of the rectification module, the output of each LED unit terminates a NMOS power
The drain electrode of pipe；The source electrode of all of NMOS tube power tube after detection resistance RS by being grounded；The output of each operational amplifier
One grid of NMOS power tubes of termination；The reverse input end of all operational amplifiers after detection resistance RS by being grounded；It is described
The tie point of rectification module and first LED unit is grounded after passing sequentially through the first sampling resistor RA and the second sampling resistor RB；
The tie point of the input termination first sampling resistor RA and the second sampling resistor RB of the state detection module, during its output termination
The input of clock signal generator module；The output termination two of the clock signal generating module is input into the first input end of OR gate；
The output end of the second input termination initialization module of two input OR gates, the clock signal that its output termination enables signaling module is defeated
Enter end；The output end of the input termination initialization module of signaling module is enabled, its reset signal terminates the reset of initialization module
Signal output part, its output end connects the enable signal end of each operational amplifier respectively；The enable signaling module output end
Quantity it is equal with the quantity of operational amplifier and correspond.
Embodiment
The quantity of operational amplifier is 4 in this example, respectively the first operational amplifier, the second operational amplifier, the 3rd fortune
Calculate amplifier and four-operational amplifier；Then the state monitoring module includes 8 output ends, produces mould with clock signal respectively
8 inputs of block are sequentially connected；As shown in figure 4, the clock signal generating module by the first buffer, the second buffer,
3rd buffer, the 4th buffer, the 5th buffer, hex buffer, the 7th buffer, the 8th buffer, first resistor R1,
Second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8,
First electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electric capacity C6, the 7th electric capacity C7,
8th electric capacity C8, the first not gate NOT1, the second not gate NOT2, the 3rd not gate NOT3, the 4th not gate NOT4, the 5th not gate NOT5,
6th not gate NOT6, the 7th not gate NOT7, the 8th not gate NOT8, first and door AND1, second and door AND2, the 3rd and door
AND3, the 4th and door AND4, the 5th with door AND5, the 6th and door AND6, the 7th and door AND7, the 8th and door AND8, first or
Door OR1, the second OR gate OR2, the 3rd OR gate OR3, the 4th OR gate OR4, the 5th OR gate OR5, the 6th OR gate OR6 and the 7th OR gate
OR7；The input of the first buffer and first is the first input of clock signal generating module with the first input end of door AND1
End；The output end of the first buffer is followed by the input of the first not gate NOT1 by first resistor R1；First resistor R1 and first
The tie point of not gate NOT1 inputs after the first electric capacity C1 by being grounded；Output termination first and the door AND1 of the first not gate NOT1
The second input；First first input end that the first OR gate OR1 is terminated with the output of door AND1；The input of the second buffer
It is the second input of clock signal generating module with the first input end of door AND2 with second；The output end of the second buffer is led to
Cross the input that second resistance R1 is followed by the second not gate NOT2；The tie point of second resistance R2 and the second not gate NOT2 inputs leads to
It is grounded after crossing the second electric capacity C2；The output termination second of the second not gate NOT2 and second input of door AND2；Second and door
Second input of the first OR gate OR1 of output termination of AND2；The first of the 5th OR gate OR5 of output termination of the first OR gate OR1
Input；The input of the 3rd buffer and the 3rd the 3rd defeated for clock signal generating module with the first input end of door AND3
Enter end；The output end of the 3rd buffer is followed by the input of the 3rd not gate NOT3 by 3rd resistor R3；3rd resistor R3 and
The tie point of three not gate NOT3 inputs after the 3rd electric capacity C3 by being grounded；The output of the 3rd not gate NOT3 terminates the 3rd and door
Second input of AND3；3rd first input end that the second OR gate OR2 is terminated with the output of door AND3；4th buffer it is defeated
It is the 4th input of clock signal generating module with the first input end of door AND4 to enter end and the 4th；The output of the 4th buffer
End is followed by the input of the 4th not gate NOT4 by the 4th resistance R4；The connection of the 4th resistance R4 and the 4th not gate NOT4 inputs
Point after the 4th electric capacity C4 by being grounded；The output termination the 4th of the 4th not gate NOT4 and second input of door AND4；4th with
Second input of the second OR gate OR2 of output termination of door AND4；The of the 5th OR gate OR5 of output termination of the second OR gate OR2
Two inputs；The first input end of the 7th OR gate OR7 of output termination of the 5th OR gate OR5；The input of the 5th buffer and
Five is the 5th input of clock signal generating module with the first input end of door AND5；The output end of the 5th buffer is by the
Five resistance R5 are followed by the input of the 5th not gate NOT5；The tie point of the 5th resistance R5 and the 5th not gate NOT5 inputs is by the
It is grounded after five electric capacity C5；The output termination the 5th of the 5th not gate NOT5 and second input of door AND5；5th with door AND5's
The first input end of the 3rd OR gate OR3 of output termination；The first input end of the input of hex buffer and the 6th and door AND6
It is the 6th input of clock signal generating module；The output end of hex buffer is followed by the 6th not gate by the 6th resistance R6
The input of NOT6；The tie point of the 6th resistance R6 and the 6th not gate NOT6 inputs after the 6th electric capacity C6 by being grounded；6th
The output termination the 6th of not gate NOT6 and second input of door AND6；6th terminates the 3rd OR gate OR3 with the output of door AND6
The second input；The first input end of the 6th OR gate OR6 of output termination of the 3rd OR gate OR3；The input of the 7th buffer
It is the 7th input of clock signal generating module with the first input end of door AND7 with the 7th；The output end of the 7th buffer is led to
Cross the input that the 7th resistance R7 is followed by the 7th not gate NOT7；The tie point of the 7th resistance R7 and the 7th not gate NOT7 inputs leads to
It is grounded after crossing the 7th electric capacity C7；The output termination the 7th of the 7th not gate NOT7 and second input of door AND7；7th and door
The first input end of the 4th OR gate OR of output termination of AND7；The input of the 8th buffer and the 8th defeated with the first of door AND8
It is the 8th input of clock signal generating module to enter end；It is non-that the output end of the 8th buffer is followed by the 8th by the 8th resistance R8
The input of door NOT8；The tie point of the 8th resistance R8 and the 8th not gate NOT8 inputs after the 8th electric capacity C8 by being grounded；The
The output termination the 8th of eight not gate NOT8 and second input of door AND8；8th terminates the 4th OR gate with the output of door AND8
Second input of OR4；Second input of the 6th OR gate OR6 of output termination of the 4th OR gate OR4；The output of the 6th OR gate O6
Terminate second output end of the 7th OR gate R7；The output end of the 7th OR gate OR7 is the output end of clock signal generating module.
As shown in figure 5, the initialization module is by the 9th resistance R9, the tenth resistance R10, the first PMOS MP1, second
PMOS MP2, the 3rd PMOS MP3, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube
MN4 and the 9th electric capacity C9 is constituted；The 9th electric capacity C9 and the tenth resistance R10 connects, another termination power of the 9th electric capacity C9,
The other end ground connection of the tenth resistance R10；The grid of the first NMOS tube MN1 connects being connected to for the 9th electric capacity C9 and the tenth resistance R10,
Its drain electrode is followed by power supply by the 9th resistance R9, its source ground；The source electrode of the first PMOS MP1 connects power supply, and its grid connects
The tie point that one NMOS tube MN1 drains with the 9th resistance R9, its drain electrode connects the drain electrode of the second NMOS tube MN2；Second NMOS tube MN2
Grid connect the first NMOS tube MN1 drain electrodes and the tie point of the 9th resistance R9, its source ground；The source electrode of the second PMOS MP2
Power supply is connect, its grid connects the tie point of the drain electrode of the first PMOS and the drain electrode of the second NMOS tube, its drain electrode connects the 3rd NMOS tube MN3's
Drain electrode；The grid of the 3rd NMOS tube MN3 connects the tie point of the drain electrode of the first PMOS and the drain electrode of the second NMOS tube, its source ground；
The source electrode of the 3rd PMOS MP3 connects power supply, and its grid connects the connection of the second PMOS MP2 drain electrodes and the 3rd NMOS tube MN3 drain electrodes
Point, plays the drain electrode that drain electrode meets the 4th NMOS tube MN4；The grid of the 4th NMOS tube MN4 connects the second PMOS MP2 drain electrodes and the 3rd
The tie point of NMOS tube MN3 drain electrodes, its source ground；Second PMOS MP2 drain electrodes, the 3rd NMOS tube MN3 drain electrodes, the 3rd PMOS
The tie point of pipe MP3 grids and the 4th NMOS tube MN4 grids is the reset signal output end of initialization module, the 3rd PMOS
It is the output end of initialization module that MP3 drains with the tie point of the 4th NMOS tube MN4 drain electrodes.
As shown in fig. 6, the enable signaling module is by the first d type flip flop, the second d type flip flop, 3d flip-flop, the 4th D
Trigger, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, the 8th d type flip flop, the 8th OR gate OR8, the 9th OR gate
OR9, the tenth OR gate OR10 and the 11st OR gate OR11 are constituted；The clock signal input terminal interconnection of all d type flip flops is simultaneously defeated with two
Enter the output end connection of OR gate；The output end of the D input termination initialization modules of the first d type flip flop, its Q output meets the 2nd D
The D inputs of trigger；The Q output of the second d type flip flop connects the D inputs of 3d flip-flop；The Q outputs of scattered d type flip flop
Terminate the D inputs of four d flip-flop；The Q output of four d flip-flop connects the D inputs of the 5th d type flip flop；5th D is triggered
The Q output of device connects the D inputs of the 6th d type flip flop；The Q output of the 6th d type flip flop connects the D inputs of the 7th d type flip flop；
The Q output of the 7th d type flip flop connects the D inputs of the 8th d type flip flop；The first input end of the 8th OR gate OR8 connects D triggerings
The tie point of device Q output and the second d type flip flop D inputs, its second input termination the second d type flip flop Q output and the 3rd D
The tie point of trigger D inputs, its 3rd input the 7th d type flip flop Q output of termination and the 8th d type flip flop D inputs
Tie point, the Q output of its 4th input the 8th d type flip flop of termination, its output end output first enables signal and connects the first fortune
Calculate the enable signal end of amplifier；The first input end of the 9th OR gate OR9 connects the second d type flip flop Q output and 3d flip-flop
The tie point of the tie point of D inputs, its second input termination 3d flip-flop Q output and four d flip-flop D inputs,
The tie point of its 3rd input termination the 6th d type flip flop Q output and the 7th d type flip flop D inputs, its 4th input terminates the
The tie point of seven d type flip flop Q outputs and the 8th d type flip flop D inputs, its output end output second enables signal and connects second
The enable signal end of operational amplifier；The first input end of the tenth OR gate OR10 connects 3d flip-flop Q output and the 4th D is touched
The tie point of device D inputs is sent out, the company of its second input termination four d flip-flop Q output and the 5th d type flip flop D inputs
The tie point of contact, its 3rd input the 5th d type flip flop Q output of termination and the 6th d type flip flop D inputs, its output end is defeated
Go out the 3rd enable signal and connect the enable signal end of the 3rd operational amplifier；The first input end of the 11st OR gate OR11 connects the 4th
The tie point of d type flip flop Q output and the 5th d type flip flop D inputs, the second input the 5th d type flip flop Q output of termination and the
The tie point of six d type flip flop D inputs, its output end output the 4th enables signal and connects the enable signal of four-operational amplifier
End.
The operation principle of this example is：
As shown in Fig. 2 state detection module specifically includes state detection unit 1-8 in this example, state detection unit 1-8 is defeated
Enter the voltage Vtest on sample resistance RB, output T1-T8 is signally attached to clock generation module, the output of clock generation module with
EN modules are acted on after initialization module output computing, EN modules are produced and enable signal EN1-EN4 enable operational amplifiers OP1-
OP4；Operational amplifier OP1-OP4 forward ends connect the output VREF1-VREF4 of reference voltage generation module, end of oppisite phase and detection
Resistance Rs is connected, output connection power tube MN1-MN4 grids；LED1-LED4 is sequentially connected in series, and its each negative electrode connect respectively
The drain electrode of the MN1-MN4, the anode of the first LED string connects the input voltage of full-wave rectification.Due to reference voltage VREF1<
VREF2<VREF3<VREF4, as full-wave rectified voltage gradually rises, the MN2, MN3, MN4, MN5 will be turned on one by one, then taken
Voltage changes as shown in the Vtest of Fig. 3 on sample resistance RB.
State detection unit 1-4 detects input voltage propradation respectively, works as Vtest>During V1, detection unit 1 exports height
Level；State detection unit 5-8 detects that input voltage declines state respectively；When Vtest is in decline state and Vtest<
During V5, the output high level of detection unit 5.
If Fig. 3 is state detection unit 1-8 effect diagrams.As illustrated, working as Vtest>During V1, detection unit 1 is exported
High level；Work as Vtest>During V2, the output high level of detection unit 2；Work as Vtest>During V3, the output high level of detection unit 3；When
Vtest>During V4, the output high level of detection unit 4；When Vtest is in decline state and Vtest<During V5, detection unit 5 is exported
High level.When Vtest is in decline state and Vtest<During V6, the output high level of detection unit 6.Decline shape when Vtest is in
State and Vtest<During V7, the output high level of detection unit 7.When Vtest is in decline state and Vtest<During V8, detection unit 8
Output high level.
As shown in figure 4, the clock generation module is input into T1 signals to two inputs and door AND1, while T1 inputs are connected
Buffer buffer1 connects R1, R1 other ends connection electric capacity C1 and to connect phase inverter NOT1, T1 and NOT1 output signal defeated through two
Enter and be input into OR gate OR1 with door AND1 inputs two.T2-T8 is the repeat unit of T1, and it is defeated that two inputs are respectively its with door AND2-AND8
Go out.AND1 and AND2 is input to OR1；AND3 and AND4 is input to OR2；AND5 and AND6 is input to OR3；AND7 and AND8 is input into
To OR4.OR1 and OR2 are exported to be carried out or computing as the inputs of two input OR gate OR5, OR3 and OR4 export as two inputs or
The input of door OR6 is carried out or computing, OR7 output CLK_TEST signals.When in 8 output signal T1-T8 of state detection module certain
When low level is changed into high level, clock generation module produces a rising edge clock signal for individual output.
As shown in fig. 7, it is operational amplifier enable signal control effect schematic diagram in the present invention to be, wherein solid line is driving
Operational amplifier enables signal EN1-EN4 waveforms, and dotted line is the enable signal that the existing property of traditional segmentation drives, it is seen that phase of the present invention
The working time for driving amplifier is significantly reduced for conventional art.
Claims (1)
1. a kind of piece-wise linear constant current LED drive circuit, including rectification module, reference voltage generation module, power tube module
And LED module, it is characterised in that also including state detection module, clock signal generating module, operational amplifier module, enable
Signaling module, initialization module, the first sampling resistor RA, the second sampling resistor RB, the input OR gates of detection resistance RS and two；It is described
LED module includes the LED unit of multiple series connection；The operational amplifier module includes multiple operational amplifiers；The power tube
Module includes multiple NMOS power tubes；The quantity of the LED unit, operational amplifier and NMOS power tubes is equal；The reference
The output end of voltage generating module is connected with the positive input of each operational amplifier respectively；The output end of the rectification module
Connect first input of LED unit, output one drain electrode of NMOS power tubes of termination of each LED unit；All of NMOS
The source electrode of tube power pipe after detection resistance RS by being grounded；Output one NMOS power tube of termination of each operational amplifier
Grid；The reverse input end of all operational amplifiers after detection resistance RS by being grounded；The rectification module and first LED are mono-
The tie point of unit is grounded after passing sequentially through the first sampling resistor RA and the second sampling resistor RB；The input of the state detection module
The tie point of the first sampling resistor RA and the second sampling resistor RB is terminated, the input of its output termination clock signal generating module
End；The output termination two of the clock signal generating module is input into the first input end of OR gate；Second input of two input OR gates
The output end of initialization module is terminated, its output termination enables the clock signal input terminal of signaling module；Enable signaling module
The output end of input termination initialization module, its reset signal terminates the reset signal output end of initialization module, its output end
The enable signal end of each operational amplifier is connect respectively；The quantity for enabling signaling module output end and operational amplifier
Quantity is equal and corresponds；
The quantity of the operational amplifier is 4, respectively the first operational amplifier, the second operational amplifier, the 3rd operation amplifier
Device and four-operational amplifier；Then the state detection module includes 8 output ends, respectively with the 8 of clock signal generating module
Individual input is sequentially connected；The clock signal generating module is by the first buffer, the second buffer, the 3rd buffer, the 4th
Buffer, the 5th buffer, hex buffer, the 7th buffer, the 8th buffer, first resistor R1, second resistance R2, the 3rd
Resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the first electric capacity C1, second
Electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electric capacity C6, the 7th electric capacity C7, the 8th electric capacity C8, first
Not gate NOT1, the second not gate NOT2, the 3rd not gate NOT3, the 4th not gate NOT4, the 5th not gate NOT5, the 6th not gate NOT6,
Seven not gate NOT7, the 8th not gate NOT8, first and door AND1, second and door AND2, the 3rd and door AND3, the 4th and door AND4,
5th with door AND5, the 6th and door AND6, the 7th and door AND7, the 8th and door AND8, the first OR gate OR1, the second OR gate OR2,
3rd OR gate OR3, the 4th OR gate OR4, the 5th OR gate OR5, the 6th OR gate OR6 and the 7th OR gate OR7；The input of the first buffer
End and first is the first input end of clock signal generating module with the first input end of door AND1；The output end of the first buffer
The input of the first not gate NOT1 is followed by by first resistor R1；The tie point of first resistor R1 and the first not gate NOT1 inputs
By being grounded after the first electric capacity C1；The output termination first of the first not gate NOT1 and second input of door AND1；First and door
The first input end of the first OR gate OR1 of output termination of AND1；The input of the second buffer and second and the first of door AND2
Input is the second input of clock signal generating module；The output end of the second buffer is followed by second by second resistance R2
The input of not gate NOT2；The tie point of second resistance R2 and the second not gate NOT2 inputs after the second electric capacity C2 by being grounded；
The output termination second of the second not gate NOT2 and second input of door AND2；Second terminates the first OR gate with the output of door AND2
Second input of OR1；The first input end of the 5th OR gate OR5 of output termination of the first OR gate OR1；The input of the 3rd buffer
End and the 3rd is the 3rd input of clock signal generating module with the first input end of door AND3；The output end of the 3rd buffer
The input of the 3rd not gate NOT3 is followed by by 3rd resistor R3；The tie point of 3rd resistor R3 and the 3rd not gate NOT3 inputs
By being grounded after the 3rd electric capacity C3；The output termination the 3rd of the 3rd not gate NOT3 and second input of door AND3；3rd and door
The first input end of the second OR gate OR2 of output termination of AND3；The input of the 4th buffer and the 4th and the first of door AND4
Input is the 4th input of clock signal generating module；The output end of the 4th buffer is followed by the 4th by the 4th resistance R4
The input of not gate NOT4；The tie point of the 4th resistance R4 and the 4th not gate NOT4 inputs after the 4th electric capacity C4 by being grounded；
The output termination the 4th of the 4th not gate NOT4 and second input of door AND4；4th terminates the second OR gate with the output of door AND4
Second input of OR2；Second input of the 5th OR gate OR5 of output termination of the second OR gate OR2；5th OR gate OR5's is defeated
Go out the first input end of the 7th OR gate OR7 of termination；The input of the 5th buffer and the 5th is with the first input end of door AND5
5th input of clock signal generating module；The output end of the 5th buffer is followed by the 5th not gate NOT5 by the 5th resistance R5
Input；The tie point of the 5th resistance R5 and the 5th not gate NOT5 inputs after the 5th electric capacity C5 by being grounded；5th not gate
The output termination the 5th of NOT5 and second input of door AND5；5th and the of the 3rd OR gate OR3 of output termination of door AND5
One input；The input of hex buffer and the 6th is the 6th of clock signal generating module with the first input end of door AND6
Input；The output end of hex buffer is followed by the input of the 6th not gate NOT6 by the 6th resistance R6；6th resistance R6 with
The tie point of the 6th not gate NOT6 inputs after the 6th electric capacity C6 by being grounded；The output of the 6th not gate NOT6 terminates the 6th and door
Second input of AND6；6th the second input that the 3rd OR gate OR3 is terminated with the output of door AND6；3rd OR gate OR3's
The first input end of the 6th OR gate OR6 of output termination；The first input end of the input of the 7th buffer and the 7th and door AND7
It is the 7th input of clock signal generating module；The output end of the 7th buffer is followed by the 7th not gate by the 7th resistance R7
The input of NOT7；The tie point of the 7th resistance R7 and the 7th not gate NOT7 inputs after the 7th electric capacity C7 by being grounded；7th
The output termination the 7th of not gate NOT7 and second input of door AND7；7th with the 4th OR gate OR's of output termination of door AND7
First input end；The input of the 8th buffer and the 8th is the of clock signal generating module with the first input end of door AND8
Eight inputs；The output end of the 8th buffer is followed by the input of the 8th not gate NOT8 by the 8th resistance R8；8th resistance R8
With the tie point of the 8th not gate NOT8 inputs by being grounded after the 8th electric capacity C8；8th not gate NOT8 output termination the 8th with
Second input of door AND8；8th the second input that the 4th OR gate OR4 is terminated with the output of door AND8；4th OR gate OR4
Output termination the 6th OR gate OR6 the second input；Second output end of the 7th OR gate R7 of output termination of the 6th OR gate O6；
The output end of the 7th OR gate OR7 is the output end of clock signal generating module；
The initialization module is by the 9th resistance R9, the tenth resistance R10, the first PMOS MP1, the second PMOS MP2, the 3rd
PMOS MP3, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4 and the 9th electric capacity C9
Constitute；The 9th electric capacity C9 and the tenth resistance R10 connects, and another termination power of the 9th electric capacity C9, the tenth resistance R10's is another
One end is grounded；The grid of the first NMOS tube MN1 connects being connected to for the 9th electric capacity C9 and the tenth resistance R10, and its drain electrode passes through the 9th
Resistance R9 is followed by power supply, its source ground；The source electrode of the first PMOS MP1 connects power supply, and its grid connects the first NMOS tube MN1 drain electrodes
With the tie point of the 9th resistance R9, it drains and connects the drain electrode of the second NMOS tube MN2；The grid of the second NMOS tube MN2 connects first
The tie point that NMOS tube MN1 drains with the 9th resistance R9, its source ground；The source electrode of the second PMOS MP2 connects power supply, its grid
The tie point of the drain electrode of the first PMOS and the drain electrode of the second NMOS tube is connect, its drain electrode connects the drain electrode of the 3rd NMOS tube MN3；3rd NMOS
The grid of pipe MN3 connects the tie point of the drain electrode of the first PMOS and the drain electrode of the second NMOS tube, its source ground；3rd PMOS MP3
Source electrode connect power supply, its grid connects the tie point of the second PMOS MP2 drain electrodes and the 3rd NMOS tube MN3 drain electrodes, and its drain electrode connects the
The drain electrode of four NMOS tube MN4；The grid of the 4th NMOS tube MN4 connects the second PMOS MP2 drain electrodes with the 3rd NMOS tube MN3 drain electrodes
Tie point, its source ground；Second PMOS MP2 drain electrodes, the 3rd NMOS tube MN3 drain electrodes, the 3rd PMOS MP3 grids and the 4th
The tie point of NMOS tube MN4 grids is the reset signal output end of initialization module, the 3rd PMOS MP3 drain electrodes and the 4th NMOS
The tie point of pipe MN4 drain electrodes is the output end of initialization module；
The enable signaling module is touched by the first d type flip flop, the second d type flip flop, 3d flip-flop, four d flip-flop, the 5th D
Hair device, the 6th d type flip flop, the 7th d type flip flop, the 8th d type flip flop, the 8th OR gate OR8, the 9th OR gate OR9, the tenth OR gate OR10
Constituted with the 11st OR gate OR11；The clock signal input terminal interconnection of all d type flip flops simultaneously connects with the output end of two input OR gates
Connect；The output end of the D input termination initialization modules of the first d type flip flop, its Q output connects the D inputs of the second d type flip flop；
The Q output of the second d type flip flop connects the D inputs of 3d flip-flop；The Q output of scattered d type flip flop connects four d flip-flop
D inputs；The Q output of four d flip-flop connects the D inputs of the 5th d type flip flop；The Q output of the 5th d type flip flop connects
The D inputs of six d type flip flops；The Q output of the 6th d type flip flop connects the D inputs of the 7th d type flip flop；The Q of the 7th d type flip flop
The D inputs of output the 8th d type flip flop of termination；The first input end of the 8th OR gate OR8 connects the first d type flip flop Q output and
The tie point of 2-D trigger D inputs, its second input termination the second d type flip flop Q output and 3d flip-flop D inputs
Tie point, its 3rd input termination the 7th d type flip flop Q output and the 8th d type flip flop D inputs tie point, it the 4th
The Q output of input the 8th d type flip flop of termination, its output end output first enables signal and connects the enable of the first operational amplifier
Signal end；The first input end of the 9th OR gate OR9 connects the connection of the second d type flip flop Q output and 3d flip-flop D inputs
The tie point of point, its second input termination 3d flip-flop Q output and four d flip-flop D inputs, its 3rd input
The tie point of the 6th d type flip flop Q output and the 7th d type flip flop D inputs is connect, the 7th d type flip flop Q is defeated for its 4th input termination
Go out the tie point at end and the 8th d type flip flop D inputs, its output end output second enables signal and connects the second operational amplifier
Enable signal end；The first input end of the tenth OR gate OR10 connects 3d flip-flop Q output and four d flip-flop D inputs
The tie point of tie point, its second input termination four d flip-flop Q output and the 5th d type flip flop D inputs, it is the 3rd defeated
Enter the tie point of the 5th d type flip flop Q output of termination and the 6th d type flip flop D inputs, its 4th input termination the 6th D triggering
The tie point of device Q output and the 7th d type flip flop D inputs, its output end output the 3rd enables signal and connects the 3rd computing and puts
The enable signal end of big device；The first input end of the 11st OR gate OR11 meets four d flip-flop Q output and the 5th d type flip flop D
The tie point of the tie point of input, the second input the 5th d type flip flop Q output of termination and the 6th d type flip flop D inputs, its
Output end output the 4th enables signal and connects the enable signal end of four-operational amplifier.
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| CN201510564489.XA CN105188216B (en) | 2015-09-07 | 2015-09-07 | A kind of piece-wise linear constant current LED drive circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510564489.XA CN105188216B (en) | 2015-09-07 | 2015-09-07 | A kind of piece-wise linear constant current LED drive circuit |
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| CN105188216B true CN105188216B (en) | 2017-06-30 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103188854A (en) * | 2011-12-30 | 2013-07-03 | 美格纳半导体有限公司 | LED driver circuit and light apparatus having the same |
| US20140055050A1 (en) * | 2012-08-21 | 2014-02-27 | Hung-Chi Chu | Apparatus for driving a plurality of segments of led-based lighting units |
| CN104272875A (en) * | 2012-04-02 | 2015-01-07 | 硅工厂股份有限公司 | Light-emitting diode driving circuit and light-emitting diode lighting device including same |
| CN104602391A (en) * | 2013-10-31 | 2015-05-06 | 三星电机株式会社 | Light emitting diode driving apparatus |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015106566A (en) * | 2013-11-28 | 2015-06-08 | 松男 市橋 | Led drive circuit |
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2015
- 2015-09-07 CN CN201510564489.XA patent/CN105188216B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103188854A (en) * | 2011-12-30 | 2013-07-03 | 美格纳半导体有限公司 | LED driver circuit and light apparatus having the same |
| CN104272875A (en) * | 2012-04-02 | 2015-01-07 | 硅工厂股份有限公司 | Light-emitting diode driving circuit and light-emitting diode lighting device including same |
| US20140055050A1 (en) * | 2012-08-21 | 2014-02-27 | Hung-Chi Chu | Apparatus for driving a plurality of segments of led-based lighting units |
| CN104602391A (en) * | 2013-10-31 | 2015-05-06 | 三星电机株式会社 | Light emitting diode driving apparatus |
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