CN105182088A - Amplified field intensity detection circuit - Google Patents
Amplified field intensity detection circuit Download PDFInfo
- Publication number
- CN105182088A CN105182088A CN201510316261.9A CN201510316261A CN105182088A CN 105182088 A CN105182088 A CN 105182088A CN 201510316261 A CN201510316261 A CN 201510316261A CN 105182088 A CN105182088 A CN 105182088A
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- China
- Prior art keywords
- resistance
- power amplifier
- sheffer stroke
- stroke gate
- pin
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses an amplified field intensity detection circuit, which is characterized by comprising a power amplifier P1, an NAND gate IC1, an NAND gate IC2, an NAND gate IC3, an integrated block U1, a power amplifier P2, a polarity capacitor C1, a resistor R1, a polarity capacitor C2 and the like, and is characterized in that a negative electrode of the polarity capacitor C1 is connected with a positive electrode input end of the power amplifier P1, a positive electrode of the polarity capacitor C1 is grounded through a photodiode D1, one end of the resistor R1 is connected with the positive electrode of the polarity capacitor C1, the other end of the resistor R1 is grounded through a diode D2, a positive electrode of the polarity capacitor C2 is connected with a connection point of the resistor R1 and the diode D2, and a negative electrode of the polarity capacitor C2 is grounded. The amplified field intensity detection circuit is simple in overall structure, and very convenient in manufacture and use. Meanwhile, the amplified field intensity detection circuit caln also effectively reduce radio frequency interferences of the circuit itself and the outside world.
Description
Technical field
The present invention relates to a kind of amplifying circuit, specifically refer to a kind of amplifying type field intensity testing circuit.
Background technology
At present, widely, relevant voltage signal, current signal and other pulse signals are mainly carried out power amplification by according to demand in the utilization of power amplification circuit.But, traditional power amplification circuit is after carrying out power drive amplification, and not only the attenuation amplitude of its amplifying signal is comparatively large, but also can be subject to outside electromagnetic interference (EMI), and then make amplifying signal performance comparatively unstable, serious constrains using and promoting of its profound level.
Summary of the invention
The object of the invention is to overcome the defect of the comparatively large and amplified signal unstable properties of signal attenuation amplitude after the amplification that current power amplification circuit exists, a kind of amplifying type field intensity testing circuit is provided.
Object of the present invention is achieved through the following technical solutions: a kind of amplifying type field intensity testing circuit, by power amplifier P1, Sheffer stroke gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, integrated package U1, power amplifier P2, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C1 of positive pole ground connection after optical diode D1, one end is connected with the positive pole of polar capacitor C1, the resistance R1 of other end ground connection after diode D2, positive pole is connected with the tie point of diode D2 with resistance R1, the polar capacitor C2 of minus earth, one end is connected with the negative input of Sheffer stroke gate IC1, the resistance R2 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R3 between the negative input of power amplifier P1 and output terminal, one end is connected with the output terminal of Sheffer stroke gate IC1, the resistance R4 that the other end is connected with the negative input of Sheffer stroke gate IC3, positive pole is connected with the output terminal of Sheffer stroke gate IC2, the electric capacity C3 that negative pole is connected with the negative input of Sheffer stroke gate IC3, and one end is connected with the positive pole of polar capacitor C2, the resistance R5 that the other end is connected with the negative input of Sheffer stroke gate IC2, positive pole is connected with the DD pin of integrated package U1 after resistance R11, negative pole is in turn through resistance R12, resistance R15, diode D4, the polar capacitor C6 be connected with the COMP pin of integrated package U1 after resistance R13, N pole is connected with the negative pole of power amplifier P2 after resistance R10, P pole is in turn through resistance R9, polar capacitor C5, resistance R8, resistance R6, resistance R7, the diode D3 be connected with the positive pole of power amplifier P2 after electric capacity C4, base stage is connected with the SW pin of integrated package U1 after resistance R17, its emitter is in turn through resistance R14, resistance R16, be connected with the output terminal of power amplifier P2 after resistance R19, the triode Q1 of its grounded collector, one end is connected with the tie point of resistance R16 with resistance R14, the resistance R18 that the other end is connected with the COMP pin of integrated package U1 forms, the SENSE pin of described integrated package U1 is connected with the tie point of resistance R9 with electric capacity C5, its PWM pin is connected with the positive pole of electric capacity C6, its ADJ pin is connected with the negative pole of electric capacity C6, its IN pin is connected with resistance R8 tie point with resistance R6, its GND pin ground connection.
The tie point ground connection of described resistance R12 and resistance R15; The tie point of described resistance 14 and resistance R16 is as output terminal; The electrode input end of described Sheffer stroke gate IC1 is connected with the negative input of power amplifier P1, and its output terminal is connected with the electrode input end of Sheffer stroke gate IC2; The electrode input end of described Sheffer stroke gate IC3 is connected with the output terminal of power amplifier P1, and its output terminal is then connected with the tie point of resistance R8 with resistance R6.
For guaranteeing result of use, described integrated package U1 preferentially adopts SD42524 integrated circuit to realize.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) one-piece construction of the present invention is comparatively simple, and it makes and very easy to use.Meanwhile, the present invention can also effectively reduce circuit self and extraneous Radio frequency interference (RFI).
(2) the present invention can guarantee that larger decay can not occur the signal after it amplifies, thus can guarantee the quality and performance of amplifying signal.
Accompanying drawing explanation
Fig. 1 is one-piece construction schematic diagram of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1, the present invention is by power amplifier P1, Sheffer stroke gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, integrated package U1, power amplifier P2, polar capacitor C1, polar capacitor C2, electric capacity C3, electric capacity C4, polar capacitor C5, polar capacitor C6, optical diode D1, diode D2, diode D3, diode D4, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, and triode Q1 forms.
During connection, the negative pole of polar capacitor C1 is connected with the electrode input end of power amplifier P1, and its positive pole is then connected with the N pole of optical diode D1, the P pole then ground connection of optical diode D1.One end of resistance R1 is connected with the positive pole of polar capacitor C1, and its other end is ground connection after diode D2.
The positive pole of described polar capacitor C2 is connected with the tie point of diode D2 with resistance R1, its minus earth; One end of resistance R2 is connected with the negative input of Sheffer stroke gate IC1, and its other end is connected with the electrode input end of power amplifier P; Between the negative input that resistance R3 is then serially connected in power amplifier P and output terminal.
One end of resistance R4 is connected with the output terminal of Sheffer stroke gate IC1, and its other end is connected with the negative input of Sheffer stroke gate IC3; Meanwhile, the positive pole of electric capacity C3 is connected with the output terminal of Sheffer stroke gate IC2, and its negative pole is also connected with the negative input of Sheffer stroke gate IC3.One end of described resistance R5 is connected with the positive pole of polar capacitor C2, and its other end is connected with the negative input of Sheffer stroke gate IC2.
The electrode input end of described Sheffer stroke gate IC1 is connected with the negative input of power amplifier P1, and its output terminal is connected with the electrode input end of Sheffer stroke gate IC2; The electrode input end of Sheffer stroke gate IC3 is connected with the output terminal of power amplifier P1.
Meanwhile, the positive pole of polar capacitor C6 is connected with the DD pin of integrated package U1 after resistance R11, negative pole is connected with the COMP pin of integrated package U1 in turn after resistance R12, resistance R15, diode D4, resistance R13.The N pole of diode D3 is connected with the negative pole of power amplifier P2 after resistance R10, and its P pole is then connected with the positive pole of power amplifier P2 in turn after resistance R9, polar capacitor C5, resistance R8, resistance R6, resistance R7, electric capacity C4.
The base stage of triode Q1 is connected with the SW pin of integrated package U1 after resistance R17, its emitter is connected with the output terminal of power amplifier P2 in turn after resistance R14, resistance R16, resistance R19, its grounded collector.One end of resistance R18 is connected with the tie point of resistance R16 with resistance R14, the other end is connected with the COMP pin of integrated package U1.
The SENSE pin of described integrated package U1 is connected with the tie point of resistance R9 with electric capacity C5, its PWM pin is connected with the positive pole of electric capacity C6, its ADJ pin is connected with the negative pole of electric capacity C6, its IN pin is connected and its GND pin ground connection with resistance R8 tie point with resistance R6; The tie point ground connection of described resistance R12 and resistance R15; The tie point of described resistance 14 and resistance R16 is as output terminal;
For guaranteeing result of use of the present invention, this integrated package U1 preferentially adopts SD42524 integrated circuit to realize, and it has the function such as overcurrent protection, overtemperature prote.The input voltage range of this SD42524 integrated circuit is 6 ~ 36V, and current margin is 1.5 ~ 2mA, and maximum output current is 1A.
For guaranteeing result of use, the amount of this polar capacitor C1, polar capacitor C2, electric capacity polar capacitor C5, polar capacitor C6 is 10 μ F, electric capacity C3, electric capacity C4, electric capacity be then 5 μ F.Simultaneously, the resistance of resistance R1, resistance R2, resistance R3, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11 is 20K Ω, and the resistance of resistance R4, resistance R12, resistance R13, resistance R14, resistance R15 is 15K Ω, the resistance of resistance R5 is 25K Ω, and the resistance of resistance R16, resistance R17, resistance R18, resistance R19 is 30K Ω.
As mentioned above, just the present invention can well be realized.
Claims (2)
1. an amplifying type field intensity testing circuit, is characterized in that, by power amplifier P1, Sheffer stroke gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, and integrated package U1, power amplifier P2, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C1 of positive pole ground connection after optical diode D1, one end is connected with the positive pole of polar capacitor C1, the resistance R1 of other end ground connection after diode D2, positive pole is connected with the tie point of diode D2 with resistance R1, the polar capacitor C2 of minus earth, one end is connected with the negative input of Sheffer stroke gate IC1, the resistance R2 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R3 between the negative input of power amplifier P1 and output terminal, one end is connected with the output terminal of Sheffer stroke gate IC1, the resistance R4 that the other end is connected with the negative input of Sheffer stroke gate IC3, positive pole is connected with the output terminal of Sheffer stroke gate IC2, the electric capacity C3 that negative pole is connected with the negative input of Sheffer stroke gate IC3, and one end is connected with the positive pole of polar capacitor C2, the resistance R5 that the other end is connected with the negative input of Sheffer stroke gate IC2, positive pole is connected with the DD pin of integrated package U1 after resistance R11, negative pole is in turn through resistance R12, resistance R15, diode D4, the polar capacitor C6 be connected with the COMP pin of integrated package U1 after resistance R13, N pole is connected with the negative pole of power amplifier P2 after resistance R10, P pole is in turn through resistance R9, polar capacitor C5, resistance R8, resistance R6, resistance R7, the diode D3 be connected with the positive pole of power amplifier P2 after electric capacity C4, base stage is connected with the SW pin of integrated package U1 after resistance R17, its emitter is in turn through resistance R14, resistance R16, be connected with the output terminal of power amplifier P2 after resistance R19, the triode Q1 of its grounded collector, one end is connected with the tie point of resistance R16 with resistance R14, the resistance R18 that the other end is connected with the COMP pin of integrated package U1 forms, the SENSE pin of described integrated package U1 is connected with the tie point of resistance R9 with electric capacity C5, its PWM pin is connected with the positive pole of electric capacity C6, its ADJ pin is connected with the negative pole of electric capacity C6, its IN pin is connected with resistance R8 tie point with resistance R6, its GND pin ground connection, the tie point ground connection of described resistance R12 and resistance R15, the tie point of described resistance 14 and resistance R16 is as output terminal, the electrode input end of described Sheffer stroke gate IC1 is connected with the negative input of power amplifier P1, and its output terminal is connected with the electrode input end of Sheffer stroke gate IC2, the electrode input end of described Sheffer stroke gate IC3 is connected with the output terminal of power amplifier P1, and its output terminal is then connected with the tie point of resistance R8 with resistance R6.
2. a kind of amplifying type field intensity testing circuit according to claim 1, it is characterized in that, described integrated package U1 is SD42524 integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510316261.9A CN105182088A (en) | 2014-11-25 | 2015-06-11 | Amplified field intensity detection circuit |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410687555.8A CN104467706A (en) | 2014-11-25 | 2014-11-25 | Light beam excitation type logic amplification circuit |
| CN2014106875558 | 2014-11-25 | ||
| CN201510316261.9A CN105182088A (en) | 2014-11-25 | 2015-06-11 | Amplified field intensity detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105182088A true CN105182088A (en) | 2015-12-23 |
Family
ID=52913198
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410687555.8A Pending CN104467706A (en) | 2014-11-25 | 2014-11-25 | Light beam excitation type logic amplification circuit |
| CN201510316261.9A Withdrawn CN105182088A (en) | 2014-11-25 | 2015-06-11 | Amplified field intensity detection circuit |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410687555.8A Pending CN104467706A (en) | 2014-11-25 | 2014-11-25 | Light beam excitation type logic amplification circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN104467706A (en) |
-
2014
- 2014-11-25 CN CN201410687555.8A patent/CN104467706A/en active Pending
-
2015
- 2015-06-11 CN CN201510316261.9A patent/CN105182088A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| CN104467706A (en) | 2015-03-25 |
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| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20151223 |
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| WW01 | Invention patent application withdrawn after publication |